# OpenTimer shell commands to gate-size a design with six NAND2 cells
# and report timing/power/area values.
# 
# How to run: ../../bin/ot-shell < sizer.conf

# initialize the design
# the Nangate has X1, X2, and X3 for teh NAND2 cell
read_celllib NangateOpenCellLibrary_typical.lib
read_verilog sizer.v
read_spef sizer.spef
read_sdc sizer.sdc
report_timing
report_tns
report_wns
report_area
report_leakage_power

# downsize all gates from X2 to X1
repower_gate inst_0 NAND2_X1
repower_gate inst_1 NAND2_X1
repower_gate inst_2 NAND2_X1
repower_gate inst_3 NAND2_X1
repower_gate inst_4 NAND2_X1
repower_gate inst_5 NAND2_X1
report_timing
report_tns
report_wns
report_area
report_leakage_power

# upsize all gates from X1 to X4
repower_gate inst_0 NAND2_X4
repower_gate inst_1 NAND2_X4
repower_gate inst_2 NAND2_X4
repower_gate inst_3 NAND2_X4
repower_gate inst_4 NAND2_X4
repower_gate inst_5 NAND2_X4
report_timing
report_tns
report_wns
report_area
report_leakage_power

# dump the newest verilog and spef
dump_verilog -o sizer_opt.v -name sizer_opt
dump_spef -o sizer_opt.spef