There's really no need to switch VM contexts within cpu_switchto() as
MI code always calls pmap_deactivate/pmap_activate on context switch.

Instead, just record the last active lwp (or NULL if it ex

There's really no need to switch VM contexts within cpu_switchto() as
MI code always calls pmap_deactivate/pmap_activate on context switch.

Instead, just record the last active lwp (or NULL if it exited) and
defer switching VM context to pmap_activate(). This saves an additional
function call overhead in cpu_switchto().

While here, g/c unused cpuswitch.S local .Lblock_userspace_access.

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VFP support.

Optimize cpu_switchto to store the new PCB address in r7, rather than
loading it from memory in 3 places.

Also adjust ordering of a few loads to try and avoid stalling.

With the removal of IPKDB on arm, the undefined stack is only used to
bounce into SVC32 mode, there is no per-process data stored on it.

We can therefore use the undefined stack setup by the platfor

With the removal of IPKDB on arm, the undefined stack is only used to
bounce into SVC32 mode, there is no per-process data stored on it.

We can therefore use the undefined stack setup by the platform machdep.c
as a system wide undefined stack.

This removes the need for a per-process undefined stack, and the processor
mode switching overhead it causes in cpu_switchto.

The space freed in the USPACE is used to increase the per process kernel
stack size.

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Take a micro-optimization from FreeBSD/arm.

When switching from SVC32->UND32 to read/write R13_und we don't need to clear
the mode bits as:
PSR_SVC32_MODE | PSR_UND32_MODE = PSR_UND32_MODE

While re

Take a micro-optimization from FreeBSD/arm.

When switching from SVC32->UND32 to read/write R13_und we don't need to clear
the mode bits as:
PSR_SVC32_MODE | PSR_UND32_MODE = PSR_UND32_MODE

While reading the code I also noted that interrupts are enabled for most of
the function as pmap_switch returns with interrupts in the state they are on
entry. This appears to be different to what the code after pmap_switch
expects, in that the behaviour suggests they should be disabled.

Because of this I've made the writing of R13_und explicitly disable.
interupts as part of the mode switch.

This also means that the IRQenableALL call is now redundant as the
interrupts are already enabled.

XXX: it's not clear if arm_fpe_core_changecontext should be called with
interrupts disabled.

Remove unused items: IRQdisableALL, IRQenableALL & Lcpufuncs.

Tested on cats. lmbench shows no performance change.

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Add and fix a couple of comments.

Push a switchframe in dumpsys and cpu_switchto, but as dumpsys calls
other funcs a switchframe needs to be a multiple of 8 bytes. Stash sp as
well in the switchframe to bump it to 24bytes.

Setup the

Push a switchframe in dumpsys and cpu_switchto, but as dumpsys calls
other funcs a switchframe needs to be a multiple of 8 bytes. Stash sp as
well in the switchframe to bump it to 24bytes.

Setup the switchframe appropriately in cpu_lwp_fork.

Remove savectx - nothing uses it.

All of this make gdb's life much easier when dealing with crash dumps and
live kernels.

Reviewd by chris.

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Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the v

Merge the ppcoea-renovation branch to HEAD.

This branch was a major cleanup and rototill of many of the various OEA
cpu based PPC ports that focused on sharing as much code as possible
between the various ports to eliminate near-identical copies of files in
every tree. Additionally there is a new PIC system that unifies the
interface to interrupt code for all different OEA ppc arches. The work
for this branch was done by a variety of people, too long to list here.

TODO:
bebox still needs work to complete the transition to -renovation.
ofppc still needs a bunch of work, which I will be looking at.
ev64260 still needs to be renovated
amigappc was not attempted.

NOTES:
pmppc was removed as an arch, and moved to a evbppc target.

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ARM cpu_switchto() has been partially broken since yamt-idlelwp was merged
as its cache/tlb management smarts relied too heavily on pre-merge context-
switch behaviour. See PR kern/36548 for one mani

ARM cpu_switchto() has been partially broken since yamt-idlelwp was merged
as its cache/tlb management smarts relied too heavily on pre-merge context-
switch behaviour. See PR kern/36548 for one manifestation of the breakage.

To address this:
- Ditch the shadow pmap variables in the PCB (pagedir, l1vec, dacr, cstate)
as it was too easy for them to get out of sync with the pmap.
- Re-write (and fix) the convoluted cpuswitch.S cache/tlb ASM code in C.
It's only slightly less efficient, but is much more readable/maintainable.
- Document cpufuncs.cf_context_switch() as being C-callable.
- pmap_activate() becomes a no-op if the lwp's vmspace is already active.
(Good performance win, since pmap_activate() is now invoked on every
context-switch, even though ARM's cpu_switchto() already does all the
grunt work)

XXX: Some CPU-specific armXX_context_switch() implementations (arm67,
arm7tdmi, arm8) always flush the I+D caches. This should not be necessary.
Someone with access to hardware (acorn32?) needs to deal with this.

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No need to check if oldl == newl in cpu_switchto. All the callers ensure
this is never the case.

Fixup a few comments while I'm here.

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.

merge yamt-idlelwp branch. asked by core@. some ports still needs work.

from doc/BRANCHES:

idle lwp, and some changes depending on it.

1. separate context switching and thread scheduling.
(cf. gmcgarry_ctxsw)
2. implement idle lwp.
3. clean up related MD/MI interfaces.
4. make scheduler(s) modular.

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Get DOMAIN_CLIENT directly from arm/arm32/pte.h instead of from genassym
to avoid redefinition when both assymh and pte.h are included (as in
INTEGRATOR's intmmu.S, which uses more macros from pte.h).

Merge newlock2 to head.

Fix some more comments.

Fix some comments.

merge ktrace-lwp.

- Add LOCKDEBUG-protected calls to sched_lock_idle() to cpu_switchto and
the idle loop. They seem to have gone AWOL sometime in the past.
Fixes port-arm/23390.
- While here, tidy up the idle l

- Add LOCKDEBUG-protected calls to sched_lock_idle() to cpu_switchto and
the idle loop. They seem to have gone AWOL sometime in the past.
Fixes port-arm/23390.
- While here, tidy up the idle loop.
- Add a cheap DIAGNOSTIC check for run queue sanity.

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Fix a braino introduced in r1.37. Thanks to Tom Spindler for spotting it.

Remove p_nras from struct proc - use LIST_EMPTY(&p->p_raslist) instead.
Remove p_raslock and rename p_lwplock p_lock (one lock is enough).
Simplify window test when adding a ras and correct test on V

Remove p_nras from struct proc - use LIST_EMPTY(&p->p_raslist) instead.
Remove p_raslock and rename p_lwplock p_lock (one lock is enough).
Simplify window test when adding a ras and correct test on VM_MAXUSER_ADDRESS.
Avoid unpredictable branch in i386 locore.S
(pad fields left in struct proc to avoid kernel bump)

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Don't drop to spl0 in cpu_switch/cpu_switchto. Do it in the idle loop
instead.

With this change, we no longer need to save the current interrupt level
in the switchframe. This is no great loss since

Don't drop to spl0 in cpu_switch/cpu_switchto. Do it in the idle loop
instead.

With this change, we no longer need to save the current interrupt level
in the switchframe. This is no great loss since both cpu_switch and
cpu_switchto are always called at splsched, so the process' spl is
effectively saved somewhere in the callstack.

This fixes an evbarm problem reported by Allen Briggs:

lwp gets into sa_switch -> mi_switch with newl != NULL
when it's the last element on the runqueue, so it
hits the second bit of:
if (newl == NULL) {
retval = cpu_switch(l, NULL);
} else {
remrunqueue(newl);
cpu_switchto(l, newl);
retval = 0;
}

mi_switch calls remrunqueue() and cpu_switchto()

cpu_switchto unlocks the sched lock
cpu_switchto drops CPU priority
softclock is received
schedcpu is called from softclock
schedcpu hits the first if () {} block here:
if (l->l_priority >= PUSER) {
if (l->l_stat == LSRUN &&
(l->l_flag & L_INMEM) &&
(l->l_priority / PPQ) != (l->l_usrpri / PPQ)) {
remrunqueue(l);
l->l_priority = l->l_usrpri;
setrunqueue(l);
} else
l->l_priority = l->l_usrpri;
}

Since mi_switch has already run remrunqueue, the LWP has been
removed, but it's not been put back on any queue, so the
remrunqueue panics.

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A couple of Xscale tweaks:

- Use the "clz" instruction to pick a run-queue, instead of using the
ffs-by-table-lookup method.
- Use strd instead of stmia where possible.
- Use multiple ldr inst

A couple of Xscale tweaks:

- Use the "clz" instruction to pick a run-queue, instead of using the
ffs-by-table-lookup method.
- Use strd instead of stmia where possible.
- Use multiple ldr instructions instead of ldmia where possible.

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Make sure to include opt_foo.h if a defflag option FOO is used.

Fix for port-arm/21962. Rather than fixing the #ifndef spl0, I removed
the test as spl0 is actually a macro for splx(0). The code now calls
splx(0)

(note building with the #ifdef fixed, caused the

Fix for port-arm/21962. Rather than fixing the #ifndef spl0, I removed
the test as spl0 is actually a macro for splx(0). The code now calls
splx(0)

(note building with the #ifdef fixed, caused the build to fail on a
GENERIC acorn32 kernel.)

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Fix LINTSTUB comments.

Remove #ifdefs supporting the old pmap, switching fully to the new.