History log of /qemu/accel/ (Results 126 – 150 of 1193)
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e20f73fb12-Sep-2023 Anton Johansson <anjo@rev.ng>

accel/tcg: Unify user and softmmu do_[st|ld]*_mmu()

The prototype of do_[st|ld]*_mmu() is unified between system- and
user-mode allowing a large chunk of helper_[st|ld]*() and cpu_[st|ld]*()
functio

accel/tcg: Unify user and softmmu do_[st|ld]*_mmu()

The prototype of do_[st|ld]*_mmu() is unified between system- and
user-mode allowing a large chunk of helper_[st|ld]*() and cpu_[st|ld]*()
functions to be expressed in same manner between both modes. These
functions will be moved to ldst_common.c.inc in a following commit.

Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230912153428.17816-11-anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

73fda56f12-Sep-2023 Anton Johansson <anjo@rev.ng>

accel/tcg: Use CPUState in atomicity helpers

Makes ldst_atomicity.c.inc almost target-independent, with the exception
of TARGET_PAGE_MASK, which will be addressed in a future patch.

Signed-off-by:

accel/tcg: Use CPUState in atomicity helpers

Makes ldst_atomicity.c.inc almost target-independent, with the exception
of TARGET_PAGE_MASK, which will be addressed in a future patch.

Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230912153428.17816-8-anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

d560225f12-Sep-2023 Anton Johansson <anjo@rev.ng>

accel/tcg: Modify atomic_mmu_lookup() to use CPUState

The goal is to (in the future) allow for per-target compilation of
functions in atomic_template.h whilst atomic_mmu_lookup() and cputlb.c
are co

accel/tcg: Modify atomic_mmu_lookup() to use CPUState

The goal is to (in the future) allow for per-target compilation of
functions in atomic_template.h whilst atomic_mmu_lookup() and cputlb.c
are compiled once-per user- or system mode.

Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230912153428.17816-7-anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[rth: Use cpu->neg.tlb instead of cpu_tlb()]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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d50ef44612-Sep-2023 Anton Johansson <anjo@rev.ng>

accel/tcg: Modify memory access functions to use CPUState

do_[ld|st]*() and mmu_lookup*() are changed to use CPUState over
CPUArchState, moving the target-dependence to the target-facing facing
cpu_

accel/tcg: Modify memory access functions to use CPUState

do_[ld|st]*() and mmu_lookup*() are changed to use CPUState over
CPUArchState, moving the target-dependence to the target-facing facing
cpu_[ld|st] functions.

Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230912153428.17816-6-anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[rth: Use cpu->neg.tlb instead of cpu_tlb; cpu_env instead of env_ptr.]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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5afec1c612-Sep-2023 Anton Johansson <anjo@rev.ng>

accel/tcg: Modify probe_access_internal() to use CPUState

probe_access_internal() is changed to instead take the generic CPUState
over CPUArchState, in order to lessen the target-specific coupling o

accel/tcg: Modify probe_access_internal() to use CPUState

probe_access_internal() is changed to instead take the generic CPUState
over CPUArchState, in order to lessen the target-specific coupling of
cputlb.c. Note: probe_access*() also don't need the full CPUArchState,
but aren't touched in this patch as they are target-facing.

Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230912153428.17816-5-anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[rth: Use cpu->neg.tlb instead of cpu_tlb()]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

10b32e2c12-Sep-2023 Anton Johansson <anjo@rev.ng>

accel/tcg: Modify tlb_*() to use CPUState

Changes tlb_*() functions to take CPUState instead of CPUArchState, as
they don't require the full CPUArchState. This makes it easier to
decouple target-(in

accel/tcg: Modify tlb_*() to use CPUState

Changes tlb_*() functions to take CPUState instead of CPUArchState, as
they don't require the full CPUArchState. This makes it easier to
decouple target-(in)dependent code.

Signed-off-by: Anton Johansson <anjo@rev.ng>
Message-Id: <20230912153428.17816-4-anjo@rev.ng>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
[rth: Use cpu->neg.tlb instead of cpu_tlb()]
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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7857ee1114-Sep-2023 Richard Henderson <richard.henderson@linaro.org>

tcg: Remove TCGContext.tlb_fast_offset

Now that there is no padding between CPUNegativeOffsetState
and CPUArchState, this value is constant across all targets.

Reviewed-by: Anton Johansson <anjo@re

tcg: Remove TCGContext.tlb_fast_offset

Now that there is no padding between CPUNegativeOffsetState
and CPUArchState, this value is constant across all targets.

Reviewed-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

b77af26e14-Sep-2023 Richard Henderson <richard.henderson@linaro.org>

accel/tcg: Replace CPUState.env_ptr with cpu_env()

Reviewed-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>


tcg/cpu-exec.c
tcg/cputlb.c
tcg/plugin-gen.c
tcg/translate-all.c
/qemu/bsd-user/main.c
/qemu/bsd-user/signal.c
/qemu/gdbstub/gdbstub.c
/qemu/gdbstub/user-target.c
/qemu/hw/i386/kvm/clock.c
/qemu/hw/intc/mips_gic.c
/qemu/hw/intc/riscv_aclint.c
/qemu/hw/intc/riscv_imsic.c
/qemu/hw/ppc/e500.c
/qemu/hw/ppc/spapr.c
/qemu/include/exec/cpu-all.h
/qemu/include/hw/core/cpu.h
/qemu/linux-user/elfload.c
/qemu/linux-user/i386/cpu_loop.c
/qemu/linux-user/main.c
/qemu/linux-user/signal.c
/qemu/monitor/hmp-cmds-target.c
/qemu/semihosting/arm-compat-semi.c
/qemu/semihosting/syscalls.c
/qemu/target/alpha/translate.c
/qemu/target/arm/common-semi-target.h
/qemu/target/arm/cpu.c
/qemu/target/arm/helper.c
/qemu/target/arm/tcg/translate-a64.c
/qemu/target/arm/tcg/translate.c
/qemu/target/avr/translate.c
/qemu/target/cris/translate.c
/qemu/target/hexagon/translate.c
/qemu/target/hppa/mem_helper.c
/qemu/target/hppa/translate.c
/qemu/target/i386/nvmm/nvmm-all.c
/qemu/target/i386/tcg/decode-new.c.inc
/qemu/target/i386/tcg/sysemu/excp_helper.c
/qemu/target/i386/tcg/tcg-cpu.c
/qemu/target/i386/tcg/translate.c
/qemu/target/i386/whpx/whpx-all.c
/qemu/target/loongarch/translate.c
/qemu/target/m68k/translate.c
/qemu/target/microblaze/translate.c
/qemu/target/mips/tcg/sysemu/mips-semi.c
/qemu/target/mips/tcg/translate.c
/qemu/target/nios2/translate.c
/qemu/target/openrisc/translate.c
/qemu/target/ppc/excp_helper.c
/qemu/target/ppc/translate.c
/qemu/target/riscv/translate.c
/qemu/target/rx/cpu.c
/qemu/target/rx/translate.c
/qemu/target/s390x/tcg/translate.c
/qemu/target/sh4/op_helper.c
/qemu/target/sh4/translate.c
/qemu/target/sparc/translate.c
/qemu/target/tricore/translate.c
/qemu/target/xtensa/translate.c
ad75a51e13-Sep-2023 Richard Henderson <richard.henderson@linaro.org>

tcg: Rename cpu_env to tcg_env

Allow the name 'cpu_env' to be used for something else.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@li

tcg: Rename cpu_env to tcg_env

Allow the name 'cpu_env' to be used for something else.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...


tcg/plugin-gen.c
tcg/translator.c
/qemu/include/tcg/tcg.h
/qemu/target/alpha/translate.c
/qemu/target/arm/tcg/translate-a32.h
/qemu/target/arm/tcg/translate-a64.c
/qemu/target/arm/tcg/translate-a64.h
/qemu/target/arm/tcg/translate-m-nocp.c
/qemu/target/arm/tcg/translate-mve.c
/qemu/target/arm/tcg/translate-neon.c
/qemu/target/arm/tcg/translate-sme.c
/qemu/target/arm/tcg/translate-sve.c
/qemu/target/arm/tcg/translate-vfp.c
/qemu/target/arm/tcg/translate.c
/qemu/target/arm/tcg/translate.h
/qemu/target/avr/translate.c
/qemu/target/cris/translate.c
/qemu/target/cris/translate_v10.c.inc
/qemu/target/hexagon/README
/qemu/target/hexagon/gen_tcg.h
/qemu/target/hexagon/gen_tcg_funcs.py
/qemu/target/hexagon/gen_tcg_hvx.h
/qemu/target/hexagon/genptr.c
/qemu/target/hexagon/idef-parser/parser-helpers.c
/qemu/target/hexagon/macros.h
/qemu/target/hexagon/translate.c
/qemu/target/hppa/translate.c
/qemu/target/i386/tcg/decode-new.c.inc
/qemu/target/i386/tcg/emit.c.inc
/qemu/target/i386/tcg/translate.c
/qemu/target/loongarch/insn_trans/trans_atomic.c.inc
/qemu/target/loongarch/insn_trans/trans_branch.c.inc
/qemu/target/loongarch/insn_trans/trans_extra.c.inc
/qemu/target/loongarch/insn_trans/trans_farith.c.inc
/qemu/target/loongarch/insn_trans/trans_fcmp.c.inc
/qemu/target/loongarch/insn_trans/trans_fmemory.c.inc
/qemu/target/loongarch/insn_trans/trans_fmov.c.inc
/qemu/target/loongarch/insn_trans/trans_memory.c.inc
/qemu/target/loongarch/insn_trans/trans_privileged.c.inc
/qemu/target/loongarch/insn_trans/trans_vec.c.inc
/qemu/target/loongarch/translate.c
/qemu/target/m68k/translate.c
/qemu/target/microblaze/translate.c
/qemu/target/mips/tcg/lcsr_translate.c
/qemu/target/mips/tcg/micromips_translate.c.inc
/qemu/target/mips/tcg/msa_translate.c
/qemu/target/mips/tcg/mxu_translate.c
/qemu/target/mips/tcg/nanomips_translate.c.inc
/qemu/target/mips/tcg/translate.c
/qemu/target/mips/tcg/translate.h
/qemu/target/mips/tcg/vr54xx_translate.c
/qemu/target/nios2/translate.c
/qemu/target/openrisc/translate.c
/qemu/target/ppc/power8-pmu-regs.c.inc
/qemu/target/ppc/translate.c
/qemu/target/ppc/translate/branch-impl.c.inc
/qemu/target/ppc/translate/dfp-impl.c.inc
/qemu/target/ppc/translate/fixedpoint-impl.c.inc
/qemu/target/ppc/translate/fp-impl.c.inc
/qemu/target/ppc/translate/processor-ctrl-impl.c.inc
/qemu/target/ppc/translate/spe-impl.c.inc
/qemu/target/ppc/translate/storage-ctrl-impl.c.inc
/qemu/target/ppc/translate/vmx-impl.c.inc
/qemu/target/ppc/translate/vsx-impl.c.inc
/qemu/target/riscv/insn_trans/trans_privileged.c.inc
/qemu/target/riscv/insn_trans/trans_rvbf16.c.inc
/qemu/target/riscv/insn_trans/trans_rvd.c.inc
/qemu/target/riscv/insn_trans/trans_rvf.c.inc
/qemu/target/riscv/insn_trans/trans_rvh.c.inc
/qemu/target/riscv/insn_trans/trans_rvi.c.inc
/qemu/target/riscv/insn_trans/trans_rvm.c.inc
/qemu/target/riscv/insn_trans/trans_rvv.c.inc
/qemu/target/riscv/insn_trans/trans_rvvk.c.inc
/qemu/target/riscv/insn_trans/trans_rvzce.c.inc
/qemu/target/riscv/insn_trans/trans_rvzfa.c.inc
/qemu/target/riscv/insn_trans/trans_rvzfh.c.inc
/qemu/target/riscv/insn_trans/trans_rvzicbo.c.inc
/qemu/target/riscv/insn_trans/trans_svinval.c.inc
/qemu/target/riscv/insn_trans/trans_xthead.c.inc
/qemu/target/riscv/translate.c
/qemu/target/rx/translate.c
/qemu/target/s390x/tcg/translate.c
/qemu/target/s390x/tcg/translate_vx.c.inc
/qemu/target/sh4/translate.c
/qemu/target/sparc/translate.c
/qemu/target/tricore/translate.c
/qemu/target/xtensa/translate.c
/qemu/tcg/tcg-op-gvec.c
/qemu/tcg/tcg-op-ldst.c
/qemu/tcg/tcg-op.c
/qemu/tcg/tcg.c
a953b5fa13-Sep-2023 Richard Henderson <richard.henderson@linaro.org>

accel/tcg: Remove cpu_neg()

Now that CPUNegativeOffsetState is part of CPUState,
we can reference it directly.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henders

accel/tcg: Remove cpu_neg()

Now that CPUNegativeOffsetState is part of CPUState,
we can reference it directly.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

464dacf615-Sep-2023 Richard Henderson <richard.henderson@linaro.org>

accel/tcg: Move can_do_io to CPUNegativeOffsetState

Minimize the displacement to can_do_io, since it may
be touched at the start of each TranslationBlock.
It fits into other padding within the subst

accel/tcg: Move can_do_io to CPUNegativeOffsetState

Minimize the displacement to can_do_io, since it may
be touched at the start of each TranslationBlock.
It fits into other padding within the substructure.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

3b3d7df513-Sep-2023 Richard Henderson <richard.henderson@linaro.org>

accel/tcg: Move CPUNegativeOffsetState into CPUState

Retain the separate structure to emphasize its importance.
Enforce CPUArchState always follows CPUState without padding.

Reviewed-by: Anton Joha

accel/tcg: Move CPUNegativeOffsetState into CPUState

Retain the separate structure to emphasize its importance.
Enforce CPUArchState always follows CPUState without padding.

Reviewed-by: Anton Johansson <anjo@rev.ng>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

23af78b003-Oct-2023 Philippe Mathieu-Daudé <philmd@linaro.org>

accel/tcg: Restrict tcg_exec_[un]realizefn() to TCG

We don't need to expose these TCG-specific methods to the
whole code base. Register them as AccelClass handlers, they
will be called by the generi

accel/tcg: Restrict tcg_exec_[un]realizefn() to TCG

We don't need to expose these TCG-specific methods to the
whole code base. Register them as AccelClass handlers, they
will be called by the generic accel_cpu_[un]realize() methods.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20231003123026.99229-8-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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fa312f2e03-Oct-2023 Philippe Mathieu-Daudé <philmd@linaro.org>

accel/tcg: Have tcg_exec_realizefn() return a boolean

Following the example documented since commit e3fe3988d7 ("error:
Document Error API usage rules"), have tcg_exec_realizefn() return
a boolean i

accel/tcg: Have tcg_exec_realizefn() return a boolean

Following the example documented since commit e3fe3988d7 ("error:
Document Error API usage rules"), have tcg_exec_realizefn() return
a boolean indicating whether an error is set or not.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20231003123026.99229-7-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

5985186803-Oct-2023 Philippe Mathieu-Daudé <philmd@linaro.org>

accel: Declare AccelClass::cpu_common_[un]realize() handlers

Currently accel_cpu_realize() only performs target-specific
realization. Introduce the cpu_common_[un]realize fields in
the base AccelCla

accel: Declare AccelClass::cpu_common_[un]realize() handlers

Currently accel_cpu_realize() only performs target-specific
realization. Introduce the cpu_common_[un]realize fields in
the base AccelClass to be able to perform target-agnostic
[un]realization of vCPUs.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20231003123026.99229-6-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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1aa1d83003-Oct-2023 Philippe Mathieu-Daudé <philmd@linaro.org>

accel: Introduce accel_cpu_common_unrealize() stub

Prepare the stub for parity with accel_cpu_common_realize().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20231003123026

accel: Introduce accel_cpu_common_unrealize() stub

Prepare the stub for parity with accel_cpu_common_realize().

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20231003123026.99229-5-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

bd684b2f03-Oct-2023 Philippe Mathieu-Daudé <philmd@linaro.org>

accel: Rename accel_cpu_realize() -> accel_cpu_common_realize()

accel_cpu_realize() is a generic function working with CPUs
from any target. Rename it using '_common_' to emphasis it is
not target s

accel: Rename accel_cpu_realize() -> accel_cpu_common_realize()

accel_cpu_realize() is a generic function working with CPUs
from any target. Rename it using '_common_' to emphasis it is
not target specific.

Suggested-by: Claudio Fontana <cfontana@suse.de>

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20231003123026.99229-4-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

6294e50203-Oct-2023 Philippe Mathieu-Daudé <philmd@linaro.org>

accel: Rename AccelCPUClass::cpu_realizefn() -> cpu_target_realize()

The AccelCPUClass::cpu_realizefn handler is meant for target
specific code, rename it using '_target_' to emphasis it.

Suggested

accel: Rename AccelCPUClass::cpu_realizefn() -> cpu_target_realize()

The AccelCPUClass::cpu_realizefn handler is meant for target
specific code, rename it using '_target_' to emphasis it.

Suggested-by: Claudio Fontana <cfontana@suse.de>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-Id: <20231003123026.99229-3-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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e5dc722c03-Oct-2023 Philippe Mathieu-Daudé <philmd@linaro.org>

accel: Rename accel_cpu_realizefn() -> accel_cpu_realize()

We use the '*fn' suffix for handlers, this is a public method.
Drop the suffix.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>

accel: Rename accel_cpu_realizefn() -> accel_cpu_realize()

We use the '*fn' suffix for handlers, this is a public method.
Drop the suffix.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Claudio Fontana <cfontana@suse.de>
Message-Id: <20231003123026.99229-2-philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

show more ...

9a239c6e04-Sep-2023 Philippe Mathieu-Daudé <philmd@linaro.org>

tcg: Clean up local variable shadowing

Fix:

tcg/tcg.c:2551:27: error: declaration shadows a local variable [-Werror,-Wshadow]
MemOp op = get_memop(oi);

tcg: Clean up local variable shadowing

Fix:

tcg/tcg.c:2551:27: error: declaration shadows a local variable [-Werror,-Wshadow]
MemOp op = get_memop(oi);
^
tcg/tcg.c:2437:12: note: previous declaration is here
TCGOp *op;
^
accel/tcg/tb-maint.c:245:18: error: declaration shadows a local variable [-Werror,-Wshadow]
for (int i = 0; i < V_L2_SIZE; i++) {
^
accel/tcg/tb-maint.c:210:9: note: previous declaration is here
int i;
^

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20230904161235.84651-2-philmd@linaro.org>
Signed-off-by: Markus Armbruster <armbru@redhat.com>

show more ...

7191f24c01-Dec-2022 Akihiko Odaki <akihiko.odaki@daynix.com>

accel/kvm/kvm-all: Handle register access errors

A register access error typically means something seriously wrong
happened so that anything bad can happen after that and recovery is
impossible.
Eve

accel/kvm/kvm-all: Handle register access errors

A register access error typically means something seriously wrong
happened so that anything bad can happen after that and recovery is
impossible.
Even failing one register access is catastorophic as
architecture-specific code are not written so that it torelates such
failures.

Make sure the VM stop and nothing worse happens if such an error occurs.

Signed-off-by: Akihiko Odaki <akihiko.odaki@daynix.com>
Message-ID: <20221201102728.69751-1-akihiko.odaki@daynix.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>

show more ...

18a536f113-Sep-2023 Richard Henderson <richard.henderson@linaro.org>

accel/tcg: Always require can_do_io

Require i/o as the last insn of a TranslationBlock always,
not only with icount. This is required for i/o that alters
the address space, such as a pci config spa

accel/tcg: Always require can_do_io

Require i/o as the last insn of a TranslationBlock always,
not only with icount. This is required for i/o that alters
the address space, such as a pci config space write.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1866
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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200c1f9014-Sep-2023 Richard Henderson <richard.henderson@linaro.org>

accel/tcg: Always set CF_LAST_IO with CF_NOIRQ

Without this we can get see loops through cpu_io_recompile,
in which the cpu makes no progress.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org

accel/tcg: Always set CF_LAST_IO with CF_NOIRQ

Without this we can get see loops through cpu_io_recompile,
in which the cpu makes no progress.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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a2f99d4814-Sep-2023 Richard Henderson <richard.henderson@linaro.org>

accel/tcg: Improve setting of can_do_io at start of TB

Initialize can_do_io to true if this the TB has CF_LAST_IO
and will consist of a single instruction. This avoids a
set to 0 followed immediate

accel/tcg: Improve setting of can_do_io at start of TB

Initialize can_do_io to true if this the TB has CF_LAST_IO
and will consist of a single instruction. This avoids a
set to 0 followed immediately by a set to 1.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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0ca41ccf14-Sep-2023 Richard Henderson <richard.henderson@linaro.org>

accel/tcg: Track current value of can_do_io in the TB

Simplify translator_io_start by recording the current
known value of can_do_io within DisasContextBase.

Reviewed-by: Philippe Mathieu-Daudé <ph

accel/tcg: Track current value of can_do_io in the TB

Simplify translator_io_start by recording the current
known value of can_do_io within DisasContextBase.

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>

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