| db7e8b1f | 05-Mar-2024 |
Alex Bennée <alex.bennee@linaro.org> |
target/riscv: honour show_opcodes when disassembling
This makes the output suitable when used for plugins.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <
target/riscv: honour show_opcodes when disassembling
This makes the output suitable when used for plugins.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240305121005.3528075-30-alex.bennee@linaro.org>
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| 7cff154b | 05-Mar-2024 |
Alex Bennée <alex.bennee@linaro.org> |
disas/hppa: honour show_opcodes
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240305121005.3528075-28-alex.bennee@l
disas/hppa: honour show_opcodes
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Message-Id: <20240305121005.3528075-28-alex.bennee@linaro.org>
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| 251385fd | 26-Oct-2023 |
Max Chou <max.chou@sifive.com> |
disas/riscv: Replace TABs with space
Replaces TABs with spaces, making sure to have a consistent coding style
of 4 space indentations.
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alista
disas/riscv: Replace TABs with space
Replaces TABs with spaces, making sure to have a consistent coding style
of 4 space indentations.
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231026151828.754279-15-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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| 9d92f56d | 26-Oct-2023 |
Max Chou <max.chou@sifive.com> |
disas/riscv: Add support for vector crypto extensions
This patch adds following v1.0.0 ratified vector crypto extensions
support to the RISC-V disassembler.
- Zvbb
- Zvbc
- Zvkb
- Zvkg
- Zvkned
- Zv
disas/riscv: Add support for vector crypto extensions
This patch adds following v1.0.0 ratified vector crypto extensions
support to the RISC-V disassembler.
- Zvbb
- Zvbc
- Zvkb
- Zvkg
- Zvkned
- Zvknha
- Zvknhb
- Zvksed
- Zvksh
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20231026151828.754279-14-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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| 434c609b | 26-Oct-2023 |
Max Chou <max.chou@sifive.com> |
disas/riscv: Add rv_codec_vror_vi for vror.vi
Add rv_codec_vror_vi for the vector crypto instruction - vror.vi.
The rotate amount of vror.vi is defined by combining seperated bits.
Signed-off-by: M
disas/riscv: Add rv_codec_vror_vi for vror.vi
Add rv_codec_vror_vi for the vector crypto instruction - vror.vi.
The rotate amount of vror.vi is defined by combining seperated bits.
Signed-off-by: Max Chou <max.chou@sifive.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231026151828.754279-13-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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| a47842d1 | 10-Jul-2023 |
Christoph Müllner <christoph.muellner@vrull.eu> |
riscv: Add support for the Zfa extension
This patch introduces the RISC-V Zfa extension, which introduces
additional floating-point instructions:
* fli (load-immediate) with pre-defined immediates
*
riscv: Add support for the Zfa extension
This patch introduces the RISC-V Zfa extension, which introduces
additional floating-point instructions:
* fli (load-immediate) with pre-defined immediates
* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)
* fround/froundmx (round to integer)
* fcvtmod.w.d (Modular Convert-to-Integer)
* fmv* to access high bits of float register bigger than XLEN
* Quiet comparison instructions (fleq/fltq)
Zfa defines its instructions in combination with the following extensions:
* single-precision floating-point (F)
* double-precision floating-point (D)
* quad-precision floating-point (Q)
* half-precision floating-point (Zfh)
Since QEMU does not support the RISC-V quad-precision floating-point
ISA extension (Q), this patch does not include the instructions that
depend on this extension. All other instructions are included in this
patch.
The Zfa specification can be found here:
https://github.com/riscv/riscv-isa-manual/blob/master/src/zfa.tex
The Zfa specifciation is frozen and is in public review since May 3, 2023:
https://groups.google.com/a/groups.riscv.org/g/isa-dev/c/SED4ntBkabg
The patch also includes a TCG test for the fcvtmod.w.d instruction.
The test cases test for correct results and flag behaviour.
Note, that the Zfa specification requires fcvtmod's flag behaviour
to be identical to a fcvt with the same operands (which is also
tested).
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230710071243.282464-1-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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| 318df723 | 12-Jun-2023 |
Christoph Müllner <christoph.muellner@vrull.eu> |
disas/riscv: Add support for XThead* instructions
Support for emulating XThead* instruction has been added recently.
This patch adds support for these instructions to the RISC-V disassembler.
Co-de
disas/riscv: Add support for XThead* instructions
Support for emulating XThead* instruction has been added recently.
This patch adds support for these instructions to the RISC-V disassembler.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230612111034.3955227-9-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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| f6f72338 | 12-Jun-2023 |
Christoph Müllner <christoph.muellner@vrull.eu> |
disas/riscv: Add support for XVentanaCondOps
This patch adds XVentanaCondOps support to the RISC-V disassembler.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Franci
disas/riscv: Add support for XVentanaCondOps
This patch adds XVentanaCondOps support to the RISC-V disassembler.
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Message-Id: <20230612111034.3955227-8-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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| c859a242 | 12-Jun-2023 |
Christoph Müllner <christoph.muellner@vrull.eu> |
disas/riscv: Provide infrastructure for vendor extensions
A previous patch provides a pointer to the RISCVCPUConfig data.
Let's use this to add the necessary code for vendor extensions.
This patch d
disas/riscv: Provide infrastructure for vendor extensions
A previous patch provides a pointer to the RISCVCPUConfig data.
Let's use this to add the necessary code for vendor extensions.
This patch does not change the current behaviour, but clearly
defines how vendor extension support can be added to the disassembler.
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230612111034.3955227-7-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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| fd7c64f6 | 12-Jun-2023 |
Christoph Müllner <christoph.muellner@vrull.eu> |
disas/riscv: Encapsulate opcode_data into decode
This patch adds a reference to a struct rv_opcode_data object
into struct rv_decode. This further allows to remove all references
to the global varia
disas/riscv: Encapsulate opcode_data into decode
This patch adds a reference to a struct rv_opcode_data object
into struct rv_decode. This further allows to remove all references
to the global variable opcode_data (which is renamed to rvi_opcode_data).
This patch does not introduce any functional change, but prepares
the code for more struct rv_opcode_data objects in the future.
This patch is based on previous work from Liu Zhiwei:
https://lists.nongnu.org/archive/html/qemu-devel/2022-08/msg03662.html
Co-developed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230612111034.3955227-6-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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| 01b1361f | 12-Jun-2023 |
Christoph Müllner <christoph.muellner@vrull.eu> |
disas/riscv: Make rv_op_illegal a shared enum value
The enum value 'rv_op_illegal' does not represent an
instruction, but is a catch-all value in case we have
no match in the decoder. Let's make the
disas/riscv: Make rv_op_illegal a shared enum value
The enum value 'rv_op_illegal' does not represent an
instruction, but is a catch-all value in case we have
no match in the decoder. Let's make the value a shared
one, so that other compile units can reuse it.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>
Signed-off-by: Christoph Müllner <christoph.muellner@vrull.eu>
Message-Id: <20230612111034.3955227-5-christoph.muellner@vrull.eu>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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