#
ab5e8605 |
| 25-May-2022 |
Peter Delevoryas <pdel@fb.com> |
hw: aspeed: Add missing UART's
This adds the missing UART memory and IRQ mappings for the AST2400, AST2500, AST2600, and AST1030.
This also includes the new UART interfaces added in the AST2600 and
hw: aspeed: Add missing UART's
This adds the missing UART memory and IRQ mappings for the AST2400, AST2500, AST2600, and AST1030.
This also includes the new UART interfaces added in the AST2600 and AST1030 from UART6 to UART13. The addresses and interrupt numbers for these two later chips are identical.
Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220516062328.298336-2-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
699db715 |
| 25-May-2022 |
Cédric Le Goater <clg@kaod.org> |
aspeed: Introduce a get_irq AspeedSoCClass method
and make routine aspeed_soc_get_irq() common to all SoCs. This will be useful to share code.
Cc: Jamin Lin <jamin_lin@aspeedtech.com> Cc: Peter Del
aspeed: Introduce a get_irq AspeedSoCClass method
and make routine aspeed_soc_get_irq() common to all SoCs. This will be useful to share code.
Cc: Jamin Lin <jamin_lin@aspeedtech.com> Cc: Peter Delevoryas <pdel@fb.com> Reviewed-by: Peter Delevoryas <pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220516055620.2380197-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
470253b6 |
| 25-May-2022 |
Peter Delevoryas <pdel@fb.com> |
hw: aspeed: Introduce common UART init function
Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220516062328.298336-5-pdel@fb.com> Signed-of
hw: aspeed: Introduce common UART init function
Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220516062328.298336-5-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
c5e1bdb9 |
| 25-May-2022 |
Peter Delevoryas <pdel@fb.com> |
hw: aspeed: Add uarts_num SoC attribute
AST2400 and AST2500 have 5 UART's, while the AST2600 and AST1030 have 13.
Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@ka
hw: aspeed: Add uarts_num SoC attribute
AST2400 and AST2500 have 5 UART's, while the AST2600 and AST1030 have 13.
Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220516062328.298336-3-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
ab5e8605 |
| 25-May-2022 |
Peter Delevoryas <pdel@fb.com> |
hw: aspeed: Add missing UART's
This adds the missing UART memory and IRQ mappings for the AST2400, AST2500, AST2600, and AST1030.
This also includes the new UART interfaces added in the AST2600 and
hw: aspeed: Add missing UART's
This adds the missing UART memory and IRQ mappings for the AST2400, AST2500, AST2600, and AST1030.
This also includes the new UART interfaces added in the AST2600 and AST1030 from UART6 to UART13. The addresses and interrupt numbers for these two later chips are identical.
Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220516062328.298336-2-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
699db715 |
| 25-May-2022 |
Cédric Le Goater <clg@kaod.org> |
aspeed: Introduce a get_irq AspeedSoCClass method
and make routine aspeed_soc_get_irq() common to all SoCs. This will be useful to share code.
Cc: Jamin Lin <jamin_lin@aspeedtech.com> Cc: Peter Del
aspeed: Introduce a get_irq AspeedSoCClass method
and make routine aspeed_soc_get_irq() common to all SoCs. This will be useful to share code.
Cc: Jamin Lin <jamin_lin@aspeedtech.com> Cc: Peter Delevoryas <pdel@fb.com> Reviewed-by: Peter Delevoryas <pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220516055620.2380197-1-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
fe31a2ec |
| 02-May-2022 |
Joel Stanley <joel@jms.id.au> |
aspeed: Add eMMC Boot Controller stub
Guest code (u-boot) pokes at this on boot. No functionality is required for guest code to work correctly, but it helps to document the region being read from.
aspeed: Add eMMC Boot Controller stub
Guest code (u-boot) pokes at this on boot. No functionality is required for guest code to work correctly, but it helps to document the region being read from.
Signed-off-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20220318092211.723938-1-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
Revision tags: v7.0.0, v7.0.0-rc4, v7.0.0-rc3, v7.0.0-rc2, v7.0.0-rc1, v7.0.0-rc0 |
|
#
8d99713b |
| 08-Mar-2022 |
Cédric Le Goater <clg@kaod.org> |
aspeed/smc: Remove 'num_cs' field
It is not used anymore.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220307071856.
aspeed/smc: Remove 'num_cs' field
It is not used anymore.
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20220307071856.1410731-4-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
e1acf581 |
| 18-Feb-2022 |
Joel Stanley <joel@jms.id.au> |
ast2600: Add Secure Boot Controller model
Just a stub that indicates the system has booted in secure boot mode. Used for testing the driver:
https://lore.kernel.org/all/20211019080608.283324-1-joe
ast2600: Add Secure Boot Controller model
Just a stub that indicates the system has booted in secure boot mode. Used for testing the driver:
https://lore.kernel.org/all/20211019080608.283324-1-joel@jms.id.au/
Signed-off-by: Joel Stanley <joel@jms.id.au> [ clg: - Fixed typo - Adjusted Copyright dates ] Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
08048cbd |
| 26-Jan-2022 |
Cédric Le Goater <clg@kaod.org> |
hw/arm: ast2600: Fix address mapping of second SPI controller
Address should be 0x1E631000 and not 0x1E641000 as initially introduced.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/838 Fi
hw/arm: ast2600: Fix address mapping of second SPI controller
Address should be 0x1E631000 and not 0x1E641000 as initially introduced.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/838 Fixes: f25c0ae1079d ("aspeed/soc: Add AST2600 support") Suggested-by: Troy Lee <troy_lee@aspeedtech.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-id: 20220126083520.4135713-1-clg@kaod.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
#
3222165d |
| 11-Jan-2022 |
Troy Lee <troy_lee@aspeedtech.com> |
hw/arm/aspeed: Add the i3c device to the AST2600 SoC
Add the new i3c device to the AST2600 SoC.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Reviewed-by: Graeme Gregory <quic_ggregory@quicinc.
hw/arm/aspeed: Add the i3c device to the AST2600 SoC
Add the new i3c device to the AST2600 SoC.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Reviewed-by: Graeme Gregory <quic_ggregory@quicinc.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Tested-by: Graeme Gregory <quic_ggregory@quicinc.com> Message-id: 20220111084546.4145785-3-troy_lee@aspeedtech.com [PMM: tidied commit message] Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
#
d9e9cd59 |
| 07-Jan-2022 |
Troy Lee <troy_lee@aspeedtech.com> |
Add dummy Aspeed AST2600 Display Port MCU (DPMCU)
AST2600 Display Port MCU introduces 0x18000000~0x1803FFFF as it's memory and io address. If guest machine try to access DPMCU memory, it will cause
Add dummy Aspeed AST2600 Display Port MCU (DPMCU)
AST2600 Display Port MCU introduces 0x18000000~0x1803FFFF as it's memory and io address. If guest machine try to access DPMCU memory, it will cause a fatal error.
Signed-off-by: Troy Lee <troy_lee@aspeedtech.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-id: 20211210083034.726610-1-troy_lee@aspeedtech.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
show more ...
|
Revision tags: v6.1.1, v6.2.0, v6.2.0-rc4, v6.2.0-rc3, v6.2.0-rc2, v6.2.0-rc1, v6.2.0-rc0, v6.0.1 |
|
#
199fd623 |
| 12-Oct-2021 |
Andrew Jeffery <andrew@aj.id.au> |
hw/arm: Integrate ADC model into Aspeed SoC
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Delevoryas <pdel@fb.com> Message-Id: <
hw/arm: Integrate ADC model into Aspeed SoC
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Peter Delevoryas <pdel@fb.com> Message-Id: <20211005052604.1674891-3-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
60261038 |
| 12-Oct-2021 |
Cédric Le Goater <clg@kaod.org> |
aspeed/i2c: QOMify AspeedI2CBus
Introduce an AspeedI2CBus SysBusDevice model and attach the associated memory region and IRQ to the newly instantiated objects.
Before this change, the I2C bus IRQs
aspeed/i2c: QOMify AspeedI2CBus
Introduce an AspeedI2CBus SysBusDevice model and attach the associated memory region and IRQ to the newly instantiated objects.
Before this change, the I2C bus IRQs were all attached to the SysBusDevice model of the I2C controller. Adapt the AST2600 SoC realize routine to take into account this change.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
30b6852c |
| 12-Oct-2021 |
Cédric Le Goater <clg@kaod.org> |
aspeed/smc: Drop AspeedSMCController structure
The characteristics of the Aspeed controllers are described in a AspeedSMCController structure which is redundant with the AspeedSMCClass. Move all att
aspeed/smc: Drop AspeedSMCController structure
The characteristics of the Aspeed controllers are described in a AspeedSMCController structure which is redundant with the AspeedSMCClass. Move all attributes under the class and adapt the code to use class attributes instead.
This is a large change but it is functionally equivalent.
Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
5d63d0c7 |
| 20-Sep-2021 |
Peter Delevoryas <pdel@fb.com> |
hw/arm/aspeed: Allow machine to set UART default
When you run QEMU with an Aspeed machine and a single serial device using stdio like this:
qemu -machine ast2600-evb -drive ... -serial stdio
T
hw/arm/aspeed: Allow machine to set UART default
When you run QEMU with an Aspeed machine and a single serial device using stdio like this:
qemu -machine ast2600-evb -drive ... -serial stdio
The guest OS can read and write to the UART5 registers at 0x1E784000 and it will receive from stdin and write to stdout. The Aspeed SoC's have a lot more UART's though (AST2500 has 5, AST2600 has 13) and depending on the board design, may be using any of them as the serial console. (See "stdout-path" in a DTS to check which one is chosen).
Most boards, including all of those currently defined in hw/arm/aspeed.c, just use UART5, but some use UART1. This change adds some flexibility for different boards without requiring users to change their command-line invocation of QEMU.
I tested this doesn't break existing code by booting an AST2500 OpenBMC image and an AST2600 OpenBMC image, each using UART5 as the console.
Then I tested switching the default to UART1 and booting an AST2600 OpenBMC image that uses UART1, and that worked too.
Signed-off-by: Peter Delevoryas <pdel@fb.com> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210901153615.2746885-2-pdel@fb.com> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
c5811bb3 |
| 20-Sep-2021 |
Joel Stanley <joel@jms.id.au> |
aspeed: Emulate the AST2600A3
This is the latest revision of the ASPEED 2600 SoC. As there is no need to model multiple revisions of the same SoC for the moment, update the SCU AST2600 to model the
aspeed: Emulate the AST2600A3
This is the latest revision of the ASPEED 2600 SoC. As there is no need to model multiple revisions of the same SoC for the moment, update the SCU AST2600 to model the A3 revision instead of the A1 and adapt the AST2600 SoC and machines.
Reset values are taken from v8 of the datasheet.
Signed-off-by: Joel Stanley <joel@jms.id.au> [ clg: - Introduced an Aspeed "ast2600-a3" SoC class - Commit log update ] Message-Id: <20210629142336.750058-3-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
Revision tags: v6.1.0, v6.1.0-rc4, v6.1.0-rc3, v6.1.0-rc2, v6.1.0-rc1, v6.1.0-rc0, v6.0.0, v6.0.0-rc5, v6.0.0-rc4 |
|
#
ee86213a |
| 16-Apr-2021 |
Thomas Huth <thuth@redhat.com> |
Do not include exec/address-spaces.h if it's not really necessary
Stop including exec/address-spaces.h in files that don't need it.
Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <202104
Do not include exec/address-spaces.h if it's not really necessary
Stop including exec/address-spaces.h in files that don't need it.
Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210416171314.2074665-5-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
show more ...
|
#
2068cabd |
| 16-Apr-2021 |
Thomas Huth <thuth@redhat.com> |
Do not include cpu.h if it's not really necessary
Stop including cpu.h in files that don't need it.
Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210416171314.2074665-4-thuth@redhat.
Do not include cpu.h if it's not really necessary
Stop including cpu.h in files that don't need it.
Signed-off-by: Thomas Huth <thuth@redhat.com> Message-Id: <20210416171314.2074665-4-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
show more ...
|
Revision tags: v6.0.0-rc3, v6.0.0-rc2, v6.0.0-rc1 |
|
#
19f4ed36 |
| 28-Mar-2021 |
Thomas Huth <thuth@redhat.com> |
hw: Do not include qemu/log.h if it is not necessary
Many files include qemu/log.h without needing it. Remove the superfluous include statements.
Signed-off-by: Thomas Huth <thuth@redhat.com> Revie
hw: Do not include qemu/log.h if it is not necessary
Many files include qemu/log.h without needing it. Remove the superfluous include statements.
Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-Id: <20210328054833.2351597-1-thuth@redhat.com> Signed-off-by: Laurent Vivier <laurent@vivier.eu>
show more ...
|
#
8efbee28 |
| 01-May-2021 |
Cédric Le Goater <clg@kaod.org> |
hw/misc/aspeed_xdma: Add AST2600 support
When we introduced support for the AST2600 SoC, the XDMA controller was forgotten. It went unnoticed because it's not used under emulation. But the register
hw/misc/aspeed_xdma: Add AST2600 support
When we introduced support for the AST2600 SoC, the XDMA controller was forgotten. It went unnoticed because it's not used under emulation. But the register layout being different, the reset procedure is bogus and this breaks kexec.
Add a AspeedXDMAClass to take into account the register differences.
Cc: Eddie James <eajames@linux.ibm.com> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Eddie James <eajames@linux.ibm.com> Message-Id: <20210407171637.777743-14-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
a3888d75 |
| 01-May-2021 |
Joel Stanley <joel@jms.id.au> |
aspeed: Integrate HACE
Add the hash and crypto engine model to the Aspeed socs.
Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Math
aspeed: Integrate HACE
Add the hash and crypto engine model to the Aspeed socs.
Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Reviewed-by: Klaus Heinrich Kiwi <klaus@linux.vnet.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Message-Id: <20210409000253.1475587-3-joel@jms.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
d177892d |
| 01-May-2021 |
Cédric Le Goater <clg@kaod.org> |
aspeed/smc: Remove unused "sdram-base" property
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Mess
aspeed/smc: Remove unused "sdram-base" property
Cc: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Message-Id: <20210407171637.777743-3-clg@kaod.org> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
Revision tags: v6.0.0-rc0 |
|
#
c59f781e |
| 09-Mar-2021 |
Andrew Jeffery <andrew@aj.id.au> |
hw/misc: Model KCS devices in the Aspeed LPC controller
Keyboard-Controller-Style devices for IPMI purposes are exposed via LPC IO cycles from the BMC to the host.
Expose support on the BMC side by
hw/misc: Model KCS devices in the Aspeed LPC controller
Keyboard-Controller-Style devices for IPMI purposes are exposed via LPC IO cycles from the BMC to the host.
Expose support on the BMC side by implementing the usual MMIO behaviours, and expose the ability to inspect the KCS registers in "host" style by accessing QOM properties associated with each register.
The model caters to the IRQ style of both the AST2600 and the earlier SoCs (AST2400 and AST2500). The AST2600 allocates an IRQ for each LPC sub-device, while there is a single IRQ shared across all subdevices on the AST2400 and AST2500.
Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Cédric Le Goater <clg@kaod.org> Message-Id: <20210302014317.915120-6-andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|
#
2ecf1726 |
| 09-Mar-2021 |
Cédric Le Goater <clg@kaod.org> |
hw/misc: Add a basic Aspeed LPC controller model
This is a very minimal framework to access registers which are used to configure the AHB memory mapping of the flash chips on the LPC HC Firmware add
hw/misc: Add a basic Aspeed LPC controller model
This is a very minimal framework to access registers which are used to configure the AHB memory mapping of the flash chips on the LPC HC Firmware address space.
Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Message-Id: <20210302014317.915120-5-andrew@aj.id.au> Signed-off-by: Cédric Le Goater <clg@kaod.org>
show more ...
|