f58db4ee | 23-Oct-2023 |
Zhao Liu <zhao1.liu@intel.com> |
tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count2 test
Following the guidelines in tests/qtest/bios-tables-test.c, this is step 5 and 6.
Changes in the tables: FACP:
tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count2 test
Following the guidelines in tests/qtest/bios-tables-test.c, this is step 5 and 6.
Changes in the tables: FACP:
+/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-CNE3C2, Mon Oct 23 15:25:01 2023 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0002 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 1 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000484A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 1 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-WKE3C2, Mon Oct 23 15:25:01 2023 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000CA6 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 2C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0
[snip]
+[434h 1076 1] Subtable Type : 00 [Processor Local APIC] +[435h 1077 1] Length : 08 +[436h 1078 1] Processor ID : 81 +[437h 1079 1] Local Apic ID : 81 +[438h 1080 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[43Ch 1084 1] Subtable Type : 09 [Processor Local x2APIC] +[43Dh 1085 1] Length : 10 +[43Eh 1086 2] Reserved : 0000 +[440h 1088 4] Processor x2Apic ID : 00000100 +[444h 1092 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 +[448h 1096 4] Processor UID : 00000082
[snip]
+[C4Ch 3148 1] Subtable Type : 09 [Processor Local x2APIC] +[C4Dh 3149 1] Length : 10 +[C4Eh 3150 2] Reserved : 0000 +[C50h 3152 4] Processor x2Apic ID : 00000181 +[C54h 3156 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 +[C58h 3160 4] Processor UID : 00000103 + +[C5Ch 3164 1] Subtable Type : 01 [I/O APIC] +[C5Dh 3165 1] Length : 0C +[C5Eh 3166 1] I/O Apic ID : 00 +[C5Fh 3167 1] Reserved : 00 +[C60h 3168 4] Address : FEC00000 +[C64h 3172 4] Interrupt : 00000000 + +[C68h 3176 1] Subtable Type : 02 [Interrupt Source Override] +[C69h 3177 1] Length : 0A +[C6Ah 3178 1] Bus : 00 +[C6Bh 3179 1] Source : 00 +[C6Ch 3180 4] Interrupt : 00000002 +[C70h 3184 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0
[snip]
+[C90h 3216 1] Subtable Type : 02 [Interrupt Source Override] +[C91h 3217 1] Length : 0A +[C92h 3218 1] Bus : 00 +[C93h 3219 1] Source : 0B +[C94h 3220 4] Interrupt : 0000000B +[C98h 3224 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[C9Ah 3226 1] Subtable Type : 0A [Local x2APIC NMI] +[C9Bh 3227 1] Length : 0C +[C9Ch 3228 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[C9Eh 3230 4] Processor UID : FFFFFFFF +[CA2h 3234 1] Interrupt Input LINT : 01 +[CA3h 3235 3] Reserved : 000000
...
DSDT:
+/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of /tmp/aml-CDE3C2, Mon Oct 23 15:25:01 2023 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x000083EA (33770) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x01 + * OEM ID "BOCHS " + * OEM Table ID "BXPC " + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + }
[snip]
+ Processor (C081, 0x81, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x81)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x81, 0x81, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x81) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x81, Arg0, Arg1, Arg2) + } + }
...
Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20231023094635.1588282-17-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
show more ...
|
198eee0c | 23-Oct-2023 |
Zhao Liu <zhao1.liu@intel.com> |
tests: bios-tables-test: Add test for smbios type4 thread count2
This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in type4").
In smbios_build_type_4_table() (hw/smbios/smbios.c), i
tests: bios-tables-test: Add test for smbios type4 thread count2
This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in type4").
In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of threads in the socket is more than 255, then smbios type4 table encodes threads per socket into the thread count2 field.
So for the topology in this case, there're the following considerations: 1. threads per socket should be more than 255 to ensure we could cover the thread count2 field. 2. The original bug was that threads per socket was miscalculated, so now we should configure as many topology levels as possible (multiple dies, no module since x86 hasn't supported it) to cover more general topology scenarios, to ensure that the threads per socket encoded in the thread count2 field is correct. 3. For the more general topology, we should also add "cpus" (presented threads for machine) and "maxcpus" (total threads for machine) to make sure that configuring unpluged CPUs in smp (cpus < maxcpus) does not affect the correctness of threads per socket for thread count2 field.
Note we don't consider the topology with multiple sockets since this topology would create too many vCPUs (more than 255 threads per socket with at least 2 sockets, which may cause the failure "Number of hotpluggable cpus requested (*) exceeds the maximum cpus supported by KVM (*) socket_accept failed: Resource temporarily unavailable"), and the calculation of threads per socket has already been covered by "thread count" test case.
Based on these considerations, select the topology as the follow:
-smp cpus=210,maxcpus=260,dies=2,cores=65,threads=2
The expected thread count2 = threads per socket = threads (2) * cores (65) * dies (2) = 260.
Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Message-Id: <20231023094635.1588282-16-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
show more ...
|
a775cb19 | 23-Oct-2023 |
Zhao Liu <zhao1.liu@intel.com> |
tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count test
Following the guidelines in tests/qtest/bios-tables-test.c, this is step 5 and 6.
Changes in the tables: FACP:
+
tests: bios-tables-test: Add ACPI table binaries for smbios type4 thread count test
Following the guidelines in tests/qtest/bios-tables-test.c, this is step 5 and 6.
Changes in the tables: FACP:
+/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-1NP791, Wed Aug 23 21:51:31 2023 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0002 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 1 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000484A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 1 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000
...
APIC:
+/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembly of /tmp/aml-2JP791, Wed Aug 23 21:51:31 2023 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000220 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 63 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPC " +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0
[snip]
+[1D4h 0468 1] Subtable Type : 00 [Processor Local APIC] +[1D5h 0469 1] Length : 08 +[1D6h 0470 1] Processor ID : 35 +[1D7h 0471 1] Local Apic ID : 6A +[1D8h 0472 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[1DCh 0476 1] Subtable Type : 01 [I/O APIC] +[1DDh 0477 1] Length : 0C +[1DEh 0478 1] I/O Apic ID : 00 +[1DFh 0479 1] Reserved : 00 +[1E0h 0480 4] Address : FEC00000 +[1E4h 0484 4] Interrupt : 00000000 + +[1E8h 0488 1] Subtable Type : 02 [Interrupt Source Override] +[1E9h 0489 1] Length : 0A +[1EAh 0490 1] Bus : 00 +[1EBh 0491 1] Source : 00 +[1ECh 0492 4] Interrupt : 00000002 +[1F0h 0496 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[1F2h 0498 1] Subtable Type : 02 [Interrupt Source Override] +[1F3h 0499 1] Length : 0A +[1F4h 0500 1] Bus : 00 +[1F5h 0501 1] Source : 05 +[1F6h 0502 4] Interrupt : 00000005 +[1FAh 0506 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[1FCh 0508 1] Subtable Type : 02 [Interrupt Source Override] +[1FDh 0509 1] Length : 0A +[1FEh 0510 1] Bus : 00 +[1FFh 0511 1] Source : 09 +[200h 0512 4] Interrupt : 00000009 +[204h 0516 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[206h 0518 1] Subtable Type : 02 [Interrupt Source Override] +[207h 0519 1] Length : 0A +[208h 0520 1] Bus : 00 +[209h 0521 1] Source : 0A +[20Ah 0522 4] Interrupt : 0000000A +[20Eh 0526 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[210h 0528 1] Subtable Type : 02 [Interrupt Source Override] +[211h 0529 1] Length : 0A +[212h 0530 1] Bus : 00 +[213h 0531 1] Source : 0B +[214h 0532 4] Interrupt : 0000000B +[218h 0536 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[21Ah 0538 1] Subtable Type : 04 [Local APIC NMI] +[21Bh 0539 1] Length : 06 +[21Ch 0540 1] Processor ID : FF +[21Dh 0541 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[21Fh 0543 1] Interrupt Input LINT : 01
...
DSDT:
+/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20200925 (64-bit version) + * Copyright (c) 2000 - 2020 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of /tmp/aml-00O791, Wed Aug 23 21:51:31 2023 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00003271 (12913) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0xAF + * OEM ID "BOCHS " + * OEM Table ID "BXPC " + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPC ", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + }
[snip]
+ Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + }
[snip]
+ Processor (C035, 0x35, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x35)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x35, 0x6A, 0x01, 0x00, 0x00, 0x00 // ..5j.... + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x35) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x35, Arg0, Arg1, Arg2) + } + }
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Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-14-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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7ee18dce | 23-Oct-2023 |
Zhao Liu <zhao1.liu@intel.com> |
tests: bios-tables-test: Add test for smbios type4 thread count
This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in type4").
In smbios_build_type_4_table() (hw/smbios/smbios.c), if
tests: bios-tables-test: Add test for smbios type4 thread count
This tests the commit 7298fd7de5551 ("hw/smbios: Fix thread count in type4").
In smbios_build_type_4_table() (hw/smbios/smbios.c), if the number of threads in the socket is not more than 255, then smbios type4 table encodes threads per socket into the thread count field.
So for the topology in this case, there're the following considerations: 1. threads per socket should be not more than 255 to ensure we could cover the thread count field. 2. The original bug was that threads per socket was miscalculated, so now we should configure as many topology levels as possible (multiple sockets & dies, no module since x86 hasn't supported it) to cover more general topology scenarios, to ensure that the threads per socket encoded in the thread count field is correct. 3. For the more general topology, we should also add "cpus" (presented threads for machine) and "maxcpus" (total threads for machine) to make sure that configuring unpluged CPUs in smp (cpus < maxcpus) does not affect the correctness of threads per socket for thread count field.
Based on these considerations, select the topology as the follow:
-smp cpus=15,maxcpus=54,sockets=2,dies=3,cores=3,threads=3
The expected thread count = threads per socket = threads (3) * cores (3) * dies (3) = 27.
Suggested-by: Igor Mammedov <imammedo@redhat.com> Signed-off-by: Zhao Liu <zhao1.liu@intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Message-Id: <20231023094635.1588282-13-zhao1.liu@linux.intel.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
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