Lines Matching refs:l4
8 l4 : std_logic_vector (3 downto 0); port
43 sub_u4u3u <= std_logic_vector (unsigned'(unsigned(l4) - unsigned(r3)));
44 sub_s4s3s <= std_logic_vector (signed'(signed(l4) - signed(r3)));
45 sub_u4s3s <= std_logic_vector (signed'(unsigned(l4) - signed(r3)));
46 sub_s4u3s <= std_logic_vector (signed'(signed(l4) - unsigned(r3)));
47 sub_u4iu <= std_logic_vector (unsigned'(unsigned(l4) - ri));
49 sub_s4is <= std_logic_vector (signed'(signed(l4) - ri));
51 sub_u4lu <= std_logic_vector (unsigned'(unsigned(l4) - r3(0)));
52 sub_lu3u <= std_logic_vector (unsigned'(l4(0) - unsigned(r3)));
53 sub_s4ls <= std_logic_vector (signed'(signed(l4) - r3(0)));
54 sub_ls3s <= std_logic_vector (signed'(l4(0) - signed(r3)));
56 sub_u4u3v <= unsigned(l4) - unsigned(r3);
57 sub_s4s3v <= signed(l4) - signed(r3);
58 sub_u4s3v <= unsigned(l4) - signed(r3);
59 sub_s4u3v <= signed(l4) - unsigned(r3);
60 sub_u4iv <= unsigned(l4) - ri;
62 sub_s4iv <= signed(l4) - ri;
64 sub_u4lv <= unsigned(l4) - r3(0);
65 sub_lu3v <= l4(0) - unsigned(r3);
66 sub_s4lv <= signed(l4) - r3(0);
67 sub_ls3v <= l4(0) - signed(r3);