Lines Matching refs:GetSize
76 for (int i = GetSize(sig_y)-1; i >= 0; i--) in run_cell_mux()
79 if (!info->is_output && GetSize(info->ports) <= 1 && !keep_bits.count(mi.sigmap(sig_y[i]))) { in run_cell_mux()
85 for (int k = 0; k < GetSize(sig_s); k++) { in run_cell_mux()
86 …onfig->keepdc || (ref != State::Sx && sig_b[k*GetSize(sig_a) + i] != State::Sx)) && ref != sig_b[k… in run_cell_mux()
88 if (sig_b[k*GetSize(sig_a) + i] != State::Sx) in run_cell_mux()
89 ref = sig_b[k*GetSize(sig_a) + i]; in run_cell_mux()
101 for (int i = GetSize(bits_removed)-1; i >= 0; i--) in run_cell_mux()
104 if (GetSize(bits_removed) == GetSize(sig_y)) { in run_cell_mux()
112 GetSize(sig_removed), GetSize(sig_y), log_id(module), log_id(cell), log_id(cell->type)); in run_cell_mux()
114 int n_removed = GetSize(sig_removed); in run_cell_mux()
115 int n_kept = GetSize(sig_y) - GetSize(sig_removed); in run_cell_mux()
125 for (int k = 0; k < GetSize(sig_s); k++) { in run_cell_mux()
126 new_sig_b.append(sig_b.extract(k*GetSize(sig_a), n_kept)); in run_cell_mux()
127 new_work_queue_bits.append(sig_b.extract(k*GetSize(sig_a) + n_kept, n_removed)); in run_cell_mux()
150 int width_before = GetSize(sig_q); in run_cell_dff()
163 bool zero_ext = sig_d[GetSize(sig_d)-1] == State::S0; in run_cell_dff()
166 for (int i = GetSize(sig_q)-1; i >= 0; i--) in run_cell_dff()
169 …(!has_reset || i >= GetSize(rst_value) || rst_value[i] == State::S0 || rst_value[i] == State::Sx))… in run_cell_dff()
178 (!has_reset || i >= GetSize(rst_value) || rst_value[i] == rst_value[i-1])) { in run_cell_dff()
189 if (!info->is_output && GetSize(info->ports) == 1 && !keep_bits.count(mi.sigmap(sig_q[i]))) { in run_cell_dff()
201 if (width_before == GetSize(sig_q)) in run_cell_dff()
204 if (GetSize(sig_q) == 0) { in run_cell_dff()
210 …log("Removed top %d bits (of %d) from FF cell %s.%s (%s).\n", width_before - GetSize(sig_q), width… in run_cell_dff()
221 rst_value.bits.resize(GetSize(sig_q)); in run_cell_dff()
224 rst_value.bits.resize(GetSize(sig_q)); in run_cell_dff()
242 if (GetSize(sig) > max_port_size) { in run_reduce_inport()
243 bits_removed = GetSize(sig) - max_port_size; in run_reduce_inport()
250 while (GetSize(sig) > 1 && sig[GetSize(sig)-1] == sig[GetSize(sig)-2]) in run_reduce_inport()
251 work_queue_bits.insert(sig[GetSize(sig)-1]), sig.remove(GetSize(sig)-1), bits_removed++; in run_reduce_inport()
253 while (GetSize(sig) > 1 && sig[GetSize(sig)-1] == State::S0) in run_reduce_inport()
254 work_queue_bits.insert(sig[GetSize(sig)-1]), sig.remove(GetSize(sig)-1), bits_removed++; in run_reduce_inport()
259 …bits_removed, GetSize(sig) + bits_removed, port, log_id(module), log_id(cell), log_id(cell->type)); in run_reduce_inport()
286 int max_port_a_size = cell->hasPort(ID::A) ? GetSize(cell->getPort(ID::A)) : -1; in run_cell()
287 int max_port_b_size = cell->hasPort(ID::B) ? GetSize(cell->getPort(ID::B)) : -1; in run_cell()
290 max_port_a_size = min(max_port_a_size, GetSize(sig)); in run_cell()
291 max_port_b_size = min(max_port_b_size, GetSize(sig)); in run_cell()
305 if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0 && in run_cell()
306 GetSize(sig_b) > 0 && sig_b[GetSize(sig_b)-1] == State::S0) { in run_cell()
319 if (GetSize(sig_a) > 0 && sig_a[GetSize(sig_a)-1] == State::S0) { in run_cell()
335 while (GetSize(sig) > 0) in run_cell()
337 auto bit = sig[GetSize(sig)-1]; in run_cell()
342 if (info->is_output || GetSize(info->ports) > 1) in run_cell()
345 sig.remove(GetSize(sig)-1); in run_cell()
355 if (cell->hasPort(ID::A)) a_size = GetSize(cell->getPort(ID::A)); in run_cell()
356 if (cell->hasPort(ID::B)) b_size = GetSize(cell->getPort(ID::B)); in run_cell()
366 while (GetSize(sig) > 1 && GetSize(sig) > max_y_size) { in run_cell()
367 module->connect(sig[GetSize(sig)-1], is_signed ? sig[GetSize(sig)-2] : State::S0); in run_cell()
368 sig.remove(GetSize(sig)-1); in run_cell()
373 if (GetSize(sig) == 0) { in run_cell()
381 bits_removed, GetSize(sig) + bits_removed, log_id(module), log_id(cell), log_id(cell->type)); in run_cell()
439 for (int i = GetSize(w)-1; i >= 0; i--) { in run()
442 if (info && (info->is_input || info->is_output || GetSize(info->ports) > 0)) in run()
447 if (unused_top_bits == 0 || unused_top_bits == GetSize(w)) in run()
450 if (complete_wires[mi.sigmap(w).extract(0, GetSize(w) - unused_top_bits)]) in run()
453 …log("Removed top %d bits (of %d) from wire %s.%s.\n", unused_top_bits, GetSize(w), log_id(module),… in run()
454 Wire *nw = module->addWire(NEW_ID, GetSize(w) - unused_top_bits); in run()
455 module->connect(nw, SigSpec(w).extract(0, GetSize(nw))); in run()
516 ID($logic_not), ID($logic_and), ID($logic_or)) && GetSize(c->getPort(ID::Y)) > 1) { in execute()
522 module->connect(sig, Const(0, GetSize(sig))); in execute()
529 int original_a_width = GetSize(A); in execute()
531 while (GetSize(A) > 1 && A[GetSize(A)-1] == State::S0 && A[GetSize(A)-2] == State::S0) in execute()
532 A.remove(GetSize(A)-1, 1); in execute()
534 while (GetSize(A) > 0 && A[GetSize(A)-1] == State::S0) in execute()
535 A.remove(GetSize(A)-1, 1); in execute()
537 if (original_a_width != GetSize(A)) { in execute()
539 original_a_width-GetSize(A), original_a_width, log_id(module), log_id(c), log_id(c->type)); in execute()
541 c->setParam(ID::A_WIDTH, GetSize(A)); in execute()
545 int original_b_width = GetSize(B); in execute()
547 while (GetSize(B) > 1 && B[GetSize(B)-1] == State::S0 && B[GetSize(B)-2] == State::S0) in execute()
548 B.remove(GetSize(B)-1, 1); in execute()
550 while (GetSize(B) > 0 && B[GetSize(B)-1] == State::S0) in execute()
551 B.remove(GetSize(B)-1, 1); in execute()
553 if (original_b_width != GetSize(B)) { in execute()
555 original_b_width-GetSize(B), original_b_width, log_id(module), log_id(c), log_id(c->type)); in execute()
557 c->setParam(ID::B_WIDTH, GetSize(B)); in execute()