Lines Matching refs:inv_a
73 bool inv_a, inv_b, inv_y; member
77 bool inv_a, inv_b, inv_c, inv_y; member
103 f2i.inv_a = ia; in ExtractFaWorker()
110 bool a = (i & 1) ? !f2i.inv_a : f2i.inv_a; in ExtractFaWorker()
131 f3i.inv_a = ia; in ExtractFaWorker()
139 bool a = (i & 1) ? !f3i.inv_a : f3i.inv_a; in ExtractFaWorker()
348 f3i.inv_a = !f3i.inv_a; in run()
354 if (!f3i.inv_a && !f3i.inv_b && !f3i.inv_c && !f3i.inv_y) { in run()
358 if (f3i.inv_a) log(" A"); in run()
371 if (f3i.inv_a) fakey |= 1; in run()
402 cell->setPort(ID::A, f3i.inv_a ? module->NotGate(NEW_ID, A) : A); in run()
462 if (!f2i.inv_a && !f2i.inv_b && !f2i.inv_y) { in run()
466 if (f2i.inv_a) log(" A"); in run()
478 if (f2i.inv_a) fakey |= 1; in run()
508 cell->setPort(ID::A, f2i.inv_a ? module->NotGate(NEW_ID, A) : A); in run()
520 …SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? module->NotGate(… in run()
526 …SigBit YY = invert_xy || (f2i.inv_a && !f2i.inv_b) || (!f2i.inv_a && f2i.inv_b) ? Y : module->NotG… in run()