techlibs/xilinx/cells_sim.v

1491   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4  port
1496   wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
1533     (A4 => SPO) = 238; (DPRA4 => DPO) = 238;
1550   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4  port
1555   wire [4:0] dpra = {DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
1583     (A4 => SPO) = 238; (DPRA4 => DPO) = 238;
1596   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5  port
1601   wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
1641     (A4 => SPO) = 238; (DPRA4 => DPO) = 238;
1654   input  DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5  port
1659   wire [5:0] dpra = {DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0};
1689     (A4 => SPO) = 238; (DPRA4 => DPO) = 238;