Lines Matching refs:wb_dat_o
80 wb_clk_i, wb_rst_i, arst_i, wb_adr_i, wb_dat_i, wb_dat_o,
97 output [7:0] wb_dat_o; // databus output port
104 reg [7:0] wb_dat_o; register
166 3'b000: wb_dat_o <= #1 prer[ 7:0];
167 3'b001: wb_dat_o <= #1 prer[15:8];
168 3'b010: wb_dat_o <= #1 ctr;
169 3'b011: wb_dat_o <= #1 rxr; // write is transmit register (txr)
170 3'b100: wb_dat_o <= #1 sr; // write is command register (cr)
171 3'b101: wb_dat_o <= #1 txr;
172 3'b110: wb_dat_o <= #1 cr;
173 3'b111: wb_dat_o <= #1 0; // reserved