include/opcode/i960.h

111 #define RSL	OP( 0, LIT, 0,  SFR )  macro
284 	{ R_3(0x580),	"notbit",	I_BASE,	REG,	3, { RSL,RSL,RS } },
285 	{ R_3(0x581),	"and",		I_BASE,	REG,	3, { RSL,RSL,RS } },
286 	{ R_3(0x582),	"andnot",	I_BASE,	REG,	3, { RSL,RSL,RS } },
287 	{ R_3(0x583),	"setbit",	I_BASE,	REG,	3, { RSL,RSL,RS } },
288 	{ R_3(0x584),	"notand",	I_BASE,	REG,	3, { RSL,RSL,RS } },
289 	{ R_3(0x586),	"xor",		I_BASE,	REG,	3, { RSL,RSL,RS } },
290 	{ R_3(0x587),	"or",		I_BASE,	REG,	3, { RSL,RSL,RS } },
291 	{ R_3(0x588),	"nor",		I_BASE,	REG,	3, { RSL,RSL,RS } },
292 	{ R_3(0x589),	"xnor",		I_BASE,	REG,	3, { RSL,RSL,RS } },
293 	{ R_2D(0x58a),	"not",		I_BASE,	REG,	2, { RSL,RS, 0 } },
294 	{ R_3(0x58b),	"ornot",	I_BASE,	REG,	3, { RSL,RSL,RS } },
295 	{ R_3(0x58c),	"clrbit",	I_BASE,	REG,	3, { RSL,RSL,RS } },
296 	{ R_3(0x58d),	"notor",	I_BASE,	REG,	3, { RSL,RSL,RS } },
297 	{ R_3(0x58e),	"nand",		I_BASE,	REG,	3, { RSL,RSL,RS } },
298 	{ R_3(0x58f),	"alterbit",	I_BASE,	REG,	3, { RSL,RSL,RS } },
299 	{ R_3(0x590),	"addo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
300 	{ R_3(0x591),	"addi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
301 	{ R_3(0x592),	"subo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
302 	{ R_3(0x593),	"subi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
303 	{ R_3(0x598),	"shro",		I_BASE,	REG,	3, { RSL,RSL,RS } },
304 	{ R_3(0x59a),	"shrdi",	I_BASE,	REG,	3, { RSL,RSL,RS } },
305 	{ R_3(0x59b),	"shri",		I_BASE,	REG,	3, { RSL,RSL,RS } },
306 	{ R_3(0x59c),	"shlo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
307 	{ R_3(0x59d),	"rotate",	I_BASE,	REG,	3, { RSL,RSL,RS } },
308 	{ R_3(0x59e),	"shli",		I_BASE,	REG,	3, { RSL,RSL,RS } },
309 	{ R_2(0x5a0),	"cmpo",		I_BASE,	REG,	2, { RSL,RSL, 0 } },
310 	{ R_2(0x5a1),	"cmpi",		I_BASE,	REG,	2, { RSL,RSL, 0 } },
311 	{ R_2(0x5a2),	"concmpo",	I_BASE,	REG,	2, { RSL,RSL, 0 } },
312 	{ R_2(0x5a3),	"concmpi",	I_BASE,	REG,	2, { RSL,RSL, 0 } },
313 	{ R_3(0x5a4),	"cmpinco",	I_BASE,	REG,	3, { RSL,RSL,RS } },
314 	{ R_3(0x5a5),	"cmpinci",	I_BASE,	REG,	3, { RSL,RSL,RS } },
315 	{ R_3(0x5a6),	"cmpdeco",	I_BASE,	REG,	3, { RSL,RSL,RS } },
316 	{ R_3(0x5a7),	"cmpdeci",	I_BASE,	REG,	3, { RSL,RSL,RS } },
317 	{ R_2(0x5ac),	"scanbyte",	I_BASE,	REG,	2, { RSL,RSL, 0 } },
318 	{ R_2(0x5ae),	"chkbit",	I_BASE,	REG,	2, { RSL,RSL, 0 } },
319 	{ R_3(0x5b0),	"addc",		I_BASE,	REG,	3, { RSL,RSL,RS } },
320 	{ R_3(0x5b2),	"subc",		I_BASE,	REG,	3, { RSL,RSL,RS } },
321 	{ R_2D(0x5cc),	"mov",		I_BASE,	REG,	2, { RSL,RS, 0 } },
325 	{ R_3(0x610),	"atmod",	I_BASE,	REG,	3, { RS, RSL,R } },
326 	{ R_3(0x612),	"atadd",	I_BASE,	REG,	3, { RS, RSL,RS } },
327 	{ R_2D(0x640),	"spanbit",	I_BASE,	REG,	2, { RSL,RS, 0 } },
328 	{ R_2D(0x641),	"scanbit",	I_BASE,	REG,	2, { RSL,RS, 0 } },
329 	{ R_3(0x645),	"modac",	I_BASE,	REG,	3, { RSL,RSL,RS } },
330 	{ R_3(0x650),	"modify",	I_BASE,	REG,	3, { RSL,RSL,R } },
331 	{ R_3(0x651),	"extract",	I_BASE,	REG,	3, { RSL,RSL,R } },
332 	{ R_3(0x654),	"modtc",	I_BASE,	REG,	3, { RSL,RSL,RS } },
333 	{ R_3(0x655),	"modpc",	I_BASE,	REG,	3, { RSL,RSL,R } },
334 	{ R_1(0x660),	"calls",	I_BASE,	REG,	1, { RSL, 0, 0 } },
339 	{ R_3(0x670),	"emul",		I_BASE,	REG,	3, { RSL,RSL,R2 } },
340 	{ R_3(0x671),	"ediv",		I_BASE,	REG,	3, { RSL,RL2,RS } },
342 	{ R_3(0x701),	"mulo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
343 	{ R_3(0x708),	"remo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
344 	{ R_3(0x70b),	"divo",		I_BASE,	REG,	3, { RSL,RSL,RS } },
345 	{ R_3(0x741),	"muli",		I_BASE,	REG,	3, { RSL,RSL,RS } },
346 	{ R_3(0x748),	"remi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
347 	{ R_3(0x749),	"modi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
348 	{ R_3(0x74b),	"divi",		I_BASE,	REG,	3, { RSL,RSL,RS } },
417 	{ R_3(0x642),	"daddc",	I_DEC,	REG,	3, { RSL,RSL,RS } },
418 	{ R_3(0x643),	"dsubc",	I_DEC,	REG,	3, { RSL,RSL,RS } },
419 	{ R_2D(0x644),	"dmovt",	I_DEC,	REG,	2, { RSL,RS, 0 } },
453 	{ R_3(0x5d8),	"eshro",	I_CX2,	REG,	3, { RSL,RSL,RS } },
454 	{ R_3(0x630),	"sdma",		I_CX,	REG,	3, { RSL,RSL,RL } },
456 	{ R_3(0x659),	"sysctl",	I_CX2,	REG,	3, { RSL,RSL,RL } },
460 	{ R_3(0x780),	"addono",	I_JX,	REG,	3, { RSL,RSL,RS } },
461 	{ R_3(0x790),	"addog",	I_JX,	REG,	3, { RSL,RSL,RS } },
462 	{ R_3(0x7a0),	"addoe",	I_JX,	REG,	3, { RSL,RSL,RS } },
463 	{ R_3(0x7b0),	"addoge",	I_JX,	REG,	3, { RSL,RSL,RS } },
464 	{ R_3(0x7c0),	"addol",	I_JX,	REG,	3, { RSL,RSL,RS } },
465 	{ R_3(0x7d0),	"addone",	I_JX,	REG,	3, { RSL,RSL,RS } },
466 	{ R_3(0x7e0),	"addole",	I_JX,	REG,	3, { RSL,RSL,RS } },
467 	{ R_3(0x7f0),	"addoo",	I_JX,	REG,	3, { RSL,RSL,RS } },
468 	{ R_3(0x781),	"addino",	I_JX,	REG,	3, { RSL,RSL,RS } },
469 	{ R_3(0x791),	"addig",	I_JX,	REG,	3, { RSL,RSL,RS } },
470 	{ R_3(0x7a1),	"addie",	I_JX,	REG,	3, { RSL,RSL,RS } },
471 	{ R_3(0x7b1),	"addige",	I_JX,	REG,	3, { RSL,RSL,RS } },
472 	{ R_3(0x7c1),	"addil",	I_JX,	REG,	3, { RSL,RSL,RS } },
473 	{ R_3(0x7d1),	"addine",	I_JX,	REG,	3, { RSL,RSL,RS } },
474 	{ R_3(0x7e1),	"addile",	I_JX,	REG,	3, { RSL,RSL,RS } },
475 	{ R_3(0x7f1),	"addio",	I_JX,	REG,	3, { RSL,RSL,RS } },
477 	{ R_2D(0x5ad),	"bswap",	I_JX,	REG,	2, { RSL, RS, 0 } },
479 	{ R_2(0x594),	"cmpob",	I_JX,	REG,	2, { RSL,RSL, 0 } },
480 	{ R_2(0x595),	"cmpib",	I_JX,	REG,	2, { RSL,RSL, 0 } },
481 	{ R_2(0x596),	"cmpos",	I_JX,	REG,	2, { RSL,RSL, 0 } },
482 	{ R_2(0x597),	"cmpis",	I_JX,	REG,	2, { RSL,RSL, 0 } },
484 	{ R_3(0x784),	"selno",	I_JX,	REG,	3, { RSL,RSL,RS } },
485 	{ R_3(0x794),	"selg",		I_JX,	REG,	3, { RSL,RSL,RS } },
486 	{ R_3(0x7a4),	"sele",		I_JX,	REG,	3, { RSL,RSL,RS } },
487 	{ R_3(0x7b4),	"selge",	I_JX,	REG,	3, { RSL,RSL,RS } },
488 	{ R_3(0x7c4),	"sell",		I_JX,	REG,	3, { RSL,RSL,RS } },
489 	{ R_3(0x7d4),	"selne",	I_JX,	REG,	3, { RSL,RSL,RS } },
490 	{ R_3(0x7e4),	"selle",	I_JX,	REG,	3, { RSL,RSL,RS } },
491 	{ R_3(0x7f4),	"selo",		I_JX,	REG,	3, { RSL,RSL,RS } },
493 	{ R_3(0x782),	"subono",	I_JX,	REG,	3, { RSL,RSL,RS } },
494 	{ R_3(0x792),	"subog",	I_JX,	REG,	3, { RSL,RSL,RS } },
495 	{ R_3(0x7a2),	"suboe",	I_JX,	REG,	3, { RSL,RSL,RS } },
496 	{ R_3(0x7b2),	"suboge",	I_JX,	REG,	3, { RSL,RSL,RS } },
497 	{ R_3(0x7c2),	"subol",	I_JX,	REG,	3, { RSL,RSL,RS } },
498 	{ R_3(0x7d2),	"subone",	I_JX,	REG,	3, { RSL,RSL,RS } },
499 	{ R_3(0x7e2),	"subole",	I_JX,	REG,	3, { RSL,RSL,RS } },
500 	{ R_3(0x7f2),	"suboo",	I_JX,	REG,	3, { RSL,RSL,RS } },
501 	{ R_3(0x783),	"subino",	I_JX,	REG,	3, { RSL,RSL,RS } },
502 	{ R_3(0x793),	"subig",	I_JX,	REG,	3, { RSL,RSL,RS } },
503 	{ R_3(0x7a3),	"subie",	I_JX,	REG,	3, { RSL,RSL,RS } },
504 	{ R_3(0x7b3),	"subige",	I_JX,	REG,	3, { RSL,RSL,RS } },
505 	{ R_3(0x7c3),	"subil",	I_JX,	REG,	3, { RSL,RSL,RS } },
506 	{ R_3(0x7d3),	"subine",	I_JX,	REG,	3, { RSL,RSL,RS } },
507 	{ R_3(0x7e3),	"subile",	I_JX,	REG,	3, { RSL,RSL,RS } },
508 	{ R_3(0x7f3),	"subio",	I_JX,	REG,	3, { RSL,RSL,RS } },
510 	{ R_3(0x65c),	"dcctl",	I_JX,	REG,	3, { RSL,RSL,RL } },
511 	{ R_3(0x65b),	"icctl",	I_JX,	REG,	3, { RSL,RSL,RS } },
512 	{ R_2D(0x658),	"intctl",	I_JX,	REG,	2, { RSL, RS, 0 } },
515 	{ R_0(0x65d),	"halt",		I_JX,	REG,	1, { RSL,  0, 0 } },