Lines Matching refs:ShiftImm
213 uint64_t ShiftImm, bool SetFlags = false,
218 uint64_t ShiftImm, bool SetFlags = false,
246 AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
254 uint64_t ShiftImm);
1360 unsigned ShiftImm; in emitAddSub_ri() local
1362 ShiftImm = 0; in emitAddSub_ri()
1364 ShiftImm = 12; in emitAddSub_ri()
1393 .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitAddSub_ri()
1401 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rs() argument
1411 if (ShiftImm >= RetVT.getSizeInBits()) in emitAddSub_rs()
1436 .addImm(getShifterImm(ShiftType, ShiftImm)); in emitAddSub_rs()
1444 uint64_t ShiftImm, bool SetFlags, in emitAddSub_rx() argument
1453 if (ShiftImm >= 4) in emitAddSub_rx()
1481 .addImm(getArithExtendImm(ExtType, ShiftImm)); in emitAddSub_rx()
1601 uint64_t ShiftImm, bool WantResult) { in emitSubs_rs() argument
1603 RHSIsKill, ShiftType, ShiftImm, /*SetFlags=*/true, in emitSubs_rs()
1740 uint64_t ShiftImm) { in emitLogicalOp_rs() argument
1750 if (ShiftImm >= RetVT.getSizeInBits()) in emitLogicalOp_rs()
1772 AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftImm)); in emitLogicalOp_rs()