Lines Matching refs:inst
91 static ut32 arm_disasm_branch(struct winedbg_arm_insn *arminsn, ut32 inst) { in arm_disasm_branch() argument
92 short link = (inst >> 24) & 0x01; in arm_disasm_branch()
93 int offset = (inst << 2) & 0x03ffffff; in arm_disasm_branch()
99 …appendf (arminsn->str_asm, "b%s%s 0x%"PFMT64x, link ? "l" : "", get_cond (inst), arminsn->pc+offse… in arm_disasm_branch()
106 static ut32 arm_disasm_mul(struct winedbg_arm_insn *arminsn, ut32 inst) { in arm_disasm_mul() argument
107 short accu = (inst >> 21) & 0x01; in arm_disasm_mul()
108 short condcodes = (inst >> 20) & 0x01; in arm_disasm_mul()
111 …arminsn->str_asm = r_str_appendf (arminsn->str_asm, "mla%s%s %s, %s, %s, %s", get_cond (inst), con… in arm_disasm_mul()
112 tbl_regs[get_nibble (inst, 4)], tbl_regs[get_nibble (inst, 0)], in arm_disasm_mul()
113 tbl_regs[get_nibble (inst, 2)], tbl_regs[get_nibble (inst, 3)]); in arm_disasm_mul()
115 …arminsn->str_asm = r_str_appendf (arminsn->str_asm, "mul%s%s %s, %s, %s", get_cond (inst), condcod… in arm_disasm_mul()
116 tbl_regs[get_nibble (inst, 4)], tbl_regs[get_nibble (inst, 0)], in arm_disasm_mul()
117 tbl_regs[get_nibble (inst, 2)]); in arm_disasm_mul()
122 static ut32 arm_disasm_longmul(struct winedbg_arm_insn *arminsn, ut32 inst) { in arm_disasm_longmul() argument
123 short sign = (inst >> 22) & 0x01; in arm_disasm_longmul()
124 short accu = (inst >> 21) & 0x01; in arm_disasm_longmul()
125 short condcodes = (inst >> 20) & 0x01; in arm_disasm_longmul()
128 get_cond (inst), condcodes ? "s" : "", in arm_disasm_longmul()
129 tbl_regs[get_nibble (inst, 3)], tbl_regs[get_nibble (inst, 4)], in arm_disasm_longmul()
130 tbl_regs[get_nibble (inst, 0)], tbl_regs[get_nibble (inst, 2)]); in arm_disasm_longmul()
134 static ut32 arm_disasm_swp(struct winedbg_arm_insn *arminsn, ut32 inst) { in arm_disasm_swp() argument
135 short byte = (inst >> 22) & 0x01; in arm_disasm_swp()
137 …arminsn->str_asm = r_str_appendf (arminsn->str_asm, "swp%s%s %s, %s, [%s]", get_cond (inst), byte … in arm_disasm_swp()
138 tbl_regs[get_nibble (inst, 3)], tbl_regs[get_nibble (inst, 0)], in arm_disasm_swp()
139 tbl_regs[get_nibble (inst, 4)]); in arm_disasm_swp()
143 static ut32 arm_disasm_branchxchg(struct winedbg_arm_insn *arminsn, ut32 inst) { in arm_disasm_branchxchg() argument
144 …asm = r_str_appendf (arminsn->str_asm, "bx%s %s", get_cond (inst), tbl_regs[get_nibble (inst, 0)]); in arm_disasm_branchxchg()
148 static ut32 arm_disasm_mrstrans(struct winedbg_arm_insn *arminsn, ut32 inst) { in arm_disasm_mrstrans() argument
149 short src = (inst >> 22) & 0x01; in arm_disasm_mrstrans()
151 …= r_str_appendf (arminsn->str_asm, "mrs%s %s, %s", get_cond (inst), tbl_regs[get_nibble (inst, 3)], in arm_disasm_mrstrans()
156 static ut32 arm_disasm_msrtrans(struct winedbg_arm_insn *arminsn, ut32 inst) { in arm_disasm_msrtrans() argument
157 short immediate = (inst >> 25) & 0x01; in arm_disasm_msrtrans()
158 short dst = (inst >> 22) & 0x01; in arm_disasm_msrtrans()
161 …arminsn->str_asm = r_str_appendf (arminsn->str_asm, "msr%s %s, %s", get_cond (inst), dst ? "spsr" … in arm_disasm_msrtrans()
162 tbl_regs[get_nibble (inst, 0)]); in arm_disasm_msrtrans()
165 …arminsn->str_asm = r_str_appendf (arminsn->str_asm, "msr%s %s, #%u", get_cond (inst), dst ? "spsr"… in arm_disasm_msrtrans()
166 ROR32 (inst & 0xff, 2 * get_nibble (inst, 2))); in arm_disasm_msrtrans()
170 static ut32 arm_disasm_wordmov(struct winedbg_arm_insn *arminsn, ut32 inst) { in arm_disasm_wordmov() argument
171 short top = (inst >> 22) & 0x01; in arm_disasm_wordmov()
173 …sn->str_asm = r_str_appendf (arminsn->str_asm, "mov%s%s %s, #%u", top ? "t" : "w", get_cond (inst), in arm_disasm_wordmov()
174 tbl_regs[get_nibble (inst, 3)], in arm_disasm_wordmov()
175 (get_nibble (inst, 4) << 12) | (inst & 0x0fff)); in arm_disasm_wordmov()
179 static ut32 arm_disasm_nop(struct winedbg_arm_insn *arminsn, ut32 inst) { in arm_disasm_nop() argument
180 arminsn->str_asm = r_str_appendf (arminsn->str_asm, "nop%s", get_cond (inst)); in arm_disasm_nop()
184 static ut32 arm_disasm_dataprocessing(struct winedbg_arm_insn *arminsn, ut32 inst) { in arm_disasm_dataprocessing() argument
185 short condcodes = (inst >> 20) & 0x01; in arm_disasm_dataprocessing()
186 short opcode = (inst >> 21) & 0x0f; in arm_disasm_dataprocessing()
187 short immediate = (inst >> 25) & 0x01; in arm_disasm_dataprocessing()
191 …r_appendf (arminsn->str_asm, "%s%s%s", tbl_dataops[opcode], condcodes ? "s" : "", get_cond (inst)); in arm_disasm_dataprocessing()
193 arminsn->str_asm = r_str_appendf (arminsn->str_asm, " %s, ", tbl_regs[get_nibble (inst, 3)]); in arm_disasm_dataprocessing()
199 …n->str_asm = r_str_appendf (arminsn->str_asm, "#%u", ROR32 (inst & 0xff, 2 * get_nibble (inst, 2))… in arm_disasm_dataprocessing()
201 arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s", tbl_regs[get_nibble (inst, 0)]); in arm_disasm_dataprocessing()
205 arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s, #%u", tbl_regs[get_nibble (inst, 4)], in arm_disasm_dataprocessing()
206 ROR32 (inst & 0xff, 2 * get_nibble (inst, 2))); in arm_disasm_dataprocessing()
207 } else if (((inst >> 4) & 0xff) == 0x00) { /* no shift */ in arm_disasm_dataprocessing()
208 arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s, %s", tbl_regs[get_nibble (inst, 4)], in arm_disasm_dataprocessing()
209 tbl_regs[get_nibble (inst, 0)]); in arm_disasm_dataprocessing()
210 } else if (((inst >> 4) & 0x09) == 0x01) { /* register shift */ in arm_disasm_dataprocessing()
211 …arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s, %s, %s %s", tbl_regs[get_nibble (inst, 4)… in arm_disasm_dataprocessing()
212 tbl_regs[get_nibble (inst, 0)], in arm_disasm_dataprocessing()
213 tbl_shifts[(inst >> 5) & 0x03], tbl_regs[(inst >> 8) & 0x0f]); in arm_disasm_dataprocessing()
214 } else if (((inst >> 4) & 0x01) == 0x00) { /* immediate shift */ in arm_disasm_dataprocessing()
215 …arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s, %s, %s #%d", tbl_regs[get_nibble (inst, 4… in arm_disasm_dataprocessing()
216 tbl_regs[get_nibble (inst, 0)], tbl_shifts[(inst >> 5) & 0x03], in arm_disasm_dataprocessing()
217 (inst >> 7) & 0x1f); in arm_disasm_dataprocessing()
219 return inst; in arm_disasm_dataprocessing()
225 static ut32 arm_disasm_singletrans(struct winedbg_arm_insn *arminsn, ut32 inst) { in arm_disasm_singletrans() argument
226 short load = (inst >> 20) & 0x01; in arm_disasm_singletrans()
227 short writeback = (inst >> 21) & 0x01; in arm_disasm_singletrans()
228 short byte = (inst >> 22) & 0x01; in arm_disasm_singletrans()
229 short direction = (inst >> 23) & 0x01; in arm_disasm_singletrans()
230 short indexing = (inst >> 24) & 0x01; in arm_disasm_singletrans()
231 short immediate = !((inst >> 25) & 0x01); in arm_disasm_singletrans()
232 short offset = inst & 0x0fff; in arm_disasm_singletrans()
235 get_cond (inst)); in arm_disasm_singletrans()
236 arminsn->str_asm = r_str_appendf (arminsn->str_asm, " %s, ", tbl_regs[get_nibble (inst, 3)]); in arm_disasm_singletrans()
239 …arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s, #%s%d]", tbl_regs[get_nibble (inst, 4)],… in arm_disasm_singletrans()
240 } else if (((inst >> 4) & 0xff) == 0x00) { /* no shift */ in arm_disasm_singletrans()
241 arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s, %s]", tbl_regs[get_nibble (inst, 4)], in arm_disasm_singletrans()
242 tbl_regs[get_nibble (inst, 0)]); in arm_disasm_singletrans()
243 } else if (((inst >> 4) & 0x01) == 0x00) {/* immediate shift (there's no register shift) */ in arm_disasm_singletrans()
244 …nsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s, %s, %s #%d]", tbl_regs[get_nibble (inst, 4)], in arm_disasm_singletrans()
245 tbl_regs[get_nibble (inst, 0)], tbl_shifts[(inst >> 5) & 0x03], in arm_disasm_singletrans()
246 (inst >> 7) & 0x1f); in arm_disasm_singletrans()
248 return inst; in arm_disasm_singletrans()
252 …arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s], #%s%d", tbl_regs[get_nibble (inst, 4)],… in arm_disasm_singletrans()
253 } else if (((inst >> 4) & 0xff) == 0x00) { /* no shift */ in arm_disasm_singletrans()
254 arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s], %s", tbl_regs[get_nibble (inst, 4)], in arm_disasm_singletrans()
255 tbl_regs[get_nibble (inst, 0)]); in arm_disasm_singletrans()
256 } else if (((inst >> 4) & 0x01) == 0x00) { /* immediate shift (there's no register shift) */ in arm_disasm_singletrans()
257 …nsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s], %s, %s #%d", tbl_regs[get_nibble (inst, 4)], in arm_disasm_singletrans()
258 tbl_regs[get_nibble (inst, 0)], tbl_shifts[(inst >> 5) & 0x03], in arm_disasm_singletrans()
259 (inst >> 7) & 0x1f); in arm_disasm_singletrans()
261 return inst; in arm_disasm_singletrans()
267 static ut32 arm_disasm_halfwordtrans(struct winedbg_arm_insn *arminsn, ut32 inst) { in arm_disasm_halfwordtrans() argument
268 short halfword = (inst >> 5) & 0x01; in arm_disasm_halfwordtrans()
269 short sign = (inst >> 6) & 0x01; in arm_disasm_halfwordtrans()
270 short load = (inst >> 20) & 0x01; in arm_disasm_halfwordtrans()
271 short writeback = (inst >> 21) & 0x01; in arm_disasm_halfwordtrans()
272 short immediate = (inst >> 22) & 0x01; in arm_disasm_halfwordtrans()
273 short direction = (inst >> 23) & 0x01; in arm_disasm_halfwordtrans()
274 short indexing = (inst >> 24) & 0x01; in arm_disasm_halfwordtrans()
275 short offset = ((inst >> 4) & 0xf0) + (inst & 0x0f); in arm_disasm_halfwordtrans()
278 halfword ? "h" : (sign ? "b" : ""), writeback ? "t" : "", get_cond (inst)); in arm_disasm_halfwordtrans()
279 arminsn->str_asm = r_str_appendf (arminsn->str_asm, " %s, ", tbl_regs[get_nibble (inst, 3)]); in arm_disasm_halfwordtrans()
282 …arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s, #%s%d]", tbl_regs[get_nibble (inst, 4)],… in arm_disasm_halfwordtrans()
284 arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s, %s]", tbl_regs[get_nibble (inst, 4)], in arm_disasm_halfwordtrans()
285 tbl_regs[get_nibble (inst, 0)]); in arm_disasm_halfwordtrans()
289 …arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s], #%s%d", tbl_regs[get_nibble (inst, 4)],… in arm_disasm_halfwordtrans()
291 arminsn->str_asm = r_str_appendf (arminsn->str_asm, "[%s], %s", tbl_regs[get_nibble (inst, 4)], in arm_disasm_halfwordtrans()
292 tbl_regs[get_nibble (inst, 0)]); in arm_disasm_halfwordtrans()
298 static ut32 arm_disasm_blocktrans(struct winedbg_arm_insn *arminsn, ut32 inst) { in arm_disasm_blocktrans() argument
299 short load = (inst >> 20) & 0x01; in arm_disasm_blocktrans()
300 short writeback = (inst >> 21) & 0x01; in arm_disasm_blocktrans()
301 short psr = (inst >> 22) & 0x01; in arm_disasm_blocktrans()
302 short addrmode = (inst >> 23) & 0x03; in arm_disasm_blocktrans()
307 get_cond (inst), tbl_regs[get_nibble (inst, 4)], writeback ? "!" : ""); in arm_disasm_blocktrans()
308 for (i = 0; i < 16; i++, inst >>= 1) { in arm_disasm_blocktrans()
309 if (inst & 1) { in arm_disasm_blocktrans()
318 static ut32 arm_disasm_swi(struct winedbg_arm_insn *arminsn, ut32 inst) { in arm_disasm_swi() argument
319 ut32 comment = inst & 0x00ffffff; in arm_disasm_swi()
320 arminsn->str_asm = r_str_appendf (arminsn->str_asm, "swi%s #%d", get_cond (inst), comment); in arm_disasm_swi()
324 static ut32 arm_disasm_coproctrans(struct winedbg_arm_insn *arminsn, ut32 inst) { in arm_disasm_coproctrans() argument
325 ut16 CRm = inst & 0x0f; in arm_disasm_coproctrans()
326 ut16 CP_Opc2 = (inst >> 5) & 0x07; in arm_disasm_coproctrans()
327 ut16 CPnum = (inst >> 8) & 0x0f; in arm_disasm_coproctrans()
328 ut16 CRn = (inst >> 16) & 0x0f; in arm_disasm_coproctrans()
329 ut16 load = (inst >> 20) & 0x01; in arm_disasm_coproctrans()
330 ut16 CP_Opc1 = (inst >> 21) & 0x07; in arm_disasm_coproctrans()
333 get_cond (inst), CPnum, CP_Opc1, tbl_regs[get_nibble (inst, 3)], CRn, CRm, CP_Opc2); in arm_disasm_coproctrans()
337 static ut32 arm_disasm_coprocdataop(struct winedbg_arm_insn *arminsn, ut32 inst) { in arm_disasm_coprocdataop() argument
338 ut16 CRm = inst & 0x0f; in arm_disasm_coprocdataop()
339 ut16 CP_Opc2 = (inst >> 5) & 0x07; in arm_disasm_coprocdataop()
340 ut16 CPnum = (inst >> 8) & 0x0f; in arm_disasm_coprocdataop()
341 ut16 CRd = (inst >> 12) & 0x0f; in arm_disasm_coprocdataop()
342 ut16 CRn = (inst >> 16) & 0x0f; in arm_disasm_coprocdataop()
343 ut16 CP_Opc1 = (inst >> 20) & 0x0f; in arm_disasm_coprocdataop()
345 …str_asm = r_str_appendf (arminsn->str_asm, "cdp%s %u, %u, cr%u, cr%u, cr%u, {%u}", get_cond (inst), in arm_disasm_coprocdataop()
350 static ut32 arm_disasm_coprocdatatrans(struct winedbg_arm_insn *arminsn, ut32 inst) { in arm_disasm_coprocdatatrans() argument
351 ut16 CPnum = (inst >> 8) & 0x0f; in arm_disasm_coprocdatatrans()
352 ut16 CRd = (inst >> 12) & 0x0f; in arm_disasm_coprocdatatrans()
353 ut16 load = (inst >> 20) & 0x01; in arm_disasm_coprocdatatrans()
354 ut16 writeback = (inst >> 21) & 0x01; in arm_disasm_coprocdatatrans()
355 ut16 translen = (inst >> 22) & 0x01; in arm_disasm_coprocdatatrans()
356 ut16 direction = (inst >> 23) & 0x01; in arm_disasm_coprocdatatrans()
357 ut16 indexing = (inst >> 24) & 0x01; in arm_disasm_coprocdatatrans()
358 short offset = (inst & 0xff) << 2; in arm_disasm_coprocdatatrans()
360 …r_appendf (arminsn->str_asm, "%s%s%s", load ? "ldc" : "stc", translen ? "l" : "", get_cond (inst)); in arm_disasm_coprocdatatrans()
362 …_appendf (arminsn->str_asm, " %u, cr%u, [%s, #%s%d]%s", CPnum, CRd, tbl_regs[get_nibble (inst, 4)], in arm_disasm_coprocdatatrans()
365 …tr_appendf (arminsn->str_asm, " %u, cr%u, [%s], #%s%d", CPnum, CRd, tbl_regs[get_nibble (inst, 4)], in arm_disasm_coprocdatatrans()
371 static ut16 thumb_disasm_hireg(struct winedbg_arm_insn *arminsn, ut16 inst) { in thumb_disasm_hireg() argument
372 short dst = inst & 0x07; in thumb_disasm_hireg()
373 short src = (inst >> 3) & 0x07; in thumb_disasm_hireg()
374 short h2 = (inst >> 6) & 0x01; in thumb_disasm_hireg()
375 short h1 = (inst >> 7) & 0x01; in thumb_disasm_hireg()
376 short op = (inst >> 8) & 0x03; in thumb_disasm_hireg()
399 static ut16 thumb_disasm_aluop(struct winedbg_arm_insn *arminsn, ut16 inst) { in thumb_disasm_aluop() argument
400 short dst = inst & 0x07; in thumb_disasm_aluop()
401 short src = (inst >> 3) & 0x07; in thumb_disasm_aluop()
402 short op = (inst >> 6) & 0x0f; in thumb_disasm_aluop()
408 static ut16 thumb_disasm_pushpop(struct winedbg_arm_insn *arminsn, ut16 inst) { in thumb_disasm_pushpop() argument
409 short lrpc = (inst >> 8) & 0x01; in thumb_disasm_pushpop()
410 short load = (inst >> 11) & 0x01; in thumb_disasm_pushpop()
416 for (i = 0; i < 8; i++, inst >>= 1) { in thumb_disasm_pushpop()
417 if (inst & 1) { in thumb_disasm_pushpop()
430 static ut16 thumb_disasm_blocktrans(struct winedbg_arm_insn *arminsn, ut16 inst) { in thumb_disasm_blocktrans() argument
431 short load = (inst >> 11) & 0x01; in thumb_disasm_blocktrans()
435 …tr_appendf (arminsn->str_asm, "%s %s!, {", load ? "ldmia" : "stmia", tbl_regs[(inst >> 8) & 0x07]); in thumb_disasm_blocktrans()
437 for (i = 0; i < 8; i++, inst >>= 1) { in thumb_disasm_blocktrans()
438 if (inst & 1) { in thumb_disasm_blocktrans()
448 static ut16 thumb_disasm_condbranch(struct winedbg_arm_insn *arminsn, ut16 inst) { in thumb_disasm_condbranch() argument
449 ut16 offset = inst & 0x00ff; in thumb_disasm_condbranch()
450 …arminsn->str_asm = r_str_appendf (arminsn->str_asm, "b%s 0x%"PFMT64x, tbl_cond[(inst >> 8) & 0x0f]… in thumb_disasm_condbranch()
457 static ut16 thumb_disasm_uncondbranch(struct winedbg_arm_insn *arminsn, ut16 inst) { in thumb_disasm_uncondbranch() argument
458 short offset = (inst & 0x07ff) << 1; in thumb_disasm_uncondbranch()
470 static ut16 thumb_disasm_loadadr(struct winedbg_arm_insn *arminsn, ut16 inst) { in thumb_disasm_loadadr() argument
471 ut16 src = (inst >> 11) & 0x01; in thumb_disasm_loadadr()
472 ut16 offset = (inst & 0xff) << 2; in thumb_disasm_loadadr()
474 …arminsn->str_asm = r_str_appendf (arminsn->str_asm, "add %s, %s, #%d", tbl_regs[(inst >> 8) & 0x07… in thumb_disasm_loadadr()
479 static ut16 thumb_disasm_swi(struct winedbg_arm_insn *arminsn, ut16 inst) { in thumb_disasm_swi() argument
480 ut16 comment = inst & 0x00ff; in thumb_disasm_swi()
485 static ut16 thumb_disasm_nop(struct winedbg_arm_insn *arminsn, ut16 inst) { in thumb_disasm_nop() argument
490 static ut16 thumb_disasm_ldrpcrel(struct winedbg_arm_insn *arminsn, ut16 inst) { in thumb_disasm_ldrpcrel() argument
491 ut16 offset = (inst & 0xff) << 2; in thumb_disasm_ldrpcrel()
492 …arminsn->str_asm = r_str_appendf (arminsn->str_asm, "ldr %s, [pc, #%u]", tbl_regs[(inst >> 8) & 0x… in thumb_disasm_ldrpcrel()
496 static ut16 thumb_disasm_ldrsprel(struct winedbg_arm_insn *arminsn, ut16 inst) { in thumb_disasm_ldrsprel() argument
497 ut16 offset = (inst & 0xff) << 2; in thumb_disasm_ldrsprel()
498 …arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s %s, [sp, #%u]", (inst & 0x0800)?"ldr":"str… in thumb_disasm_ldrsprel()
499 tbl_regs[(inst >> 8) & 0x07], offset); in thumb_disasm_ldrsprel()
503 static ut16 thumb_disasm_addsprel(struct winedbg_arm_insn *arminsn, ut16 inst) { in thumb_disasm_addsprel() argument
504 ut16 offset = (inst & 0x7f) << 2; in thumb_disasm_addsprel()
505 if ((inst >> 7) & 0x01) { in thumb_disasm_addsprel()
514 static ut16 thumb_disasm_ldrimm(struct winedbg_arm_insn *arminsn, ut16 inst) { in thumb_disasm_ldrimm() argument
515 ut16 offset = (inst & 0x07c0) >> 6; in thumb_disasm_ldrimm()
517 (inst & 0x0800)?"ldr":"str", (inst & 0x1000)?"b":"", in thumb_disasm_ldrimm()
518 tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], in thumb_disasm_ldrimm()
519 (inst & 0x1000)?offset:(offset << 2)); in thumb_disasm_ldrimm()
523 static ut16 thumb_disasm_ldrhimm(struct winedbg_arm_insn *arminsn, ut16 inst) { in thumb_disasm_ldrhimm() argument
524 ut16 offset = (inst & 0x07c0) >> 5; in thumb_disasm_ldrhimm()
525 …arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s %s, [%s, #%u]", (inst & 0x0800)?"ldrh":"st… in thumb_disasm_ldrhimm()
526 tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], offset); in thumb_disasm_ldrhimm()
530 static ut16 thumb_disasm_ldrreg(struct winedbg_arm_insn *arminsn, ut16 inst) { in thumb_disasm_ldrreg() argument
532 (inst & 0x0800)?"ldr":"str", (inst & 0x0400)?"b":"", in thumb_disasm_ldrreg()
533 tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], in thumb_disasm_ldrreg()
534 tbl_regs[(inst >> 6) & 0x07]); in thumb_disasm_ldrreg()
538 static ut16 thumb_disasm_ldrsreg(struct winedbg_arm_insn *arminsn, ut16 inst) { in thumb_disasm_ldrsreg() argument
540 tbl_sregops_t[(inst >> 10) & 0x03], tbl_regs[inst & 0x07], in thumb_disasm_ldrsreg()
541 tbl_regs[(inst >> 3) & 0x07], tbl_regs[(inst >> 6) & 0x07]); in thumb_disasm_ldrsreg()
545 static ut16 thumb_disasm_immop(struct winedbg_arm_insn *arminsn, ut16 inst) { in thumb_disasm_immop() argument
546 ut16 op = (inst >> 11) & 0x03; in thumb_disasm_immop()
547 …arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s %s, #%u", tbl_immops_t[op], tbl_regs[(inst… in thumb_disasm_immop()
548 inst & 0xff); in thumb_disasm_immop()
552 static ut16 thumb_disasm_addsub(struct winedbg_arm_insn *arminsn, ut16 inst) { in thumb_disasm_addsub() argument
553 ut16 op = (inst >> 9) & 0x01; in thumb_disasm_addsub()
554 ut16 immediate = (inst >> 10) & 0x01; in thumb_disasm_addsub()
557 tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07]); in thumb_disasm_addsub()
559 arminsn->str_asm = r_str_appendf (arminsn->str_asm, "#%d", (inst >> 6) & 0x07); in thumb_disasm_addsub()
562 arminsn->str_asm = r_str_appendf (arminsn->str_asm, "%s", tbl_regs[(inst >> 6) & 0x07]); in thumb_disasm_addsub()
567 static ut16 thumb_disasm_movshift(struct winedbg_arm_insn *arminsn, ut16 inst) { in thumb_disasm_movshift() argument
568 ut16 op = (inst >> 11) & 0x03; in thumb_disasm_movshift()
570 tbl_regs[inst & 0x07], tbl_regs[(inst >> 3) & 0x07], (inst >> 6) & 0x1f); in thumb_disasm_movshift()
574 static ut32 thumb2_disasm_branchlinked(struct winedbg_arm_insn *arminsn, ut32 inst) { in thumb2_disasm_branchlinked() argument
575 ut32 offset = (((inst & 0x07ff0000) >> 4) | ((inst & 0x000007ff) << 1)) + 4; in thumb2_disasm_branchlinked()
582 static ut32 thumb2_disasm_misc(struct winedbg_arm_insn *arminsn, ut32 inst) { in thumb2_disasm_misc() argument
583 ut16 op1 = (inst >> 20) & 0x03; in thumb2_disasm_misc()
584 ut16 op2 = (inst >> 4) & 0x03; in thumb2_disasm_misc()
586 if (get_nibble (inst, 4) != get_nibble (inst, 0)) { in thumb2_disasm_misc()
587 return inst; in thumb2_disasm_misc()
591 arminsn->str_asm = r_str_appendf (arminsn->str_asm, "clz %s, %s ", tbl_regs[get_nibble (inst, 2)], in thumb2_disasm_misc()
592 tbl_regs[get_nibble (inst, 0)]); in thumb2_disasm_misc()
611 …ppendf (arminsn->str_asm, "%s, %s ", tbl_regs[get_nibble (inst, 2)], tbl_regs[get_nibble (inst, 0)… in thumb2_disasm_misc()
615 return inst; in thumb2_disasm_misc()
618 static ut32 thumb2_disasm_mul(struct winedbg_arm_insn *arminsn, ut32 inst) { in thumb2_disasm_mul() argument
619 ut16 op1 = (inst >> 20) & 0x07; in thumb2_disasm_mul()
620 ut16 op2 = (inst >> 4) & 0x03; in thumb2_disasm_mul()
623 return inst; in thumb2_disasm_mul()
626 if (op2 == 0 && get_nibble (inst, 3) != 0xf) { in thumb2_disasm_mul()
627 …->str_asm = r_str_appendf (arminsn->str_asm, "mla %s, %s, %s, %s ", tbl_regs[get_nibble (inst, 2)], in thumb2_disasm_mul()
628 tbl_regs[get_nibble (inst, 4)], in thumb2_disasm_mul()
629 tbl_regs[get_nibble (inst, 0)], in thumb2_disasm_mul()
630 tbl_regs[get_nibble (inst, 3)]); in thumb2_disasm_mul()
634 if (op2 == 0 && get_nibble (inst, 3) == 0xf) { in thumb2_disasm_mul()
635 …arminsn->str_asm = r_str_appendf (arminsn->str_asm, "mul %s, %s, %s ", tbl_regs[get_nibble (inst, … in thumb2_disasm_mul()
636 tbl_regs[get_nibble (inst, 4)], in thumb2_disasm_mul()
637 tbl_regs[get_nibble (inst, 0)]); in thumb2_disasm_mul()
642 …->str_asm = r_str_appendf (arminsn->str_asm, "mls %s, %s, %s, %s ", tbl_regs[get_nibble (inst, 2)], in thumb2_disasm_mul()
643 tbl_regs[get_nibble (inst, 4)], in thumb2_disasm_mul()
644 tbl_regs[get_nibble (inst, 0)], in thumb2_disasm_mul()
645 tbl_regs[get_nibble (inst, 3)]); in thumb2_disasm_mul()
649 return inst; in thumb2_disasm_mul()
652 static ut32 thumb2_disasm_longmuldiv(struct winedbg_arm_insn *arminsn, ut32 inst) { in thumb2_disasm_longmuldiv() argument
653 ut16 op1 = (inst >> 20) & 0x07; in thumb2_disasm_longmuldiv()
654 ut16 op2 = (inst >> 4) & 0x0f; in thumb2_disasm_longmuldiv()
671 return inst; in thumb2_disasm_longmuldiv()
674 tbl_regs[get_nibble (inst, 3)], tbl_regs[get_nibble (inst, 2)], in thumb2_disasm_longmuldiv()
675 tbl_regs[get_nibble (inst, 4)], tbl_regs[get_nibble (inst, 0)]); in thumb2_disasm_longmuldiv()
688 return inst; in thumb2_disasm_longmuldiv()
690 …df (arminsn->str_asm, "%s, %s, %s ", tbl_regs[get_nibble (inst, 2)], tbl_regs[get_nibble (inst, 4)… in thumb2_disasm_longmuldiv()
691 tbl_regs[get_nibble (inst, 0)]); in thumb2_disasm_longmuldiv()
695 return inst; in thumb2_disasm_longmuldiv()
698 static ut32 thumb2_disasm_coprocmov1(struct winedbg_arm_insn *arminsn, ut32 inst) { in thumb2_disasm_coprocmov1() argument
699 ut16 opc1 = (inst >> 21) & 0x07; in thumb2_disasm_coprocmov1()
700 ut16 opc2 = (inst >> 5) & 0x07; in thumb2_disasm_coprocmov1()
704 "%s%s\tp%u, #%u, %s, cr%u, cr%u, #%u", (inst & 0x00100000)?"mrc":"mcr", in thumb2_disasm_coprocmov1()
705 (inst & 0x10000000)?"2":"", get_nibble (inst, 2), opc1, in thumb2_disasm_coprocmov1()
706 tbl_regs[get_nibble (inst, 3)], get_nibble (inst, 4), get_nibble (inst, 0), opc2); in thumb2_disasm_coprocmov1()
710 "%s%s\tp%u, #%u, %s, cr%u, cr%u", (inst & 0x00100000)?"mrc":"mcr", in thumb2_disasm_coprocmov1()
711 (inst & 0x10000000)?"2":"", get_nibble (inst, 2), opc1, in thumb2_disasm_coprocmov1()
712 tbl_regs[get_nibble (inst, 3)], get_nibble (inst, 4), get_nibble (inst, 0)); in thumb2_disasm_coprocmov1()
825 ut32 inst; in arm_disasm_one_insn() local
833 inst = db_get_inst(arminsn->buf, size); in arm_disasm_one_insn()
835 if ((inst & a_ptr->mask) == a_ptr->pattern) { in arm_disasm_one_insn()
843 arminsn->str_asm = r_str_appendf (arminsn->str_asm, "Unknown ARM Instruction: %08x", inst); in arm_disasm_one_insn()
846 a_ptr->func(arminsn, inst); in arm_disasm_one_insn()
849 *((ut8*)(&inst)), *((ut8*)(&inst)+1), *((ut8*)(&inst)+2), *((ut8*)(&inst)+3)); in arm_disasm_one_insn()
858 inst = db_get_inst(arminsn->buf+1, THUMB_INSN_SIZE); in arm_disasm_one_insn()
859 inst |= (tinst << 16); in arm_disasm_one_insn()
862 if ((inst & t2_ptr->mask) == t2_ptr->pattern) { in arm_disasm_one_insn()
870 arminsn->str_asm = r_str_appendf (arminsn->str_asm, "Unknown Thumb2 Instruction: %08x", inst); in arm_disasm_one_insn()
873 t2_ptr->func(arminsn, inst); in arm_disasm_one_insn()
876 *((ut8*)(&inst)), *((ut8*)(&inst)+1), *((ut8*)(&inst)+2), *((ut8*)(&inst)+3)); in arm_disasm_one_insn()