Lines Matching refs:sl
440 static uint32_t get_stm32l0_flash_base(stlink_t *sl) { in get_stm32l0_flash_base() argument
441 switch (sl->chip_id) { in get_stm32l0_flash_base()
460 static uint32_t __attribute__((unused)) read_flash_rdp(stlink_t *sl) { in read_flash_rdp() argument
462 stlink_read_debug32(sl, FLASH_WRPR, &rdp); in read_flash_rdp()
466 static inline uint32_t read_flash_cr(stlink_t *sl, unsigned bank) { in read_flash_cr() argument
469 if (sl->flash_type == STLINK_FLASH_TYPE_F4) { in read_flash_cr()
471 } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { in read_flash_cr()
473 } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { in read_flash_cr()
475 } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || in read_flash_cr()
476 sl->flash_type == STLINK_FLASH_TYPE_G4) { in read_flash_cr()
478 } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { in read_flash_cr()
480 } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { in read_flash_cr()
486 stlink_read_debug32(sl, reg, &res); in read_flash_cr()
494 static inline unsigned int is_flash_locked(stlink_t *sl) { in is_flash_locked() argument
500 if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || in is_flash_locked()
501 (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { in is_flash_locked()
504 } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { in is_flash_locked()
507 } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { in is_flash_locked()
510 } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { in is_flash_locked()
511 cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; in is_flash_locked()
513 } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { in is_flash_locked()
516 } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || in is_flash_locked()
517 sl->flash_type == STLINK_FLASH_TYPE_G4) { in is_flash_locked()
520 } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { in is_flash_locked()
523 } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { in is_flash_locked()
531 stlink_read_debug32(sl, cr_reg, &n); in is_flash_locked()
535 static void unlock_flash(stlink_t *sl) { in unlock_flash() argument
544 if (sl->flash_type == STLINK_FLASH_TYPE_F0) { in unlock_flash()
546 } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { in unlock_flash()
549 } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { in unlock_flash()
551 } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { in unlock_flash()
553 } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { in unlock_flash()
554 key_reg = get_stm32l0_flash_base(sl) + FLASH_PEKEYR_OFF; in unlock_flash()
557 } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { in unlock_flash()
559 } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || in unlock_flash()
560 sl->flash_type == STLINK_FLASH_TYPE_G4) { in unlock_flash()
562 } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { in unlock_flash()
564 } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { in unlock_flash()
566 if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { in unlock_flash()
574 stlink_write_debug32(sl, key_reg, flash_key1); in unlock_flash()
575 stlink_write_debug32(sl, key_reg, flash_key2); in unlock_flash()
578 stlink_write_debug32(sl, key2_reg, flash_key1); in unlock_flash()
579 stlink_write_debug32(sl, key2_reg, flash_key2); in unlock_flash()
584 static int unlock_flash_if(stlink_t *sl) { in unlock_flash_if() argument
585 if (is_flash_locked(sl)) { in unlock_flash_if()
586 unlock_flash(sl); in unlock_flash_if()
588 if (is_flash_locked(sl)) { in unlock_flash_if()
598 static void lock_flash(stlink_t *sl) { in lock_flash() argument
602 if (sl->flash_type == STLINK_FLASH_TYPE_F0) { in lock_flash()
605 } else if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { in lock_flash()
609 } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { in lock_flash()
612 } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { in lock_flash()
615 } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { in lock_flash()
616 cr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; in lock_flash()
618 } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { in lock_flash()
621 } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || in lock_flash()
622 sl->flash_type == STLINK_FLASH_TYPE_G4) { in lock_flash()
625 } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { in lock_flash()
628 } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { in lock_flash()
630 if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { in lock_flash()
640 stlink_read_debug32(sl, cr_reg, &n); in lock_flash()
643 stlink_write_debug32(sl, cr_reg, n); in lock_flash()
646 n = read_flash_cr(sl, BANK_2) | (1u << cr_lock_shift); in lock_flash()
647 stlink_write_debug32(sl, cr2_reg, n); in lock_flash()
651 static bool is_flash_option_locked(stlink_t *sl) { in is_flash_option_locked() argument
656 switch (sl->flash_type) { in is_flash_option_locked()
672 optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; in is_flash_option_locked()
697 stlink_read_debug32(sl, optcr_reg, &n); in is_flash_option_locked()
706 static int lock_flash_option(stlink_t *sl) { in lock_flash_option() argument
710 switch (sl->flash_type) { in lock_flash_option()
726 optcr_reg = get_stm32l0_flash_base(sl) + FLASH_PECR_OFF; in lock_flash_option()
745 if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) in lock_flash_option()
753 stlink_read_debug32(sl, optcr_reg, &n); in lock_flash_option()
761 stlink_write_debug32(sl, optcr_reg, n); in lock_flash_option()
764 stlink_read_debug32(sl, optcr2_reg, &n); in lock_flash_option()
772 stlink_write_debug32(sl, optcr2_reg, n); in lock_flash_option()
778 static int unlock_flash_option(stlink_t *sl) { in unlock_flash_option() argument
783 switch (sl->flash_type) { in unlock_flash_option()
797 optkey_reg = get_stm32l0_flash_base(sl) + FLASH_OPTKEYR_OFF; in unlock_flash_option()
813 if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) in unlock_flash_option()
821 stlink_write_debug32(sl, optkey_reg, optkey1); in unlock_flash_option()
822 stlink_write_debug32(sl, optkey_reg, optkey2); in unlock_flash_option()
825 stlink_write_debug32(sl, optkey2_reg, optkey1); in unlock_flash_option()
826 stlink_write_debug32(sl, optkey2_reg, optkey2); in unlock_flash_option()
832 static int unlock_flash_option_if(stlink_t *sl) { in unlock_flash_option_if() argument
833 if (is_flash_option_locked(sl)) { in unlock_flash_option_if()
834 if (unlock_flash_option(sl)) { in unlock_flash_option_if()
839 if (is_flash_option_locked(sl)) { in unlock_flash_option_if()
849 static void set_flash_cr_pg(stlink_t *sl, unsigned bank) { in set_flash_cr_pg() argument
852 x = read_flash_cr(sl, bank); in set_flash_cr_pg()
854 if (sl->flash_type == STLINK_FLASH_TYPE_F4) { in set_flash_cr_pg()
857 } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { in set_flash_cr_pg()
860 } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { in set_flash_cr_pg()
864 } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || in set_flash_cr_pg()
865 sl->flash_type == STLINK_FLASH_TYPE_G4) { in set_flash_cr_pg()
868 } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { in set_flash_cr_pg()
871 } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { in set_flash_cr_pg()
879 stlink_write_debug32(sl, cr_reg, x); in set_flash_cr_pg()
882 static void clear_flash_cr_pg(stlink_t *sl, unsigned bank) { in clear_flash_cr_pg() argument
886 if (sl->flash_type == STLINK_FLASH_TYPE_F4) { in clear_flash_cr_pg()
888 } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { in clear_flash_cr_pg()
890 } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { in clear_flash_cr_pg()
892 } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || in clear_flash_cr_pg()
893 sl->flash_type == STLINK_FLASH_TYPE_G4) { in clear_flash_cr_pg()
895 } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { in clear_flash_cr_pg()
897 } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { in clear_flash_cr_pg()
904 n = read_flash_cr(sl, bank) & ~(1 << bit); in clear_flash_cr_pg()
905 stlink_write_debug32(sl, cr_reg, n); in clear_flash_cr_pg()
908 static void set_flash_cr_per(stlink_t *sl, unsigned bank) { in set_flash_cr_per() argument
911 if (sl->flash_type == STLINK_FLASH_TYPE_G0 || in set_flash_cr_per()
912 sl->flash_type == STLINK_FLASH_TYPE_G4) { in set_flash_cr_per()
914 } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { in set_flash_cr_per()
920 stlink_read_debug32(sl, cr_reg, &val); in set_flash_cr_per()
922 stlink_write_debug32(sl, cr_reg, val); in set_flash_cr_per()
925 static void clear_flash_cr_per(stlink_t *sl, unsigned bank) { in clear_flash_cr_per() argument
928 if (sl->flash_type == STLINK_FLASH_TYPE_G0 || in clear_flash_cr_per()
929 sl->flash_type == STLINK_FLASH_TYPE_G4) { in clear_flash_cr_per()
931 } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { in clear_flash_cr_per()
937 const uint32_t n = read_flash_cr(sl, bank) & ~(1 << FLASH_CR_PER); in clear_flash_cr_per()
938 stlink_write_debug32(sl, cr_reg, n); in clear_flash_cr_per()
941 static void set_flash_cr_mer(stlink_t *sl, bool v, unsigned bank) { in set_flash_cr_mer() argument
944 if (sl->flash_type == STLINK_FLASH_TYPE_F4) { in set_flash_cr_mer()
948 } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { in set_flash_cr_mer()
952 } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { in set_flash_cr_mer()
956 } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || in set_flash_cr_mer()
957 sl->flash_type == STLINK_FLASH_TYPE_G4) { in set_flash_cr_mer()
961 if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { in set_flash_cr_mer()
966 } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { in set_flash_cr_mer()
970 } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { in set_flash_cr_mer()
980 stlink_read_debug32(sl, cr_reg, &val); in set_flash_cr_mer()
985 stlink_write_debug32(sl, cr_reg, val); in set_flash_cr_mer()
994 stlink_write_debug32(sl, cr_reg, val); in set_flash_cr_mer()
997 static void set_flash_cr_strt(stlink_t *sl, unsigned bank) { in set_flash_cr_strt() argument
1000 if (sl->flash_type == STLINK_FLASH_TYPE_F4) { in set_flash_cr_strt()
1003 } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { in set_flash_cr_strt()
1006 } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { in set_flash_cr_strt()
1009 } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || in set_flash_cr_strt()
1010 sl->flash_type == STLINK_FLASH_TYPE_G4) { in set_flash_cr_strt()
1013 } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { in set_flash_cr_strt()
1016 } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { in set_flash_cr_strt()
1018 cr_strt = 1 << FLASH_H7_CR_START(sl->chip_id); in set_flash_cr_strt()
1024 stlink_read_debug32(sl, cr_reg, &val); in set_flash_cr_strt()
1026 stlink_write_debug32(sl, cr_reg, val); in set_flash_cr_strt()
1029 static inline uint32_t read_flash_sr(stlink_t *sl, unsigned bank) { in read_flash_sr() argument
1032 if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || in read_flash_sr()
1033 (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { in read_flash_sr()
1035 } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { in read_flash_sr()
1036 sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; in read_flash_sr()
1037 } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { in read_flash_sr()
1039 } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { in read_flash_sr()
1041 } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { in read_flash_sr()
1043 } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || in read_flash_sr()
1044 sl->flash_type == STLINK_FLASH_TYPE_G4) { in read_flash_sr()
1046 } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { in read_flash_sr()
1048 } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { in read_flash_sr()
1055 stlink_read_debug32(sl, sr_reg, &res); in read_flash_sr()
1059 static inline int write_flash_sr(stlink_t *sl, unsigned bank, uint32_t val) { in write_flash_sr() argument
1062 if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || in write_flash_sr()
1063 (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { in write_flash_sr()
1065 } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { in write_flash_sr()
1066 sr_reg = get_stm32l0_flash_base(sl) + FLASH_SR_OFF; in write_flash_sr()
1067 } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { in write_flash_sr()
1069 } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { in write_flash_sr()
1071 } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { in write_flash_sr()
1073 } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || in write_flash_sr()
1074 sl->flash_type == STLINK_FLASH_TYPE_G4) { in write_flash_sr()
1076 } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { in write_flash_sr()
1078 } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { in write_flash_sr()
1085 return stlink_write_debug32(sl, sr_reg, val); in write_flash_sr()
1088 static inline unsigned int is_flash_busy(stlink_t *sl) { in is_flash_busy() argument
1092 if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || in is_flash_busy()
1093 (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) || in is_flash_busy()
1094 (sl->flash_type == STLINK_FLASH_TYPE_L0)) { in is_flash_busy()
1096 } else if (sl->flash_type == STLINK_FLASH_TYPE_F4) { in is_flash_busy()
1098 } else if (sl->flash_type == STLINK_FLASH_TYPE_F7) { in is_flash_busy()
1100 } else if (sl->flash_type == STLINK_FLASH_TYPE_L4) { in is_flash_busy()
1102 } else if (sl->flash_type == STLINK_FLASH_TYPE_G0 || in is_flash_busy()
1103 sl->flash_type == STLINK_FLASH_TYPE_G4) { in is_flash_busy()
1105 } else if (sl->flash_type == STLINK_FLASH_TYPE_WB) { in is_flash_busy()
1107 } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { in is_flash_busy()
1114 res = read_flash_sr(sl, BANK_1) & (1 << sr_busy_shift); in is_flash_busy()
1116 if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || in is_flash_busy()
1117 (sl->flash_type == STLINK_FLASH_TYPE_H7 && in is_flash_busy()
1118 sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { in is_flash_busy()
1119 res |= read_flash_sr(sl, BANK_2) & (1 << sr_busy_shift); in is_flash_busy()
1125 static void wait_flash_busy(stlink_t *sl) { in wait_flash_busy() argument
1127 while (is_flash_busy(sl)) in wait_flash_busy()
1131 static void wait_flash_busy_progress(stlink_t *sl) { in wait_flash_busy_progress() argument
1136 while (is_flash_busy(sl)) { in wait_flash_busy_progress()
1149 static void clear_flash_error(stlink_t *sl) { in clear_flash_error() argument
1150 switch (sl->flash_type) { in clear_flash_error()
1152 write_flash_sr(sl, BANK_1, FLASH_SR_ERROR_MASK); in clear_flash_error()
1155 write_flash_sr(sl, BANK_1, FLASH_F4_SR_ERROR_MASK); in clear_flash_error()
1158 write_flash_sr(sl, BANK_1, FLASH_F7_SR_ERROR_MASK); in clear_flash_error()
1162 write_flash_sr(sl, BANK_1, STM32Gx_FLASH_SR_ERROR_MASK); in clear_flash_error()
1165 write_flash_sr(sl, BANK_1, STM32L0_FLASH_SR_ERROR_MASK); in clear_flash_error()
1168 write_flash_sr(sl, BANK_1, STM32L4_FLASH_SR_ERROR_MASK); in clear_flash_error()
1171 write_flash_sr(sl, BANK_1, FLASH_H7_SR_ERROR_MASK); in clear_flash_error()
1172 if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { in clear_flash_error()
1173 write_flash_sr(sl, BANK_2, FLASH_H7_SR_ERROR_MASK); in clear_flash_error()
1177 write_flash_sr(sl, BANK_1, STM32WB_FLASH_SR_ERROR_MASK); in clear_flash_error()
1184 static int check_flash_error(stlink_t *sl) { in check_flash_error() argument
1190 switch (sl->flash_type) { in check_flash_error()
1193 res = read_flash_sr(sl, BANK_1) & FLASH_SR_ERROR_MASK; in check_flash_error()
1194 if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { in check_flash_error()
1195 res |= read_flash_sr(sl, BANK_2) & FLASH_SR_ERROR_MASK; in check_flash_error()
1201 res = read_flash_sr(sl, BANK_1) & FLASH_F4_SR_ERROR_MASK; in check_flash_error()
1206 res = read_flash_sr(sl, BANK_1) & FLASH_F7_SR_ERROR_MASK; in check_flash_error()
1212 res = read_flash_sr(sl, BANK_1) & STM32Gx_FLASH_SR_ERROR_MASK; in check_flash_error()
1218 res = read_flash_sr(sl, BANK_1) & STM32L0_FLASH_SR_ERROR_MASK; in check_flash_error()
1224 res = read_flash_sr(sl, BANK_1) & STM32L4_FLASH_SR_ERROR_MASK; in check_flash_error()
1230 res = read_flash_sr(sl, BANK_1) & FLASH_H7_SR_ERROR_MASK; in check_flash_error()
1231 if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { in check_flash_error()
1232 res |= read_flash_sr(sl, BANK_2) & FLASH_H7_SR_ERROR_MASK; in check_flash_error()
1237 res = read_flash_sr(sl, BANK_1) & STM32WB_FLASH_SR_ERROR_MASK; in check_flash_error()
1267 static void stop_wdg_in_debug(stlink_t *sl) { in stop_wdg_in_debug() argument
1272 switch (sl->flash_type) { in stop_wdg_in_debug()
1306 if (!stlink_read_debug32(sl, dbgmcu_cr, &value)) { in stop_wdg_in_debug()
1307 stlink_write_debug32(sl, dbgmcu_cr, value | set); in stop_wdg_in_debug()
1311 static void set_dma_state(stlink_t *sl, flash_loader_t *fl, int bckpRstr) { in set_dma_state() argument
1316 switch (sl->flash_type) { in set_dma_state()
1352 if (!stlink_read_debug32(sl, rcc, &value)) { in set_dma_state()
1359 stlink_write_debug32(sl, rcc, value); in set_dma_state()
1363 static inline void write_flash_ar(stlink_t *sl, uint32_t n, unsigned bank) { in write_flash_ar() argument
1364 stlink_write_debug32(sl, (bank == BANK_1) ? FLASH_AR : FLASH_AR2, n); in write_flash_ar()
1367 static inline void write_flash_cr_psiz(stlink_t *sl, uint32_t n, in write_flash_cr_psiz() argument
1370 uint32_t x = read_flash_cr(sl, bank); in write_flash_cr_psiz()
1372 if (sl->flash_type == STLINK_FLASH_TYPE_H7) { in write_flash_cr_psiz()
1385 stlink_write_debug32(sl, cr_reg, x); in write_flash_cr_psiz()
1388 static inline void write_flash_cr_snb(stlink_t *sl, uint32_t n, unsigned bank) { in write_flash_cr_snb() argument
1390 uint32_t x = read_flash_cr(sl, bank); in write_flash_cr_snb()
1392 if (sl->flash_type == STLINK_FLASH_TYPE_H7) { in write_flash_cr_snb()
1410 stlink_write_debug32(sl, cr_reg, x); in write_flash_cr_snb()
1413 static inline void write_flash_cr_bker_pnb(stlink_t *sl, uint32_t n) { in write_flash_cr_bker_pnb() argument
1414 stlink_write_debug32(sl, STM32L4_FLASH_SR, in write_flash_cr_bker_pnb()
1416 uint32_t x = read_flash_cr(sl, BANK_1); in write_flash_cr_bker_pnb()
1426 stlink_write_debug32(sl, STM32L4_FLASH_CR, x); in write_flash_cr_bker_pnb()
1431 void stlink_close(stlink_t *sl) { in stlink_close() argument
1434 if (!sl) { in stlink_close()
1438 sl->backend->close(sl); in stlink_close()
1439 free(sl); in stlink_close()
1442 int stlink_exit_debug_mode(stlink_t *sl) { in stlink_exit_debug_mode() argument
1446 ret = stlink_write_debug32(sl, STLINK_REG_DHCSR, STLINK_REG_DHCSR_DBGKEY); in stlink_exit_debug_mode()
1452 return (sl->backend->exit_debug_mode(sl)); in stlink_exit_debug_mode()
1455 int stlink_enter_swd_mode(stlink_t *sl) { in stlink_enter_swd_mode() argument
1457 return (sl->backend->enter_swd_mode(sl)); in stlink_enter_swd_mode()
1461 int stlink_force_debug(stlink_t *sl) { in stlink_force_debug() argument
1463 int res = sl->backend->force_debug(sl); in stlink_force_debug()
1465 stop_wdg_in_debug(sl); in stlink_force_debug()
1469 int stlink_exit_dfu_mode(stlink_t *sl) { in stlink_exit_dfu_mode() argument
1471 return (sl->backend->exit_dfu_mode(sl)); in stlink_exit_dfu_mode()
1474 int stlink_core_id(stlink_t *sl) { in stlink_core_id() argument
1478 ret = sl->backend->core_id(sl); in stlink_core_id()
1485 if (sl->verbose > 2) { in stlink_core_id()
1486 stlink_print_data(sl); in stlink_core_id()
1489 DLOG("core_id = 0x%08x\n", sl->core_id); in stlink_core_id()
1495 int stlink_chip_id(stlink_t *sl, uint32_t *chip_id) { in stlink_chip_id() argument
1500 if (stlink_cpu_id(sl, &cpu_id) || in stlink_chip_id()
1513 if ((sl->core_id == STM32H7_CORE_ID || sl->core_id == STM32H7_CORE_ID_JTAG) && in stlink_chip_id()
1516 ret = stlink_read_debug32(sl, 0x5c001000, chip_id); in stlink_chip_id()
1522 ret = stlink_read_debug32(sl, 0x40015800, chip_id); in stlink_chip_id()
1525 ret = stlink_read_debug32(sl, 0xE0044000, chip_id); in stlink_chip_id()
1537 ret = stlink_read_debug32(sl, 0xE0042000, chip_id); in stlink_chip_id()
1561 int stlink_cpu_id(stlink_t *sl, cortex_m3_cpuid_t *cpuid) { in stlink_cpu_id() argument
1564 if (stlink_read_debug32(sl, STLINK_REG_CM3_CPUID, &raw)) { in stlink_cpu_id()
1584 int stlink_load_device_params(stlink_t *sl) { in stlink_load_device_params() argument
1589 stlink_core_id(sl); in stlink_load_device_params()
1592 if (stlink_chip_id(sl, &sl->chip_id)) { in stlink_load_device_params()
1596 params = stlink_chipid_get_params(sl->chip_id); in stlink_load_device_params()
1599 WLOG("unknown chip id! %#x\n", sl->chip_id); in stlink_load_device_params()
1605 sl->flash_size = 0; in stlink_load_device_params()
1610 sl->flash_base = STM32_FLASH_BASE; in stlink_load_device_params()
1611 sl->sram_base = STM32_SRAM_BASE; in stlink_load_device_params()
1612 stlink_read_debug32(sl, (params->flash_size_reg) & ~3, &flash_size); in stlink_load_device_params()
1620 if ((sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM || in stlink_load_device_params()
1621 sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW || in stlink_load_device_params()
1622 sl->chip_id == STLINK_CHIPID_STM32_L1_MEDIUM_PLUS) && in stlink_load_device_params()
1624 sl->flash_size = 128 * 1024; in stlink_load_device_params()
1625 } else if (sl->chip_id == STLINK_CHIPID_STM32_L1_CAT2) { in stlink_load_device_params()
1626 sl->flash_size = (flash_size & 0xff) * 1024; in stlink_load_device_params()
1627 } else if ((sl->chip_id & 0xFFF) == STLINK_CHIPID_STM32_L1_HIGH) { in stlink_load_device_params()
1630 sl->flash_size = 384 * 1024; in stlink_load_device_params()
1632 sl->flash_size = 256 * 1024; in stlink_load_device_params()
1635 sl->flash_size = flash_size * 1024; in stlink_load_device_params()
1638 sl->flash_type = params->flash_type; in stlink_load_device_params()
1639 sl->flash_pgsz = params->flash_pagesize; in stlink_load_device_params()
1640 sl->sram_size = params->sram_size; in stlink_load_device_params()
1641 sl->sys_base = params->bootrom_base; in stlink_load_device_params()
1642 sl->sys_size = params->bootrom_size; in stlink_load_device_params()
1643 sl->option_base = params->option_base; in stlink_load_device_params()
1644 sl->option_size = params->option_size; in stlink_load_device_params()
1645 sl->chip_flags = params->flags; in stlink_load_device_params()
1649 if (sl->chip_id == STLINK_CHIPID_STM32_F1_VL_MEDIUM_LOW && in stlink_load_device_params()
1650 sl->flash_size < 64 * 1024) { in stlink_load_device_params()
1651 sl->sram_size = 0x1000; in stlink_load_device_params()
1654 if (sl->chip_id == STLINK_CHIPID_STM32_G4_CAT3) { in stlink_load_device_params()
1656 stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, &flash_optr); in stlink_load_device_params()
1659 sl->flash_pgsz <<= 1; in stlink_load_device_params()
1664 if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK && in stlink_load_device_params()
1665 sl->flash_type == STLINK_FLASH_TYPE_H7) { in stlink_load_device_params()
1666 if ((flash_size / sl->flash_pgsz) <= 1) in stlink_load_device_params()
1667 sl->chip_flags &= ~CHIP_F_HAS_DUAL_BANK; in stlink_load_device_params()
1671 params->description, (unsigned)(sl->sram_size / 1024), in stlink_load_device_params()
1672 (unsigned)(sl->flash_size / 1024), in stlink_load_device_params()
1673 (sl->flash_pgsz < 1024) ? (unsigned)(sl->flash_pgsz) in stlink_load_device_params()
1674 : (unsigned)(sl->flash_pgsz / 1024), in stlink_load_device_params()
1675 (sl->flash_pgsz < 1024) ? "byte" : "KiB"); in stlink_load_device_params()
1680 int stlink_jtag_reset(stlink_t *sl, int value) { in stlink_jtag_reset() argument
1682 return (sl->backend->jtag_reset(sl, value)); in stlink_jtag_reset()
1685 int stlink_soft_reset(stlink_t *sl, int halt_on_reset) { in stlink_soft_reset() argument
1694 stlink_write_debug32(sl, STLINK_REG_DHCSR, in stlink_soft_reset()
1701 sl, STLINK_REG_CM3_DEMCR, in stlink_soft_reset()
1706 stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_VCATCH); in stlink_soft_reset()
1708 stlink_write_debug32(sl, STLINK_REG_CM3_DEMCR, in stlink_soft_reset()
1715 stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); in stlink_soft_reset()
1718 ret = stlink_write_debug32(sl, STLINK_REG_AIRCR, in stlink_soft_reset()
1732 stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); in stlink_soft_reset()
1738 stlink_read_debug32(sl, STLINK_REG_DFSR, &dfsr); in stlink_soft_reset()
1749 stlink_write_debug32(sl, STLINK_REG_DFSR, STLINK_REG_DFSR_CLEAR); in stlink_soft_reset()
1759 int stlink_reset(stlink_t *sl, enum reset_type type) { in stlink_reset() argument
1767 stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); in stlink_reset()
1772 if (sl->version.stlink_v > 1) { in stlink_reset()
1773 stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); in stlink_reset()
1776 stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_HIGH); in stlink_reset()
1778 if (sl->backend->reset(sl)) { in stlink_reset()
1790 stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); in stlink_reset()
1797 return stlink_soft_reset(sl, 0); in stlink_reset()
1804 stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); in stlink_reset()
1813 return stlink_soft_reset(sl, (type == RESET_SOFT_AND_HALT)); in stlink_reset()
1819 int stlink_run(stlink_t *sl, enum run_type type) { in stlink_run() argument
1826 stlink_read_reg(sl, 16, &rr); in stlink_run()
1829 stlink_write_reg(sl, rr.xpsr | (1 << 24), 16); in stlink_run()
1832 return (sl->backend->run(sl, type)); in stlink_run()
1835 int stlink_set_swdclk(stlink_t *sl, int freq_khz) { in stlink_set_swdclk() argument
1837 return (sl->backend->set_swdclk(sl, freq_khz)); in stlink_set_swdclk()
1840 int stlink_status(stlink_t *sl) { in stlink_status() argument
1844 ret = sl->backend->status(sl); in stlink_status()
1845 stlink_core_stat(sl); in stlink_status()
1854 void _parse_version(stlink_t *sl, stlink_version_t *slv) { in _parse_version() argument
1855 sl->version.flags = 0; in _parse_version()
1857 if (sl->version.stlink_v < 3) { in _parse_version()
1858 uint32_t b0 = sl->q_buf[0]; // lsb in _parse_version()
1859 uint32_t b1 = sl->q_buf[1]; in _parse_version()
1860 uint32_t b2 = sl->q_buf[2]; in _parse_version()
1861 uint32_t b3 = sl->q_buf[3]; in _parse_version()
1862 uint32_t b4 = sl->q_buf[4]; in _parse_version()
1863 uint32_t b5 = sl->q_buf[5]; // msb in _parse_version()
1883 if (sl->version.jtag_v >= 15) { in _parse_version()
1884 sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; in _parse_version()
1887 if (sl->version.jtag_v >= 13) { in _parse_version()
1888 sl->version.flags |= STLINK_F_HAS_TRACE; in _parse_version()
1889 sl->max_trace_freq = STLINK_V2_MAX_TRACE_FREQUENCY; in _parse_version()
1896 slv->stlink_v = sl->q_buf[0]; in _parse_version()
1897 slv->swim_v = sl->q_buf[1]; in _parse_version()
1898 slv->jtag_v = sl->q_buf[2]; in _parse_version()
1899 slv->st_vid = (uint32_t)((sl->q_buf[9] << 8) | sl->q_buf[8]); in _parse_version()
1900 slv->stlink_pid = (uint32_t)((sl->q_buf[11] << 8) | sl->q_buf[10]); in _parse_version()
1903 sl->version.flags |= STLINK_F_HAS_GETLASTRWSTATUS2; in _parse_version()
1904 sl->version.flags |= STLINK_F_HAS_TRACE; in _parse_version()
1905 sl->max_trace_freq = STLINK_V3_MAX_TRACE_FREQUENCY; in _parse_version()
1911 int stlink_version(stlink_t *sl) { in stlink_version() argument
1914 if (sl->backend->version(sl)) { in stlink_version()
1918 _parse_version(sl, &sl->version); in stlink_version()
1920 DLOG("st vid = 0x%04x (expect 0x%04x)\n", sl->version.st_vid, in stlink_version()
1922 DLOG("stlink pid = 0x%04x\n", sl->version.stlink_pid); in stlink_version()
1923 DLOG("stlink version = 0x%x\n", sl->version.stlink_v); in stlink_version()
1924 DLOG("jtag version = 0x%x\n", sl->version.jtag_v); in stlink_version()
1925 DLOG("swim version = 0x%x\n", sl->version.swim_v); in stlink_version()
1927 if (sl->version.jtag_v == 0) { in stlink_version()
1931 if (sl->version.swim_v == 0) { in stlink_version()
1938 int stlink_target_voltage(stlink_t *sl) { in stlink_target_voltage() argument
1942 if (sl->backend->target_voltage != NULL) { in stlink_target_voltage()
1943 voltage = sl->backend->target_voltage(sl); in stlink_target_voltage()
1957 int stlink_read_debug32(stlink_t *sl, uint32_t addr, uint32_t *data) { in stlink_read_debug32() argument
1960 ret = sl->backend->read_debug32(sl, addr, data); in stlink_read_debug32()
1967 int stlink_write_debug32(stlink_t *sl, uint32_t addr, uint32_t data) { in stlink_write_debug32() argument
1969 return sl->backend->write_debug32(sl, addr, data); in stlink_write_debug32()
1972 int stlink_write_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { in stlink_write_mem32() argument
1980 return (sl->backend->write_mem32(sl, addr, len)); in stlink_write_mem32()
1983 int stlink_read_mem32(stlink_t *sl, uint32_t addr, uint16_t len) { in stlink_read_mem32() argument
1991 return (sl->backend->read_mem32(sl, addr, len)); in stlink_read_mem32()
1994 int stlink_write_mem8(stlink_t *sl, uint32_t addr, uint16_t len) { in stlink_write_mem8() argument
2003 return (sl->backend->write_mem8(sl, addr, len)); in stlink_write_mem8()
2006 int stlink_read_all_regs(stlink_t *sl, struct stlink_reg *regp) { in stlink_read_all_regs() argument
2008 return (sl->backend->read_all_regs(sl, regp)); in stlink_read_all_regs()
2011 int stlink_read_all_unsupported_regs(stlink_t *sl, struct stlink_reg *regp) { in stlink_read_all_unsupported_regs() argument
2013 return (sl->backend->read_all_unsupported_regs(sl, regp)); in stlink_read_all_unsupported_regs()
2016 int stlink_write_reg(stlink_t *sl, uint32_t reg, int idx) { in stlink_write_reg() argument
2018 return (sl->backend->write_reg(sl, reg, idx)); in stlink_write_reg()
2021 int stlink_read_reg(stlink_t *sl, int r_idx, struct stlink_reg *regp) { in stlink_read_reg() argument
2030 return (sl->backend->read_reg(sl, r_idx, regp)); in stlink_read_reg()
2033 int stlink_read_unsupported_reg(stlink_t *sl, int r_idx, in stlink_read_unsupported_reg() argument
2053 return (sl->backend->read_unsupported_reg(sl, r_convert, regp)); in stlink_read_unsupported_reg()
2056 int stlink_write_unsupported_reg(stlink_t *sl, uint32_t val, int r_idx, in stlink_write_unsupported_reg() argument
2076 return (sl->backend->write_unsupported_reg(sl, val, r_convert, regp)); in stlink_write_unsupported_reg()
2079 bool stlink_is_core_halted(stlink_t *sl) { in stlink_is_core_halted() argument
2080 stlink_status(sl); in stlink_is_core_halted()
2081 return (sl->core_stat == TARGET_HALTED); in stlink_is_core_halted()
2084 int stlink_step(stlink_t *sl) { in stlink_step() argument
2086 return (sl->backend->step(sl)); in stlink_step()
2089 int stlink_current_mode(stlink_t *sl) { in stlink_current_mode() argument
2090 int mode = sl->backend->current_mode(sl); in stlink_current_mode()
2108 int stlink_trace_enable(stlink_t *sl, uint32_t frequency) { in stlink_trace_enable() argument
2110 return (sl->backend->trace_enable(sl, frequency)); in stlink_trace_enable()
2113 int stlink_trace_disable(stlink_t *sl) { in stlink_trace_disable() argument
2115 return (sl->backend->trace_disable(sl)); in stlink_trace_disable()
2118 int stlink_trace_read(stlink_t *sl, uint8_t *buf, size_t size) { in stlink_trace_read() argument
2119 return (sl->backend->trace_read(sl, buf, size)); in stlink_trace_read()
2126 void stlink_run_at(stlink_t *sl, stm32_addr_t addr) { in stlink_run_at() argument
2127 stlink_write_reg(sl, addr, 15); /* pc register */ in stlink_run_at()
2128 stlink_run(sl, RUN_NORMAL); in stlink_run_at()
2130 while (stlink_is_core_halted(sl)) { in stlink_run_at()
2137 void stlink_core_stat(stlink_t *sl) { in stlink_core_stat() argument
2138 switch (sl->core_stat) { in stlink_core_stat()
2156 void stlink_print_data(stlink_t *sl) { in stlink_print_data() argument
2157 if (sl->q_len <= 0 || sl->verbose < UDEBUG) { in stlink_print_data()
2161 if (sl->verbose > 2) { in stlink_print_data()
2162 DLOG("data_len = %d 0x%x\n", sl->q_len, sl->q_len); in stlink_print_data()
2165 for (int i = 0; i < sl->q_len; i++) { in stlink_print_data()
2176 fprintf(stderr, " %02x", (unsigned int)sl->q_buf[i]); in stlink_print_data()
2240 static int check_file(stlink_t *sl, mapped_file_t *mf, stm32_addr_t addr) { in check_file() argument
2242 size_t n_cmp = sl->flash_pgsz; in check_file()
2263 stlink_read_mem32(sl, addr + (uint32_t)off, aligned_size); in check_file()
2265 if (memcmp(sl->q_buf, mf->base + off, cmp_size)) { in check_file()
2301 static void stlink_fwrite_finalize(stlink_t *sl, stm32_addr_t addr) { in stlink_fwrite_finalize() argument
2304 stlink_read_debug32(sl, addr, &val); in stlink_fwrite_finalize()
2305 stlink_write_reg(sl, val, 13); in stlink_fwrite_finalize()
2307 stlink_read_debug32(sl, addr + 4, &val); in stlink_fwrite_finalize()
2308 stlink_write_reg(sl, val, 15); in stlink_fwrite_finalize()
2309 stlink_run(sl, RUN_NORMAL); in stlink_fwrite_finalize()
2312 int stlink_mwrite_sram(stlink_t *sl, uint8_t *data, uint32_t length, in stlink_mwrite_sram() argument
2321 if (addr < sl->sram_base) { in stlink_mwrite_sram()
2327 } else if ((addr + length) > (sl->sram_base + sl->sram_size)) { in stlink_mwrite_sram()
2349 memcpy(sl->q_buf, data + off, size); in stlink_mwrite_sram()
2355 stlink_write_mem32(sl, addr + (uint32_t)off, size); in stlink_mwrite_sram()
2359 memcpy(sl->q_buf, data + len, length - len); in stlink_mwrite_sram()
2360 stlink_write_mem8(sl, addr + (uint32_t)len, length - len); in stlink_mwrite_sram()
2364 stlink_fwrite_finalize(sl, addr); in stlink_mwrite_sram()
2370 int stlink_fwrite_sram(stlink_t *sl, const char *path, stm32_addr_t addr) { in stlink_fwrite_sram() argument
2388 if (addr < sl->sram_base) { in stlink_fwrite_sram()
2394 } else if ((addr + mf.len) > (sl->sram_base + sl->sram_size)) { in stlink_fwrite_sram()
2416 memcpy(sl->q_buf, mf.base + off, size); in stlink_fwrite_sram()
2422 stlink_write_mem32(sl, addr + (uint32_t)off, size); in stlink_fwrite_sram()
2426 memcpy(sl->q_buf, mf.base + len, mf.len - len); in stlink_fwrite_sram()
2427 stlink_write_mem8(sl, addr + (uint32_t)len, mf.len - len); in stlink_fwrite_sram()
2431 if (check_file(sl, &mf, addr) == -1) { in stlink_fwrite_sram()
2437 stlink_fwrite_finalize(sl, addr); in stlink_fwrite_sram()
2446 static int stlink_read(stlink_t *sl, stm32_addr_t addr, size_t size, in stlink_read() argument
2452 size = sl->flash_size; in stlink_read()
2455 if (size > sl->flash_size) { in stlink_read()
2456 size = sl->flash_size; in stlink_read()
2459 size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; in stlink_read()
2475 stlink_read_mem32(sl, addr + (uint32_t)off, aligned_size); in stlink_read()
2477 if (!fn(fn_arg, sl->q_buf, aligned_size)) { in stlink_read()
2611 int stlink_fread(stlink_t *sl, const char *path, bool is_ihex, in stlink_fread() argument
2628 error = stlink_read(sl, addr, size, &stlink_fread_ihex_worker, &arg); in stlink_fread()
2638 error = stlink_read(sl, addr, size, &stlink_fread_worker, &arg); in stlink_fread()
2645 int write_buffer_to_sram(stlink_t *sl, flash_loader_t *fl, const uint8_t *buf, in write_buffer_to_sram() argument
2652 memcpy(sl->q_buf, buf, chunk); in write_buffer_to_sram()
2653 stlink_write_mem32(sl, fl->buf_addr, chunk); in write_buffer_to_sram()
2657 memcpy(sl->q_buf, buf + chunk, rem); in write_buffer_to_sram()
2658 stlink_write_mem8(sl, (fl->buf_addr) + (uint32_t)chunk, rem); in write_buffer_to_sram()
2700 uint32_t calculate_H7_sectornum(stlink_t *sl, uint32_t flashaddr, in calculate_H7_sectornum() argument
2706 return (flashaddr / sl->flash_pgsz); in calculate_H7_sectornum()
2710 uint32_t calculate_L4_page(stlink_t *sl, uint32_t flashaddr) { in calculate_L4_page() argument
2713 stlink_read_debug32(sl, STM32L4_FLASH_OPTR, &flashopt); in calculate_L4_page()
2716 if (sl->chip_id == STLINK_CHIPID_STM32_L4 || in calculate_L4_page()
2717 sl->chip_id == STLINK_CHIPID_STM32_L496X || in calculate_L4_page()
2718 sl->chip_id == STLINK_CHIPID_STM32_L4RX) { in calculate_L4_page()
2721 uint32_t banksize = (uint32_t)sl->flash_size / 2; in calculate_L4_page()
2732 return (bker | flashaddr / (uint32_t)sl->flash_pgsz); in calculate_L4_page()
2735 uint32_t stlink_calculate_pagesize(stlink_t *sl, uint32_t flashaddr) { in stlink_calculate_pagesize() argument
2736 if ((sl->chip_id == STLINK_CHIPID_STM32_F2) || in stlink_calculate_pagesize()
2737 (sl->chip_id == STLINK_CHIPID_STM32_F4) || in stlink_calculate_pagesize()
2738 (sl->chip_id == STLINK_CHIPID_STM32_F4_DE) || in stlink_calculate_pagesize()
2739 (sl->chip_id == STLINK_CHIPID_STM32_F4_LP) || in stlink_calculate_pagesize()
2740 (sl->chip_id == STLINK_CHIPID_STM32_F4_HD) || in stlink_calculate_pagesize()
2741 (sl->chip_id == STLINK_CHIPID_STM32_F411RE) || in stlink_calculate_pagesize()
2742 (sl->chip_id == STLINK_CHIPID_STM32_F446) || in stlink_calculate_pagesize()
2743 (sl->chip_id == STLINK_CHIPID_STM32_F4_DSI) || in stlink_calculate_pagesize()
2744 (sl->chip_id == STLINK_CHIPID_STM32_F72XXX) || in stlink_calculate_pagesize()
2745 (sl->chip_id == STLINK_CHIPID_STM32_F412)) { in stlink_calculate_pagesize()
2753 sl->flash_pgsz = 0x4000; in stlink_calculate_pagesize()
2755 sl->flash_pgsz = 0x10000; in stlink_calculate_pagesize()
2757 sl->flash_pgsz = 0x20000; in stlink_calculate_pagesize()
2759 } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || in stlink_calculate_pagesize()
2760 sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { in stlink_calculate_pagesize()
2764 sl->flash_pgsz = 0x8000; in stlink_calculate_pagesize()
2766 sl->flash_pgsz = 0x20000; in stlink_calculate_pagesize()
2768 sl->flash_pgsz = 0x40000; in stlink_calculate_pagesize()
2772 return ((uint32_t)sl->flash_pgsz); in stlink_calculate_pagesize()
2782 int stlink_erase_flash_page(stlink_t *sl, stm32_addr_t flashaddr) { in stlink_erase_flash_page() argument
2784 wait_flash_busy(sl); in stlink_erase_flash_page()
2786 clear_flash_error(sl); in stlink_erase_flash_page()
2788 if (sl->flash_type == STLINK_FLASH_TYPE_F4 || in stlink_erase_flash_page()
2789 sl->flash_type == STLINK_FLASH_TYPE_F7 || in stlink_erase_flash_page()
2790 sl->flash_type == STLINK_FLASH_TYPE_L4) { in stlink_erase_flash_page()
2792 unlock_flash_if(sl); in stlink_erase_flash_page()
2795 if ((sl->chip_id == STLINK_CHIPID_STM32_L4) || in stlink_erase_flash_page()
2796 (sl->chip_id == STLINK_CHIPID_STM32_L43X) || in stlink_erase_flash_page()
2797 (sl->chip_id == STLINK_CHIPID_STM32_L46X) || in stlink_erase_flash_page()
2798 (sl->chip_id == STLINK_CHIPID_STM32_L496X) || in stlink_erase_flash_page()
2799 (sl->chip_id == STLINK_CHIPID_STM32_L4RX)) { in stlink_erase_flash_page()
2801 uint32_t page = calculate_L4_page(sl, flashaddr); in stlink_erase_flash_page()
2804 stlink_calculate_pagesize(sl, flashaddr)); in stlink_erase_flash_page()
2806 write_flash_cr_bker_pnb(sl, page); in stlink_erase_flash_page()
2807 } else if (sl->chip_id == STLINK_CHIPID_STM32_F7 || in stlink_erase_flash_page()
2808 sl->chip_id == STLINK_CHIPID_STM32_F7XXXX) { in stlink_erase_flash_page()
2813 stlink_calculate_pagesize(sl, flashaddr)); in stlink_erase_flash_page()
2814 write_flash_cr_snb(sl, sector, BANK_1); in stlink_erase_flash_page()
2820 stlink_calculate_pagesize(sl, flashaddr)); in stlink_erase_flash_page()
2828 write_flash_cr_snb(sl, sector, BANK_1); in stlink_erase_flash_page()
2831 set_flash_cr_strt(sl, BANK_1); // start erase operation in stlink_erase_flash_page()
2832 wait_flash_busy(sl); // wait for completion in stlink_erase_flash_page()
2833 lock_flash(sl); // TODO: fails to program if this is in in stlink_erase_flash_page()
2835 fprintf(stdout, "Erase Final CR:0x%x\n", read_flash_cr(sl, BANK_1)); in stlink_erase_flash_page()
2837 } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { in stlink_erase_flash_page()
2840 uint32_t flash_regs_base = get_stm32l0_flash_base(sl); in stlink_erase_flash_page()
2843 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); in stlink_erase_flash_page()
2847 stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, in stlink_erase_flash_page()
2849 stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, in stlink_erase_flash_page()
2853 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); in stlink_erase_flash_page()
2861 stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, in stlink_erase_flash_page()
2863 stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, in stlink_erase_flash_page()
2867 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); in stlink_erase_flash_page()
2877 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); in stlink_erase_flash_page()
2880 stlink_write_debug32(sl, flashaddr, 0); in stlink_erase_flash_page()
2887 wait_flash_busy(sl); in stlink_erase_flash_page()
2890 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); in stlink_erase_flash_page()
2892 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); in stlink_erase_flash_page()
2893 } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || in stlink_erase_flash_page()
2894 sl->flash_type == STLINK_FLASH_TYPE_G0 || in stlink_erase_flash_page()
2895 sl->flash_type == STLINK_FLASH_TYPE_G4) { in stlink_erase_flash_page()
2897 unlock_flash_if(sl); in stlink_erase_flash_page()
2898 set_flash_cr_per(sl, BANK_1); // set the 'enable Flash erase' bit in stlink_erase_flash_page()
2901 if (sl->flash_type == STLINK_FLASH_TYPE_WB) { in stlink_erase_flash_page()
2903 ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); in stlink_erase_flash_page()
2904 stlink_read_debug32(sl, STM32WB_FLASH_CR, &val); in stlink_erase_flash_page()
2910 stlink_write_debug32(sl, STM32WB_FLASH_CR, val); in stlink_erase_flash_page()
2911 } else if (sl->flash_type == STLINK_FLASH_TYPE_G0) { in stlink_erase_flash_page()
2913 ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); in stlink_erase_flash_page()
2914 stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); in stlink_erase_flash_page()
2918 stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); in stlink_erase_flash_page()
2919 } else if (sl->flash_type == STLINK_FLASH_TYPE_G4) { in stlink_erase_flash_page()
2921 ((flashaddr - STM32_FLASH_BASE) / (uint32_t)(sl->flash_pgsz)); in stlink_erase_flash_page()
2922 stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); in stlink_erase_flash_page()
2926 stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); in stlink_erase_flash_page()
2929 set_flash_cr_strt(sl, BANK_1); // set the 'start operation' bit in stlink_erase_flash_page()
2930 wait_flash_busy(sl); // wait for the 'busy' bit to clear in stlink_erase_flash_page()
2931 clear_flash_cr_per(sl, BANK_1); // clear the 'enable page erase' bit in stlink_erase_flash_page()
2932 lock_flash(sl); in stlink_erase_flash_page()
2933 } else if (sl->flash_type == STLINK_FLASH_TYPE_F0 || in stlink_erase_flash_page()
2934 sl->flash_type == STLINK_FLASH_TYPE_F1_XL) { in stlink_erase_flash_page()
2936 unlock_flash_if(sl); in stlink_erase_flash_page()
2937 clear_flash_cr_pg(sl, bank); // clear the pg bit in stlink_erase_flash_page()
2938 set_flash_cr_per(sl, bank); // set the page erase bit in stlink_erase_flash_page()
2939 write_flash_ar(sl, flashaddr, bank); // select the page to erase in stlink_erase_flash_page()
2940 set_flash_cr_strt(sl, in stlink_erase_flash_page()
2942 wait_flash_busy(sl); in stlink_erase_flash_page()
2943 clear_flash_cr_per(sl, bank); // clear the page erase bit in stlink_erase_flash_page()
2944 lock_flash(sl); in stlink_erase_flash_page()
2945 } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { in stlink_erase_flash_page()
2947 unlock_flash_if(sl); // unlock if locked in stlink_erase_flash_page()
2949 sl, flashaddr, bank); // calculate the actual page from the address in stlink_erase_flash_page()
2950 write_flash_cr_snb(sl, sector, bank); // select the page to erase in stlink_erase_flash_page()
2951 set_flash_cr_strt(sl, bank); // start erase operation in stlink_erase_flash_page()
2952 wait_flash_busy(sl); // wait for completion in stlink_erase_flash_page()
2953 lock_flash(sl); in stlink_erase_flash_page()
2955 WLOG("unknown coreid %x, page erase failed\n", sl->core_id); in stlink_erase_flash_page()
2959 return check_flash_error(sl); in stlink_erase_flash_page()
2962 int stlink_erase_flash_mass(stlink_t *sl) { in stlink_erase_flash_mass() argument
2966 if (sl->flash_type == STLINK_FLASH_TYPE_L0 || in stlink_erase_flash_mass()
2967 sl->flash_type == STLINK_FLASH_TYPE_WB) { in stlink_erase_flash_mass()
2969 int i = 0, num_pages = (int)(sl->flash_size / sl->flash_pgsz); in stlink_erase_flash_mass()
2974 (stm32_addr_t)sl->flash_base + i * (stm32_addr_t)sl->flash_pgsz; in stlink_erase_flash_mass()
2976 if (stlink_erase_flash_page(sl, addr)) { in stlink_erase_flash_mass()
2987 wait_flash_busy(sl); in stlink_erase_flash_mass()
2988 clear_flash_error(sl); in stlink_erase_flash_mass()
2989 unlock_flash_if(sl); in stlink_erase_flash_mass()
2991 if (sl->flash_type == STLINK_FLASH_TYPE_H7 && in stlink_erase_flash_mass()
2992 sl->chip_id != STLINK_CHIPID_STM32_H7AX) { in stlink_erase_flash_mass()
2994 write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); in stlink_erase_flash_mass()
2995 if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { in stlink_erase_flash_mass()
2996 write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); in stlink_erase_flash_mass()
3000 set_flash_cr_mer(sl, 1, BANK_1); // set the mass erase bit in stlink_erase_flash_mass()
3002 sl, BANK_1); // start erase operation, reset by hw with busy bit in stlink_erase_flash_mass()
3004 if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || in stlink_erase_flash_mass()
3005 (sl->flash_type == STLINK_FLASH_TYPE_H7 && in stlink_erase_flash_mass()
3006 sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { in stlink_erase_flash_mass()
3007 set_flash_cr_mer(sl, 1, BANK_2); // set the mass erase bit in bank 2 in stlink_erase_flash_mass()
3008 set_flash_cr_strt(sl, BANK_2); // start erase operation in bank 2 in stlink_erase_flash_mass()
3011 wait_flash_busy_progress(sl); in stlink_erase_flash_mass()
3012 lock_flash(sl); in stlink_erase_flash_mass()
3015 set_flash_cr_mer(sl, 0, BANK_1); in stlink_erase_flash_mass()
3016 if (sl->flash_type == STLINK_FLASH_TYPE_F1_XL || in stlink_erase_flash_mass()
3017 (sl->flash_type == STLINK_FLASH_TYPE_H7 && in stlink_erase_flash_mass()
3018 sl->chip_flags & CHIP_F_HAS_DUAL_BANK)) { in stlink_erase_flash_mass()
3019 set_flash_cr_mer(sl, 0, BANK_2); in stlink_erase_flash_mass()
3022 err = check_flash_error(sl); in stlink_erase_flash_mass()
3028 int stlink_fcheck_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { in stlink_fcheck_flash() argument
3038 res = check_file(sl, &mf, addr); in stlink_fcheck_flash()
3051 int stlink_verify_write_flash(stlink_t *sl, stm32_addr_t address, uint8_t *data, in stlink_verify_write_flash() argument
3054 size_t cmp_size = (sl->flash_pgsz > 0x1800) ? 0x1800 : sl->flash_pgsz; in stlink_verify_write_flash()
3071 stlink_read_mem32(sl, address + (uint32_t)off, aligned_size); in stlink_verify_write_flash()
3073 if (memcmp(sl->q_buf, data + off, cmp_size)) { in stlink_verify_write_flash()
3083 int stm32l1_write_half_pages(stlink_t *sl, stm32_addr_t addr, uint8_t *base, in stm32l1_write_half_pages() argument
3088 uint32_t flash_regs_base = get_stm32l0_flash_base(sl); in stm32l1_write_half_pages()
3094 if (stlink_flash_loader_init(sl, &fl) == -1) { in stm32l1_write_half_pages()
3100 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); in stm32l1_write_half_pages()
3102 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); in stm32l1_write_half_pages()
3105 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); in stm32l1_write_half_pages()
3107 wait_flash_busy(sl); in stm32l1_write_half_pages()
3110 if (stlink_flash_loader_run(sl, &fl, addr + count * pagesize, in stm32l1_write_half_pages()
3114 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); in stm32l1_write_half_pages()
3116 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); in stm32l1_write_half_pages()
3121 if (sl->verbose >= 1) { in stm32l1_write_half_pages()
3128 wait_flash_busy(sl); in stm32l1_write_half_pages()
3131 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); in stm32l1_write_half_pages()
3133 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); in stm32l1_write_half_pages()
3134 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); in stm32l1_write_half_pages()
3136 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); in stm32l1_write_half_pages()
3140 int stlink_flashloader_start(stlink_t *sl, flash_loader_t *fl) { in stlink_flashloader_start() argument
3143 stlink_write_debug32(sl, STLINK_REG_DHCSR, in stlink_flashloader_start()
3147 stlink_write_debug32(sl, STLINK_REG_DHCSR, in stlink_flashloader_start()
3153 set_dma_state(sl, fl, 0); in stlink_flashloader_start()
3156 wait_flash_busy(sl); in stlink_flashloader_start()
3158 clear_flash_error(sl); in stlink_flashloader_start()
3160 if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || in stlink_flashloader_start()
3161 (sl->flash_type == STLINK_FLASH_TYPE_F7) || in stlink_flashloader_start()
3162 (sl->flash_type == STLINK_FLASH_TYPE_L4)) { in stlink_flashloader_start()
3166 if (stlink_flash_loader_init(sl, fl) == -1) { in stlink_flashloader_start()
3171 unlock_flash_if(sl); // first unlock the cr in stlink_flashloader_start()
3174 if (sl->version.stlink_v == 1) { in stlink_flashloader_start()
3178 voltage = stlink_target_voltage(sl); in stlink_flashloader_start()
3186 if (sl->flash_type == STLINK_FLASH_TYPE_L4) { in stlink_flashloader_start()
3195 write_flash_cr_psiz(sl, 2, BANK_1); in stlink_flashloader_start()
3200 write_flash_cr_psiz(sl, 0, BANK_1); in stlink_flashloader_start()
3205 set_flash_cr_pg(sl, BANK_1); in stlink_flashloader_start()
3206 } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || in stlink_flashloader_start()
3207 sl->flash_type == STLINK_FLASH_TYPE_G0 || in stlink_flashloader_start()
3208 sl->flash_type == STLINK_FLASH_TYPE_G4) { in stlink_flashloader_start()
3211 unlock_flash_if(sl); // unlock flash if necessary in stlink_flashloader_start()
3212 set_flash_cr_pg(sl, BANK_1); // set PG 'allow programming' bit in stlink_flashloader_start()
3213 } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { in stlink_flashloader_start()
3218 if (sl->chip_id == STLINK_CHIPID_STM32_L0 || in stlink_flashloader_start()
3219 sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || in stlink_flashloader_start()
3220 sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || in stlink_flashloader_start()
3221 sl->chip_id == STLINK_CHIPID_STM32_L011) { in stlink_flashloader_start()
3228 stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, in stlink_flashloader_start()
3230 stlink_write_debug32(sl, flash_regs_base + FLASH_PEKEYR_OFF, in stlink_flashloader_start()
3234 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); in stlink_flashloader_start()
3241 stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, in stlink_flashloader_start()
3243 stlink_write_debug32(sl, flash_regs_base + FLASH_PRGKEYR_OFF, in stlink_flashloader_start()
3247 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); in stlink_flashloader_start()
3252 } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || in stlink_flashloader_start()
3253 (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { in stlink_flashloader_start()
3257 if (stlink_flash_loader_init(sl, fl) == -1) { in stlink_flashloader_start()
3261 } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { in stlink_flashloader_start()
3264 unlock_flash_if(sl); // unlock the cr in stlink_flashloader_start()
3265 set_flash_cr_pg(sl, BANK_1); // set programming mode in stlink_flashloader_start()
3266 if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { in stlink_flashloader_start()
3267 set_flash_cr_pg(sl, BANK_2); in stlink_flashloader_start()
3269 if (sl->chip_id != STLINK_CHIPID_STM32_H7AX) { in stlink_flashloader_start()
3271 write_flash_cr_psiz(sl, 3 /*64it*/, BANK_1); in stlink_flashloader_start()
3272 if (sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { in stlink_flashloader_start()
3273 write_flash_cr_psiz(sl, 3 /*64bit*/, BANK_2); in stlink_flashloader_start()
3277 ELOG("unknown coreid, not sure how to write: %x\n", sl->core_id); in stlink_flashloader_start()
3284 int stlink_flashloader_write(stlink_t *sl, flash_loader_t *fl, in stlink_flashloader_write() argument
3287 if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || in stlink_flashloader_write()
3288 (sl->flash_type == STLINK_FLASH_TYPE_F7) || in stlink_flashloader_write()
3289 (sl->flash_type == STLINK_FLASH_TYPE_L4)) { in stlink_flashloader_write()
3290 size_t buf_size = (sl->sram_size > 0x8000) ? 0x8000 : 0x4000; in stlink_flashloader_write()
3293 if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, in stlink_flashloader_write()
3297 check_flash_error(sl); in stlink_flashloader_write()
3303 } else if (sl->flash_type == STLINK_FLASH_TYPE_WB || in stlink_flashloader_write()
3304 sl->flash_type == STLINK_FLASH_TYPE_G0 || in stlink_flashloader_write()
3305 sl->flash_type == STLINK_FLASH_TYPE_G4) { in stlink_flashloader_write()
3306 DLOG("Starting %3u page write\r\n", (unsigned int)(len / sl->flash_pgsz)); in stlink_flashloader_write()
3310 if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { in stlink_flashloader_write()
3312 (unsigned int)(off / sl->flash_pgsz), in stlink_flashloader_write()
3313 (unsigned int)(len / sl->flash_pgsz)); in stlink_flashloader_write()
3318 stlink_write_debug32(sl, addr + (uint32_t)off, data); in stlink_flashloader_write()
3319 wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear in stlink_flashloader_write()
3325 stlink_write_debug32(sl, addr + (uint32_t)off, in stlink_flashloader_write()
3327 wait_flash_busy(sl); // wait for 'busy' bit in FLASH_SR to clear in stlink_flashloader_write()
3329 } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { in stlink_flashloader_write()
3334 if (sl->chip_id == STLINK_CHIPID_STM32_L0 || in stlink_flashloader_write()
3335 sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || in stlink_flashloader_write()
3336 sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || in stlink_flashloader_write()
3337 sl->chip_id == STLINK_CHIPID_STM32_L011) { in stlink_flashloader_write()
3348 if (stm32l1_write_half_pages(sl, addr, base, len, pagesize) == -1) { in stlink_flashloader_write()
3360 if ((off % sl->flash_pgsz) > (sl->flash_pgsz - 5)) { in stlink_flashloader_write()
3362 (unsigned int)(off / sl->flash_pgsz), in stlink_flashloader_write()
3363 (unsigned int)(len / sl->flash_pgsz)); in stlink_flashloader_write()
3368 stlink_write_debug32(sl, addr + (uint32_t)off, data); in stlink_flashloader_write()
3372 stlink_read_debug32(sl, flash_regs_base + FLASH_SR_OFF, &val); in stlink_flashloader_write()
3378 } else if ((sl->flash_type == STLINK_FLASH_TYPE_F0) || in stlink_flashloader_write()
3379 (sl->flash_type == STLINK_FLASH_TYPE_F1_XL)) { in stlink_flashloader_write()
3381 for (off = 0; off < len; off += sl->flash_pgsz) { in stlink_flashloader_write()
3383 size_t size = len - off > sl->flash_pgsz ? sl->flash_pgsz : len - off; in stlink_flashloader_write()
3386 unlock_flash_if(sl); in stlink_flashloader_write()
3390 if (stlink_flash_loader_run(sl, fl, addr + (uint32_t)off, base + off, in stlink_flashloader_write()
3394 check_flash_error(sl); in stlink_flashloader_write()
3398 lock_flash(sl); in stlink_flashloader_write()
3400 if (sl->verbose >= 1) { in stlink_flashloader_write()
3404 (unsigned int)((len + sl->flash_pgsz - 1) / sl->flash_pgsz)); in stlink_flashloader_write()
3408 if (sl->verbose >= 1) { in stlink_flashloader_write()
3411 } else if (sl->flash_type == STLINK_FLASH_TYPE_H7) { in stlink_flashloader_write()
3415 memcpy(sl->q_buf, base + off, chunk); in stlink_flashloader_write()
3416 stlink_write_mem32(sl, addr + (uint32_t)off, 64); in stlink_flashloader_write()
3417 wait_flash_busy(sl); in stlink_flashloader_write()
3421 if (sl->verbose >= 1) { in stlink_flashloader_write()
3428 if (sl->verbose >= 1) { in stlink_flashloader_write()
3435 return check_flash_error(sl); in stlink_flashloader_write()
3438 int stlink_flashloader_stop(stlink_t *sl, flash_loader_t *fl) { in stlink_flashloader_stop() argument
3441 if ((sl->flash_type == STLINK_FLASH_TYPE_F4) || in stlink_flashloader_stop()
3442 (sl->flash_type == STLINK_FLASH_TYPE_F7) || in stlink_flashloader_stop()
3443 (sl->flash_type == STLINK_FLASH_TYPE_L4) || in stlink_flashloader_stop()
3444 (sl->flash_type == STLINK_FLASH_TYPE_WB) || in stlink_flashloader_stop()
3445 (sl->flash_type == STLINK_FLASH_TYPE_G0) || in stlink_flashloader_stop()
3446 (sl->flash_type == STLINK_FLASH_TYPE_G4) || in stlink_flashloader_stop()
3447 (sl->flash_type == STLINK_FLASH_TYPE_H7)) { in stlink_flashloader_stop()
3449 clear_flash_cr_pg(sl, BANK_1); in stlink_flashloader_stop()
3450 if (sl->flash_type == STLINK_FLASH_TYPE_H7 && in stlink_flashloader_stop()
3451 sl->chip_flags & CHIP_F_HAS_DUAL_BANK) { in stlink_flashloader_stop()
3452 clear_flash_cr_pg(sl, BANK_2); in stlink_flashloader_stop()
3454 lock_flash(sl); in stlink_flashloader_stop()
3455 } else if (sl->flash_type == STLINK_FLASH_TYPE_L0) { in stlink_flashloader_stop()
3458 if (sl->chip_id == STLINK_CHIPID_STM32_L0 || in stlink_flashloader_stop()
3459 sl->chip_id == STLINK_CHIPID_STM32_L0_CAT5 || in stlink_flashloader_stop()
3460 sl->chip_id == STLINK_CHIPID_STM32_L0_CAT2 || in stlink_flashloader_stop()
3461 sl->chip_id == STLINK_CHIPID_STM32_L011) { in stlink_flashloader_stop()
3467 stlink_read_debug32(sl, flash_regs_base + FLASH_PECR_OFF, &val); in stlink_flashloader_stop()
3469 stlink_write_debug32(sl, flash_regs_base + FLASH_PECR_OFF, val); in stlink_flashloader_stop()
3473 if (!stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr)) { in stlink_flashloader_stop()
3474 stlink_write_debug32(sl, STLINK_REG_DHCSR, in stlink_flashloader_stop()
3480 set_dma_state(sl, fl, 1); in stlink_flashloader_stop()
3485 int stlink_write_flash(stlink_t *sl, stm32_addr_t addr, uint8_t *base, in stlink_write_flash() argument
3493 stlink_calculate_pagesize(sl, addr); in stlink_write_flash()
3495 if (addr < sl->flash_base) { in stlink_write_flash()
3496 ELOG("addr too low %#x < %#x\n", addr, sl->flash_base); in stlink_write_flash()
3501 } else if ((addr + len) > (sl->flash_base + sl->flash_size)) { in stlink_write_flash()
3510 } else if (addr & (sl->flash_pgsz - 1)) { in stlink_write_flash()
3514 (unsigned)(sl->flash_pgsz)); in stlink_write_flash()
3519 stlink_core_id(sl); in stlink_write_flash()
3525 off += stlink_calculate_pagesize(sl, addr + (uint32_t)off)) { in stlink_write_flash()
3527 if (stlink_erase_flash_page(sl, addr + (uint32_t)off) == -1) { in stlink_write_flash()
3537 (unsigned)(sl->flash_pgsz), (unsigned)(sl->flash_pgsz)); in stlink_write_flash()
3543 ret = stlink_flashloader_start(sl, &fl); in stlink_write_flash()
3546 ret = stlink_flashloader_write(sl, &fl, addr, base, len); in stlink_write_flash()
3549 ret = stlink_flashloader_stop(sl, &fl); in stlink_write_flash()
3553 return (stlink_verify_write_flash(sl, addr, base, len)); in stlink_write_flash()
3738 uint8_t stlink_get_erased_pattern(stlink_t *sl) { in stlink_get_erased_pattern() argument
3739 if (sl->flash_type == STLINK_FLASH_TYPE_L0) { in stlink_get_erased_pattern()
3746 int stlink_mwrite_flash(stlink_t *sl, uint8_t *data, uint32_t length, in stlink_mwrite_flash() argument
3751 uint8_t erased_pattern = stlink_get_erased_pattern(sl); in stlink_mwrite_flash()
3757 if (sl->opt) { in stlink_mwrite_flash()
3780 err = stlink_write_flash(sl, addr, data, in stlink_mwrite_flash()
3784 stlink_fwrite_finalize(sl, addr); in stlink_mwrite_flash()
3795 int stlink_fwrite_flash(stlink_t *sl, const char *path, stm32_addr_t addr) { in stlink_fwrite_flash() argument
3799 uint8_t erased_pattern = stlink_get_erased_pattern(sl); in stlink_fwrite_flash()
3811 if (sl->opt) { in stlink_fwrite_flash()
3835 err = stlink_write_flash(sl, addr, mf.base, in stlink_fwrite_flash()
3839 stlink_fwrite_finalize(sl, addr); in stlink_fwrite_flash()
3851 static int stlink_write_option_bytes_gx(stlink_t *sl, uint8_t *base, in stlink_write_option_bytes_gx() argument
3859 clear_flash_error(sl); in stlink_write_option_bytes_gx()
3863 stlink_write_debug32(sl, STM32Gx_FLASH_OPTR, data); in stlink_write_option_bytes_gx()
3866 stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); in stlink_write_option_bytes_gx()
3868 stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); in stlink_write_option_bytes_gx()
3870 wait_flash_busy(sl); in stlink_write_option_bytes_gx()
3872 ret = check_flash_error(sl); in stlink_write_option_bytes_gx()
3875 stlink_read_debug32(sl, STM32Gx_FLASH_CR, &val); in stlink_write_option_bytes_gx()
3877 stlink_write_debug32(sl, STM32Gx_FLASH_CR, val); in stlink_write_option_bytes_gx()
3889 static int stlink_write_option_bytes_l0(stlink_t *sl, uint8_t *base, in stlink_write_option_bytes_l0() argument
3891 uint32_t flash_base = get_stm32l0_flash_base(sl); in stlink_write_option_bytes_l0()
3897 clear_flash_error(sl); in stlink_write_option_bytes_l0()
3904 stlink_write_debug32(sl, addr, data); in stlink_write_option_bytes_l0()
3905 wait_flash_busy(sl); in stlink_write_option_bytes_l0()
3907 if ((ret = check_flash_error(sl))) { in stlink_write_option_bytes_l0()
3917 stlink_read_debug32(sl, flash_base + FLASH_PECR_OFF, &val); in stlink_write_option_bytes_l0()
3919 stlink_write_debug32(sl, flash_base + FLASH_PECR_OFF, val); in stlink_write_option_bytes_l0()
3931 static int stlink_write_option_bytes_l4(stlink_t *sl, uint8_t *base, in stlink_write_option_bytes_l4() argument
3940 clear_flash_error(sl); in stlink_write_option_bytes_l4()
3946 stlink_write_debug32(sl, STM32L4_FLASH_OPTR, data); in stlink_write_option_bytes_l4()
3949 stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); in stlink_write_option_bytes_l4()
3951 stlink_write_debug32(sl, STM32L4_FLASH_CR, val); in stlink_write_option_bytes_l4()
3953 wait_flash_busy(sl); in stlink_write_option_bytes_l4()
3954 ret = check_flash_error(sl); in stlink_write_option_bytes_l4()
3957 stlink_read_debug32(sl, STM32L4_FLASH_CR, &val); in stlink_write_option_bytes_l4()
3959 stlink_write_debug32(sl, STM32L4_FLASH_CR, val); in stlink_write_option_bytes_l4()
3970 static int stlink_write_option_bytes_f4(stlink_t *sl, uint8_t *base, in stlink_write_option_bytes_f4() argument
3978 clear_flash_error(sl); in stlink_write_option_bytes_f4()
3983 stlink_write_debug32(sl, FLASH_F4_OPTCR, in stlink_write_option_bytes_f4()
3987 wait_flash_busy(sl); in stlink_write_option_bytes_f4()
3988 ret = check_flash_error(sl); in stlink_write_option_bytes_f4()
4000 static int stlink_write_option_bytes_f7(stlink_t *sl, uint8_t *base, in stlink_write_option_bytes_f7() argument
4006 clear_flash_error(sl); in stlink_write_option_bytes_f7()
4020 stlink_write_debug32(sl, FLASH_F7_OPTCR, in stlink_write_option_bytes_f7()
4026 stlink_read_debug32(sl, FLASH_F7_OPTCR, &oldvalue); in stlink_write_option_bytes_f7()
4028 stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_byte); in stlink_write_option_bytes_f7()
4030 stlink_write_debug32(sl, FLASH_F7_OPTCR, in stlink_write_option_bytes_f7()
4035 stlink_write_debug32(sl, addr, option_byte); in stlink_write_option_bytes_f7()
4038 wait_flash_busy(sl); in stlink_write_option_bytes_f7()
4040 ret = check_flash_error(sl); in stlink_write_option_bytes_f7()
4058 static int stlink_write_option_bytes_h7(stlink_t *sl, uint8_t *base, in stlink_write_option_bytes_h7() argument
4064 wait_flash_busy(sl); in stlink_write_option_bytes_h7()
4067 stlink_write_debug32(sl, FLASH_H7_OPTCCR, in stlink_write_option_bytes_h7()
4084 stlink_read_debug32(sl, addr - 4, &val); in stlink_write_option_bytes_h7()
4090 stlink_write_debug32(sl, addr, data); in stlink_write_option_bytes_h7()
4091 stlink_read_debug32(sl, FLASH_H7_OPTCR, &val); in stlink_write_option_bytes_h7()
4093 stlink_write_debug32(sl, FLASH_H7_OPTCR, val); in stlink_write_option_bytes_h7()
4097 stlink_read_debug32(sl, FLASH_H7_OPTSR_CUR, &val); in stlink_write_option_bytes_h7()
4102 stlink_write_debug32(sl, FLASH_H7_OPTCCR, in stlink_write_option_bytes_h7()
4127 int stlink_read_option_control_register_Gx(stlink_t *sl, in stlink_read_option_control_register_Gx() argument
4129 return stlink_read_debug32(sl, STM32Gx_FLASH_OPTR, option_byte); in stlink_read_option_control_register_Gx()
4138 int stlink_read_option_bytes_Gx(stlink_t *sl, uint32_t *option_byte) { in stlink_read_option_bytes_Gx() argument
4139 return stlink_read_option_control_register_Gx(sl, option_byte); in stlink_read_option_bytes_Gx()
4148 int stlink_read_option_control_register_f2(stlink_t *sl, in stlink_read_option_control_register_f2() argument
4150 return stlink_read_debug32(sl, FLASH_F2_OPT_CR, option_byte); in stlink_read_option_control_register_f2()
4159 int stlink_read_option_bytes_f2(stlink_t *sl, uint32_t *option_byte) { in stlink_read_option_bytes_f2() argument
4160 return stlink_read_option_control_register_f2(sl, option_byte); in stlink_read_option_bytes_f2()
4169 int stlink_read_option_control_register_f4(stlink_t *sl, in stlink_read_option_control_register_f4() argument
4171 return stlink_read_debug32(sl, FLASH_F4_OPTCR, option_byte); in stlink_read_option_control_register_f4()
4180 int stlink_read_option_bytes_f4(stlink_t *sl, uint32_t *option_byte) { in stlink_read_option_bytes_f4() argument
4181 return stlink_read_option_control_register_f4(sl, option_byte); in stlink_read_option_bytes_f4()
4190 int stlink_read_option_control_register_f7(stlink_t *sl, in stlink_read_option_control_register_f7() argument
4193 return stlink_read_debug32(sl, FLASH_F7_OPTCR, option_byte); in stlink_read_option_control_register_f7()
4202 int stlink_read_option_control_register1_f7(stlink_t *sl, in stlink_read_option_control_register1_f7() argument
4206 return stlink_read_debug32(sl, FLASH_F7_OPTCR1, option_byte); in stlink_read_option_control_register1_f7()
4215 int stlink_read_option_bytes_boot_add_f7(stlink_t *sl, uint32_t *option_byte) { in stlink_read_option_bytes_boot_add_f7() argument
4217 return stlink_read_option_control_register1_f7(sl, option_byte); in stlink_read_option_bytes_boot_add_f7()
4229 int stlink_read_option_bytes_f7(stlink_t *sl, uint32_t *option_byte) { in stlink_read_option_bytes_f7() argument
4231 for (uint32_t counter = 0; counter < (sl->option_size / 4 - 1); counter++) { in stlink_read_option_bytes_f7()
4232 err = stlink_read_debug32(sl, sl->option_base + counter * sizeof(uint32_t), in stlink_read_option_bytes_f7()
4242 sl, in stlink_read_option_bytes_f7()
4243 sl->option_base + (uint32_t)(sl->option_size / 4 - 1) * sizeof(uint32_t), in stlink_read_option_bytes_f7()
4253 int stlink_read_option_bytes_generic(stlink_t *sl, uint32_t *option_byte) { in stlink_read_option_bytes_generic() argument
4254 DLOG("@@@@ Read option bytes boot address from %#10x\n", sl->option_base); in stlink_read_option_bytes_generic()
4255 return stlink_read_debug32(sl, sl->option_base, option_byte); in stlink_read_option_bytes_generic()
4302 int stlink_read_option_bytes32(stlink_t *sl, uint32_t *option_byte) { in stlink_read_option_bytes32() argument
4303 if (sl->option_base == 0) { in stlink_read_option_bytes32()
4308 switch (sl->chip_id) { in stlink_read_option_bytes32()
4310 return stlink_read_option_bytes_f2(sl, option_byte); in stlink_read_option_bytes32()
4313 return stlink_read_option_bytes_f4(sl, option_byte); in stlink_read_option_bytes32()
4315 return stlink_read_option_bytes_f7(sl, option_byte); in stlink_read_option_bytes32()
4320 return stlink_read_option_bytes_Gx(sl, option_byte); in stlink_read_option_bytes32()
4322 return stlink_read_option_bytes_generic(sl, option_byte); in stlink_read_option_bytes32()
4332 int stlink_read_option_bytes_boot_add32(stlink_t *sl, uint32_t *option_byte) { in stlink_read_option_bytes_boot_add32() argument
4333 if (sl->option_base == 0) { in stlink_read_option_bytes_boot_add32()
4339 switch (sl->chip_id) { in stlink_read_option_bytes_boot_add32()
4341 return stlink_read_option_bytes_boot_add_f7(sl, option_byte); in stlink_read_option_bytes_boot_add32()
4354 int stlink_read_option_control_register32(stlink_t *sl, uint32_t *option_byte) { in stlink_read_option_control_register32() argument
4355 if (sl->option_base == 0) { in stlink_read_option_control_register32()
4360 switch (sl->chip_id) { in stlink_read_option_control_register32()
4362 return stlink_read_option_control_register_f7(sl, option_byte); in stlink_read_option_control_register32()
4375 int stlink_read_option_control_register1_32(stlink_t *sl, in stlink_read_option_control_register1_32() argument
4377 if (sl->option_base == 0) { in stlink_read_option_control_register1_32()
4382 switch (sl->chip_id) { in stlink_read_option_control_register1_32()
4384 return stlink_read_option_control_register1_f7(sl, option_byte); in stlink_read_option_control_register1_32()
4397 int stlink_write_option_bytes32(stlink_t *sl, uint32_t option_byte) { in stlink_write_option_bytes32() argument
4399 sl->option_base); in stlink_write_option_bytes32()
4400 return stlink_write_option_bytes(sl, sl->option_base, (uint8_t *)&option_byte, in stlink_write_option_bytes32()
4411 int stlink_write_option_bytes(stlink_t *sl, stm32_addr_t addr, uint8_t *base, in stlink_write_option_bytes() argument
4415 if (sl->option_base == 0) { in stlink_write_option_bytes()
4421 if ((addr < sl->option_base) || addr > sl->option_base + sl->option_size) { in stlink_write_option_bytes()
4426 if (addr + len > sl->option_base + sl->option_size) { in stlink_write_option_bytes()
4431 wait_flash_busy(sl); in stlink_write_option_bytes()
4433 if (unlock_flash_if(sl)) { in stlink_write_option_bytes()
4439 if (unlock_flash_option_if(sl)) { in stlink_write_option_bytes()
4444 switch (sl->flash_type) { in stlink_write_option_bytes()
4446 ret = stlink_write_option_bytes_f4(sl, base, addr, len); in stlink_write_option_bytes()
4449 ret = stlink_write_option_bytes_f7(sl, base, addr, len); in stlink_write_option_bytes()
4452 ret = stlink_write_option_bytes_l0(sl, base, addr, len); in stlink_write_option_bytes()
4455 ret = stlink_write_option_bytes_l4(sl, base, addr, len); in stlink_write_option_bytes()
4459 ret = stlink_write_option_bytes_gx(sl, base, addr, len); in stlink_write_option_bytes()
4462 ret = stlink_write_option_bytes_h7(sl, base, addr, len); in stlink_write_option_bytes()
4477 lock_flash_option(sl); in stlink_write_option_bytes()
4478 lock_flash(sl); in stlink_write_option_bytes()
4490 stlink_write_option_control_register_f7(stlink_t *sl, in stlink_write_option_control_register_f7() argument
4495 clear_flash_error(sl); in stlink_write_option_control_register_f7()
4501 stlink_write_debug32(sl, FLASH_F7_OPTCR, in stlink_write_option_control_register_f7()
4505 wait_flash_busy(sl); in stlink_write_option_control_register_f7()
4507 ret = check_flash_error(sl); in stlink_write_option_control_register_f7()
4522 stlink_write_option_control_register1_f7(stlink_t *sl, in stlink_write_option_control_register1_f7() argument
4527 clear_flash_error(sl); in stlink_write_option_control_register1_f7()
4534 stlink_read_debug32(sl, FLASH_F7_OPTCR, ¤t_control_register_value); in stlink_write_option_control_register1_f7()
4537 stlink_write_debug32(sl, FLASH_F7_OPTCR1, option_control_register1); in stlink_write_option_control_register1_f7()
4539 sl, FLASH_F7_OPTCR, in stlink_write_option_control_register1_f7()
4543 wait_flash_busy(sl); in stlink_write_option_control_register1_f7()
4545 ret = check_flash_error(sl); in stlink_write_option_control_register1_f7()
4560 stlink_write_option_bytes_boot_add_f7(stlink_t *sl, in stlink_write_option_bytes_boot_add_f7() argument
4563 return stlink_write_option_control_register1_f7(sl, option_byte_boot_add); in stlink_write_option_bytes_boot_add_f7()
4572 int stlink_write_option_bytes_boot_add32(stlink_t *sl, in stlink_write_option_bytes_boot_add32() argument
4576 wait_flash_busy(sl); in stlink_write_option_bytes_boot_add32()
4578 if (unlock_flash_if(sl)) { in stlink_write_option_bytes_boot_add32()
4584 if (unlock_flash_option_if(sl)) { in stlink_write_option_bytes_boot_add32()
4589 switch (sl->flash_type) { in stlink_write_option_bytes_boot_add32()
4591 ret = stlink_write_option_bytes_boot_add_f7(sl, option_bytes_boot_add); in stlink_write_option_bytes_boot_add32()
4605 lock_flash_option(sl); in stlink_write_option_bytes_boot_add32()
4606 lock_flash(sl); in stlink_write_option_bytes_boot_add32()
4617 int stlink_write_option_control_register32(stlink_t *sl, in stlink_write_option_control_register32() argument
4621 wait_flash_busy(sl); in stlink_write_option_control_register32()
4623 if (unlock_flash_if(sl)) { in stlink_write_option_control_register32()
4629 if (unlock_flash_option_if(sl)) { in stlink_write_option_control_register32()
4634 switch (sl->flash_type) { in stlink_write_option_control_register32()
4636 ret = stlink_write_option_control_register_f7(sl, option_control_register); in stlink_write_option_control_register32()
4650 lock_flash_option(sl); in stlink_write_option_control_register32()
4651 lock_flash(sl); in stlink_write_option_control_register32()
4663 stlink_t *sl, uint32_t option_control_register1) { in stlink_write_option_control_register1_32() argument
4666 wait_flash_busy(sl); in stlink_write_option_control_register1_32()
4668 if (unlock_flash_if(sl)) { in stlink_write_option_control_register1_32()
4674 if (unlock_flash_option_if(sl)) { in stlink_write_option_control_register1_32()
4679 switch (sl->flash_type) { in stlink_write_option_control_register1_32()
4682 stlink_write_option_control_register1_f7(sl, option_control_register1); in stlink_write_option_control_register1_32()
4695 lock_flash_option(sl); in stlink_write_option_control_register1_32()
4696 lock_flash(sl); in stlink_write_option_control_register1_32()
4708 int stlink_fwrite_option_bytes(stlink_t *sl, const char *path, in stlink_fwrite_option_bytes() argument
4723 err = stlink_write_option_bytes(sl, addr, mf.base, (uint32_t)mf.len); in stlink_fwrite_option_bytes()
4724 stlink_fwrite_finalize(sl, addr); in stlink_fwrite_option_bytes()
4730 int stlink_target_connect(stlink_t *sl, enum connect_type connect) { in stlink_target_connect() argument
4734 stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_LOW); in stlink_target_connect()
4739 if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { in stlink_target_connect()
4740 stlink_enter_swd_mode(sl); in stlink_target_connect()
4742 stlink_force_debug(sl); in stlink_target_connect()
4745 stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); in stlink_target_connect()
4747 stlink_jtag_reset(sl, STLINK_JTAG_DRIVE_NRST_HIGH); in stlink_target_connect()
4752 stlink_read_debug32(sl, STLINK_REG_DHCSR, &dhcsr); in stlink_target_connect()
4758 stlink_soft_reset(sl, 1 /* halt on reset */); in stlink_target_connect()
4761 if (stlink_current_mode(sl) != STLINK_DEV_DEBUG_MODE) { in stlink_target_connect()
4762 stlink_enter_swd_mode(sl); in stlink_target_connect()
4766 stlink_reset(sl, RESET_AUTO); in stlink_target_connect()
4769 return stlink_load_device_params(sl); in stlink_target_connect()