Lines Matching refs:NewR

209     static bool replaceReg(Register OldR, Register NewR,
213 static bool replaceRegWithSub(Register OldR, Register NewR, unsigned NewSR,
215 static bool replaceSubWithSub(Register OldR, unsigned OldSR, Register NewR,
355 bool HexagonBitSimplify::replaceReg(Register OldR, Register NewR, in replaceReg() argument
357 if (!OldR.isVirtual() || !NewR.isVirtual()) in replaceReg()
363 I->setReg(NewR); in replaceReg()
368 bool HexagonBitSimplify::replaceRegWithSub(Register OldR, Register NewR, in replaceRegWithSub() argument
371 if (!OldR.isVirtual() || !NewR.isVirtual()) in replaceRegWithSub()
379 I->setReg(NewR); in replaceRegWithSub()
386 Register NewR, unsigned NewSR, in replaceSubWithSub() argument
388 if (!OldR.isVirtual() || !NewR.isVirtual()) in replaceSubWithSub()
398 I->setReg(NewR); in replaceSubWithSub()
1347 Register NewR = MRI.createVirtualRegister(FRC); in processBlock() local
1349 BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR) in processBlock()
1351 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in processBlock()
1620 Register NewR = MRI.createVirtualRegister(FRC); in processBlock() local
1621 BuildMI(B, At, DL, HII.get(TargetOpcode::COPY), NewR) in processBlock()
1623 BT.put(BitTracker::RegisterRef(NewR), BT.get(MR)); in processBlock()
1624 HBS::replaceReg(R, NewR, MRI); in processBlock()
1639 Register NewR = MRI.createVirtualRegister(FRC); in processBlock() local
1640 BuildMI(B, At, DL, HII.get(TargetOpcode::REG_SEQUENCE), NewR) in processBlock()
1645 BT.put(BitTracker::RegisterRef(NewR), BT.get(R)); in processBlock()
1646 HBS::replaceReg(R, NewR, MRI); in processBlock()
2036 Register NewR = MRI.createVirtualRegister(&Hexagon::DoubleRegsRegClass); in genPackhl() local
2040 BuildMI(B, At, DL, HII.get(Hexagon::S2_packhl), NewR) in genPackhl()
2043 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in genPackhl()
2044 BT.put(BitTracker::RegisterRef(NewR), RC); in genPackhl()
2063 unsigned NewR = 0; in genExtractHalf() local
2068 NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in genExtractHalf()
2069 BuildMI(B, At, DL, HII.get(Hexagon::A2_zxth), NewR) in genExtractHalf()
2074 NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in genExtractHalf()
2075 BuildMI(B, MI, DL, HII.get(Hexagon::S2_lsr_i_r), NewR) in genExtractHalf()
2080 if (NewR == 0) in genExtractHalf()
2082 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in genExtractHalf()
2083 BT.put(BitTracker::RegisterRef(NewR), RC); in genExtractHalf()
2108 Register NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in genCombineHalf() local
2111 BuildMI(B, At, DL, HII.get(COpc), NewR) in genCombineHalf()
2114 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in genCombineHalf()
2115 BT.put(BitTracker::RegisterRef(NewR), RC); in genCombineHalf()
2165 Register NewR = MRI.createVirtualRegister(&Hexagon::IntRegsRegClass); in genExtractLow() local
2168 auto MIB = BuildMI(B, At, DL, HII.get(NewOpc), NewR) in genExtractLow()
2174 HBS::replaceSubWithSub(RD.Reg, RD.Sub, NewR, 0, MRI); in genExtractLow()
2175 BT.put(BitTracker::RegisterRef(NewR), RC); in genExtractLow()
2287 unsigned NewR = 0; in genBitSplit() local
2305 NewR = Op0.getReg(); in genBitSplit()
2308 if (!NewR) { in genBitSplit()
2309 NewR = MRI.createVirtualRegister(&Hexagon::DoubleRegsRegClass); in genBitSplit()
2310 auto NewBS = BuildMI(B, At, DL, HII.get(Hexagon::A4_bitspliti), NewR) in genBitSplit()
2316 HBS::replaceRegWithSub(RD.Reg, NewR, Hexagon::isub_lo, MRI); in genBitSplit()
2317 HBS::replaceRegWithSub(S, NewR, Hexagon::isub_hi, MRI); in genBitSplit()
2319 HBS::replaceRegWithSub(S, NewR, Hexagon::isub_lo, MRI); in genBitSplit()
2320 HBS::replaceRegWithSub(RD.Reg, NewR, Hexagon::isub_hi, MRI); in genBitSplit()
2370 Register NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass); in simplifyTstbit() local
2371 BuildMI(B, At, DL, HII.get(Hexagon::S2_tstbit_i), NewR) in simplifyTstbit()
2374 HBS::replaceReg(RD.Reg, NewR, MRI); in simplifyTstbit()
2375 BT.put(NewR, RC); in simplifyTstbit()
2379 Register NewR = MRI.createVirtualRegister(&Hexagon::PredRegsRegClass); in simplifyTstbit() local
2381 BuildMI(B, At, DL, HII.get(NewOpc), NewR); in simplifyTstbit()
2382 HBS::replaceReg(RD.Reg, NewR, MRI); in simplifyTstbit()
2552 Register NewR = MRI.createVirtualRegister(FRC); in simplifyExtractLow() local
2555 auto MIB = BuildMI(B, At, DL, HII.get(ExtOpc), NewR) in simplifyExtractLow()
2577 HBS::replaceReg(RD.Reg, NewR, MRI); in simplifyExtractLow()
2578 BT.put(BitTracker::RegisterRef(NewR), RC); in simplifyExtractLow()
2624 Register NewR = MRI.createVirtualRegister(FRC); in simplifyRCmp0() local
2625 BuildMI(B, At, DL, HII.get(Hexagon::A2_tfrsi), NewR) in simplifyRCmp0()
2627 HBS::replaceReg(RD.Reg, NewR, MRI); in simplifyRCmp0()
2633 BT.put(BitTracker::RegisterRef(NewR), NewRC); in simplifyRCmp0()
2689 Register NewR = MRI.createVirtualRegister(FRC); in simplifyRCmp0() local
2690 BuildMI(B, At, DL, HII.get(Hexagon::C2_muxii), NewR) in simplifyRCmp0()
2694 HBS::replaceReg(RD.Reg, NewR, MRI); in simplifyRCmp0()
2699 BT.put(BitTracker::RegisterRef(NewR), NewRC); in simplifyRCmp0()