Target/AArch64/AArch64ISelLowering.cpp

3104     SDValue TVal = DAG.getConstant(1, dl, MVT::i32);  in LowerXOR()  local
3110     return DAG.getNode(AArch64ISD::CSEL, dl, Op.getValueType(), TVal, FVal,  in LowerXOR()
3129   SDValue TVal = Sel.getOperand(2);  in LowerXOR()  local
3137   ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);  in LowerXOR()
3146     std::swap(TVal, FVal);  in LowerXOR()
3157     TVal = DAG.getNode(ISD::XOR, dl, Other.getValueType(), Other,  in LowerXOR()
3160     return DAG.getNode(AArch64ISD::CSEL, dl, Sel.getValueType(), FVal, TVal,  in LowerXOR()
3215   SDValue TVal = DAG.getConstant(1, dl, MVT::i32);  in LowerXALUO()  local
3222   Overflow = DAG.getNode(AArch64ISD::CSEL, dl, MVT::i32, FVal, TVal,  in LowerXALUO()
7213   SDValue TVal = DAG.getConstant(1, dl, VT);  in LowerSETCC()  local
7238     SDValue Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CCVal, Cmp);  in LowerSETCC()
7265     Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, FVal, TVal, CC1Val, Cmp);  in LowerSETCC()
7275         DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);  in LowerSETCC()
7278     Res = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);  in LowerSETCC()
7284                                               SDValue RHS, SDValue TVal,  in LowerSELECT_CC()  argument
7312     ConstantSDNode *CTVal = dyn_cast<ConstantSDNode>(TVal);  in LowerSELECT_CC()
7319         LHS.getValueType() == TVal.getValueType()) {  in LowerSELECT_CC()
7332       std::swap(TVal, FVal);  in LowerSELECT_CC()
7336       std::swap(TVal, FVal);  in LowerSELECT_CC()
7339     } else if (TVal.getOpcode() == ISD::XOR) {  in LowerSELECT_CC()
7342       if (isAllOnesConstant(TVal.getOperand(1))) {  in LowerSELECT_CC()
7343         std::swap(TVal, FVal);  in LowerSELECT_CC()
7347     } else if (TVal.getOpcode() == ISD::SUB) {  in LowerSELECT_CC()
7350       if (isNullConstant(TVal.getOperand(0))) {  in LowerSELECT_CC()
7351         std::swap(TVal, FVal);  in LowerSELECT_CC()
7368       } else if (TVal.getValueType() == MVT::i32) {  in LowerSELECT_CC()
7395         std::swap(TVal, FVal);  in LowerSELECT_CC()
7403         FVal = TVal;  in LowerSELECT_CC()
7419         TVal = LHS;  in LowerSELECT_CC()
7429         TVal = LHS;  in LowerSELECT_CC()
7436     EVT VT = TVal.getValueType();  in LowerSELECT_CC()
7437     return DAG.getNode(Opcode, dl, VT, TVal, FVal, CCVal, Cmp);  in LowerSELECT_CC()
7444   EVT VT = TVal.getValueType();  in LowerSELECT_CC()
7458       ConstantFPSDNode *CTVal = dyn_cast<ConstantFPSDNode>(TVal);  in LowerSELECT_CC()
7461           CTVal && CTVal->isZero() && TVal.getValueType() == LHS.getValueType())  in LowerSELECT_CC()
7462         TVal = LHS;  in LowerSELECT_CC()
7472   SDValue CS1 = DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, FVal, CC1Val, Cmp);  in LowerSELECT_CC()
7478     return DAG.getNode(AArch64ISD::CSEL, dl, VT, TVal, CS1, CC2Val, Cmp);  in LowerSELECT_CC()
7500   SDValue TVal = Op.getOperand(2);  in LowerSELECT_CC()  local
7503   return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);  in LowerSELECT_CC()
7509   SDValue TVal = Op->getOperand(1);  in LowerSELECT()  local
7518     return DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal);  in LowerSELECT()
7529     return DAG.getNode(ISD::VSELECT, DL, Ty, SplatPred, TVal, FVal);  in LowerSELECT()
7544     return DAG.getNode(AArch64ISD::CSEL, DL, Op.getValueType(), TVal, FVal,  in LowerSELECT()
7560   return LowerSELECT_CC(CC, LHS, RHS, TVal, FVal, DL, DAG);  in LowerSELECT()
14214   SDValue TVal = DAG.getConstant(1, DL, OutVT);  in getPTest()  local
14223   SDValue Res = DAG.getNode(AArch64ISD::CSEL, DL, OutVT, FVal, TVal, CC, Test);  in getPTest()