71 	Uint32 i_misses;  /* how many CPU i-cache misses happened at this address */  member
229 		 item->i_hits, item->i_misses,  in Profile_CpuAddressDataStr()
234 		 item->i_misses, item->d_hits);  in Profile_CpuAddressDataStr()
258 	if (cpu_profile.all.i_misses) {  in show_cpu_area_stats()
260 			area->counters.i_misses,  in show_cpu_area_stats()
261 			100.0 * area->counters.i_misses / cpu_profile.all.i_misses);  in show_cpu_area_stats()
330 	if (!(cpu_profile.all.i_misses || cpu_profile.all.d_hits)) {  in Profile_CpuShowCaches()
459 	Uint32 count1 = cpu_profile.data[*(const Uint32*)p1].i_misses;  in cmp_cpu_i_misses()
460 	Uint32 count2 = cpu_profile.data[*(const Uint32*)p2].i_misses;  in cmp_cpu_i_misses()
482 	if (!cpu_profile.all.i_misses) {  in Profile_CpuShowInstrMisses()
497 		count = data[*sort_arr].i_misses;  in Profile_CpuShowInstrMisses()
498 		percentage = 100.0*count/cpu_profile.all.i_misses;  in Profile_CpuShowInstrMisses()
1027 	Uint32 i_hits, d_hits, i_misses, d_misses;  in Profile_CpuUpdate()  local
1029 	const Uint32 i_misses = 0, d_hits = 0;  in Profile_CpuUpdate()  local
1079 	i_misses = CpuInstruction.I_Cache_miss;  in Profile_CpuUpdate()
1101 	if (likely(prev->i_misses < MAX_CPU_PROFILE_VALUE - i_misses)) {  in Profile_CpuUpdate()
1102 		prev->i_misses += i_misses;  in Profile_CpuUpdate()
1104 		prev->i_misses = MAX_CPU_PROFILE_VALUE;  in Profile_CpuUpdate()
1113 	if (!(i_hits || i_misses)) {  in Profile_CpuUpdate()
1121 	if (unlikely(i_misses >= MAX_I_MISSES)) {  in Profile_CpuUpdate()
1122 …i_misses = warn_too_large("number of CPU instruction cache misses", i_misses, MAX_I_MISSES, prev_p…  in Profile_CpuUpdate()
1124 	cpu_profile.i_miss_counts[i_misses]++;  in Profile_CpuUpdate()
1146 	counters->i_misses += i_misses;  in Profile_CpuUpdate()
1189 	area->counters.i_misses += item->i_misses;  in update_area_item()
1294 …i_misses == cpu_profile.ttram.counters.i_misses + cpu_profile.ram.counters.i_misses + cpu_profile.…  in Profile_CpuStop()