Lines Matching defs:dst
14 OP80( 0x07, i_rlc ) { uint32_t dst = Breg(AL); ROL_BYTE; Breg(AL) = dst; CLK(1); } variable
15 OP80( 0x09, i_dadb ) { uint32_t dst = Wreg(BW) + Wreg(CW); SetCFW(dst); Wreg(BW) = dst; CLK(1); } variable
21 OP80( 0x0f, i_rrc ) { uint32_t dst = Breg(AL); ROR_BYTE; Breg(AL) = dst; CLK(1); } variable
28 OP80( 0x17, i_ral ) { uint32_t dst = Breg(AL); ROLC_BYTE; Breg(AL) = dst; CLK(1); } variable
29 OP80( 0x19, i_dadd ) { uint32_t dst = Wreg(BW) + Wreg(DW); SetCFW(dst); Wreg(BW) = dst; CLK(1); } variable
35 OP80( 0x1f, i_rar ) { uint32_t dst = Breg(AL); RORC_BYTE; Breg(AL) = dst; CLK(1); } variable
43 OP80( 0x29, i_dadh ) { uint32_t dst = Wreg(BW) + Wreg(BW); SetCFW(dst); Wreg(BW) = dst; CLK(1); } variable
57 OP80( 0x39, i_dads ) { uint32_t dst = Wreg(BW) + Wreg(BP); SetCFW(dst); Wreg(BW) = dst; CLK(1); } variable
128 OP80( 0x80, i_addb ) { uint32_t src = Breg(CH), dst = Breg(AL); ADDB; Breg(AL) = dst; CLK(1); } variable
129 OP80( 0x81, i_addc ) { uint32_t src = Breg(CL), dst = Breg(AL); ADDB; Breg(AL) = dst; CLK(1); } variable
130 OP80( 0x82, i_addd ) { uint32_t src = Breg(DH), dst = Breg(AL); ADDB; Breg(AL) = dst; CLK(1); } variable
131 OP80( 0x83, i_adde ) { uint32_t src = Breg(DL), dst = Breg(AL); ADDB; Breg(AL) = dst; CLK(1); } variable
132 OP80( 0x84, i_addh ) { uint32_t src = Breg(BH), dst = Breg(AL); ADDB; Breg(AL) = dst; CLK(1); } variable
133 OP80( 0x85, i_addl ) { uint32_t src = Breg(BL), dst = Breg(AL); ADDB; Breg(AL) = dst; CLK(1); } variable
134 OP80( 0x86, i_addm ) { uint32_t src = GetMemB(DS0, Wreg(BW)), dst = Breg(AL); ADDB; Breg(AL) = dst… variable
135 OP80( 0x87, i_adda ) { uint32_t src = Breg(AL), dst = Breg(AL); ADDB; Breg(AL) = dst; CLK(1); } variable
136 OP80( 0x88, i_adcb ) { uint32_t src = Breg(CH), dst = Breg(AL); src+=CF; ADDB; Breg(AL) = dst; CLK… variable
137 OP80( 0x89, i_adcc ) { uint32_t src = Breg(CL), dst = Breg(AL); src+=CF; ADDB; Breg(AL) = dst; CLK… variable
138 OP80( 0x8a, i_adcd ) { uint32_t src = Breg(DH), dst = Breg(AL); src+=CF; ADDB; Breg(AL) = dst; CLK… variable
139 OP80( 0x8b, i_adce ) { uint32_t src = Breg(DL), dst = Breg(AL); src+=CF; ADDB; Breg(AL) = dst; CLK… variable
140 OP80( 0x8c, i_adch ) { uint32_t src = Breg(BH), dst = Breg(AL); src+=CF; ADDB; Breg(AL) = dst; CLK… variable
141 OP80( 0x8d, i_adcl ) { uint32_t src = Breg(BL), dst = Breg(AL); src+=CF; ADDB; Breg(AL) = dst; CLK… variable
142 OP80( 0x8e, i_adcm ) { uint32_t src = GetMemB(DS0, Wreg(BW)), dst = Breg(AL); src+=CF; ADDB; Breg(… variable
143 OP80( 0x8f, i_adca ) { uint32_t src = Breg(AL), dst = Breg(AL); src+=CF; ADDB; Breg(AL) = dst; CLK… variable
144 OP80( 0x90, i_subb ) { uint32_t src = Breg(CH), dst = Breg(AL); SUBB; Breg(AL) = dst; CLK(1); } variable
145 OP80( 0x91, i_subc ) { uint32_t src = Breg(CL), dst = Breg(AL); SUBB; Breg(AL) = dst; CLK(1); } variable
146 OP80( 0x92, i_subd ) { uint32_t src = Breg(DH), dst = Breg(AL); SUBB; Breg(AL) = dst; CLK(1); } variable
147 OP80( 0x93, i_sube ) { uint32_t src = Breg(DL), dst = Breg(AL); SUBB; Breg(AL) = dst; CLK(1); } variable
148 OP80( 0x94, i_subh ) { uint32_t src = Breg(BH), dst = Breg(AL); SUBB; Breg(AL) = dst; CLK(1); } variable
149 OP80( 0x95, i_subl ) { uint32_t src = Breg(BL), dst = Breg(AL); SUBB; Breg(AL) = dst; CLK(1); } variable
150 OP80( 0x96, i_subm ) { uint32_t src = GetMemB(DS0, Wreg(BW)), dst = Breg(AL); SUBB; Breg(AL) = dst… variable
151 OP80( 0x97, i_suba ) { uint32_t src = Breg(AL), dst = Breg(AL); SUBB; Breg(AL) = dst; CLK(1); } variable
152 OP80( 0x98, i_sbbb ) { uint32_t src = Breg(CH), dst = Breg(AL); src+=CF; SUBB; Breg(AL) = dst; CLK… variable
153 OP80( 0x99, i_sbbc ) { uint32_t src = Breg(CL), dst = Breg(AL); src+=CF; SUBB; Breg(AL) = dst; CLK… variable
154 OP80( 0x9a, i_sbbd ) { uint32_t src = Breg(DH), dst = Breg(AL); src+=CF; SUBB; Breg(AL) = dst; CLK… variable
155 OP80( 0x9b, i_sbbe ) { uint32_t src = Breg(DL), dst = Breg(AL); src+=CF; SUBB; Breg(AL) = dst; CLK… variable
156 OP80( 0x9c, i_sbbh ) { uint32_t src = Breg(BH), dst = Breg(AL); src+=CF; SUBB; Breg(AL) = dst; CLK… variable
157 OP80( 0x9d, i_sbbl ) { uint32_t src = Breg(BL), dst = Breg(AL); src+=CF; SUBB; Breg(AL) = dst; CLK… variable
158 OP80( 0x9e, i_sbbm ) { uint32_t src = GetMemB(DS0, Wreg(BW)), dst = Breg(AL); src+=CF; SUBB; Breg(… variable
159 OP80( 0x9f, i_sbba ) { uint32_t src = Breg(AL), dst = Breg(AL); src+=CF; SUBB; Breg(AL) = dst; CLK… variable
160 OP80( 0xa0, i_anab ) { uint32_t src = Breg(CH), dst = Breg(AL); ANDB; Breg(AL) = dst; CLK(1); } variable
161 OP80( 0xa1, i_anac ) { uint32_t src = Breg(CL), dst = Breg(AL); ANDB; Breg(AL) = dst; CLK(1); } variable
162 OP80( 0xa2, i_anad ) { uint32_t src = Breg(DH), dst = Breg(AL); ANDB; Breg(AL) = dst; CLK(1); } variable
163 OP80( 0xa3, i_anae ) { uint32_t src = Breg(DL), dst = Breg(AL); ANDB; Breg(AL) = dst; CLK(1); } variable
164 OP80( 0xa4, i_anah ) { uint32_t src = Breg(BH), dst = Breg(AL); ANDB; Breg(AL) = dst; CLK(1); } variable
165 OP80( 0xa5, i_anal ) { uint32_t src = Breg(BL), dst = Breg(AL); ANDB; Breg(AL) = dst; CLK(1); } variable
166 OP80( 0xa6, i_anam ) { uint32_t src = GetMemB(DS0, Wreg(BW)), dst = Breg(AL); ANDB; Breg(AL) = dst… variable
167 OP80( 0xa7, i_anaa ) { uint32_t src = Breg(AL), dst = Breg(AL); ANDB; Breg(AL) = dst; CLK(1); } variable
168 OP80( 0xa8, i_xrab ) { uint32_t src = Breg(CH), dst = Breg(AL); XORB; Breg(AL) = dst; CLK(1); } variable
169 OP80( 0xa9, i_xrac ) { uint32_t src = Breg(CL), dst = Breg(AL); XORB; Breg(AL) = dst; CLK(1); } variable
170 OP80( 0xaa, i_xrad ) { uint32_t src = Breg(DH), dst = Breg(AL); XORB; Breg(AL) = dst; CLK(1); } variable
171 OP80( 0xab, i_xrae ) { uint32_t src = Breg(DL), dst = Breg(AL); XORB; Breg(AL) = dst; CLK(1); } variable
172 OP80( 0xac, i_xrah ) { uint32_t src = Breg(BH), dst = Breg(AL); XORB; Breg(AL) = dst; CLK(1); } variable
173 OP80( 0xad, i_xral ) { uint32_t src = Breg(BL), dst = Breg(AL); XORB; Breg(AL) = dst; CLK(1); } variable
174 OP80( 0xae, i_xram ) { uint32_t src = GetMemB(DS0, Wreg(BW)), dst = Breg(AL); XORB; Breg(AL) = dst… variable
175 OP80( 0xaf, i_xraa ) { uint32_t src = Breg(AL), dst = Breg(AL); XORB; Breg(AL) = dst; CLK(1); } variable
176 OP80( 0xb0, i_orab ) { uint32_t src = Breg(CH), dst = Breg(AL); ORB; Breg(AL) = dst; CLK(1); } variable
177 OP80( 0xb1, i_orac ) { uint32_t src = Breg(CL), dst = Breg(AL); ORB; Breg(AL) = dst; CLK(1); } variable
178 OP80( 0xb2, i_orad ) { uint32_t src = Breg(DH), dst = Breg(AL); ORB; Breg(AL) = dst; CLK(1); } variable
179 OP80( 0xb3, i_orae ) { uint32_t src = Breg(DL), dst = Breg(AL); ORB; Breg(AL) = dst; CLK(1); } variable
180 OP80( 0xb4, i_orah ) { uint32_t src = Breg(BH), dst = Breg(AL); ORB; Breg(AL) = dst; CLK(1); } variable
181 OP80( 0xb5, i_oral ) { uint32_t src = Breg(BL), dst = Breg(AL); ORB; Breg(AL) = dst; CLK(1); } variable
182 OP80( 0xb6, i_oram ) { uint32_t src = GetMemB(DS0, Wreg(BW)), dst = Breg(AL); ORB; Breg(AL) = dst;… variable
183 OP80( 0xb7, i_oraa ) { uint32_t src = Breg(AL), dst = Breg(AL); ORB; Breg(AL) = dst; CLK(1); } variable
184 OP80( 0xb8, i_cmpb ) { uint32_t src = Breg(CH), dst = Breg(AL); SUBB; CLK(1); } variable
185 OP80( 0xb9, i_cmpc ) { uint32_t src = Breg(CL), dst = Breg(AL); SUBB; CLK(1); } variable
186 OP80( 0xba, i_cmpd ) { uint32_t src = Breg(DH), dst = Breg(AL); SUBB; CLK(1); } variable
187 OP80( 0xbb, i_cmpe ) { uint32_t src = Breg(DL), dst = Breg(AL); SUBB; CLK(1); } variable
188 OP80( 0xbc, i_cmph ) { uint32_t src = Breg(BH), dst = Breg(AL); SUBB; CLK(1); } variable
189 OP80( 0xbd, i_cmpl ) { uint32_t src = Breg(BL), dst = Breg(AL); SUBB; CLK(1); } variable
190 OP80( 0xbe, i_cmpm ) { uint32_t src = GetMemB(DS0, Wreg(BW)), dst = Breg(AL); SUBB; CLK(1); } variable
191 OP80( 0xbf, i_cmpa ) { uint32_t src = Breg(AL), dst = Breg(AL); SUBB; CLK(1); } variable
198 OP80( 0xc6, i_adi ) { uint32_t src = fetch(), dst = Breg(AL); ADDB; Breg(AL) = dst; CLK(1); } variable
205 OP80( 0xce, i_aci ) { uint32_t src = fetch(), dst = Breg(AL); src+=CF; ADDB; Breg(AL) = dst; CLK(… variable
213 OP80( 0xd6, i_sui ) { uint32_t src = fetch(), dst = Breg(AL); SUBB; Breg(AL) = dst; CLK(1); } variable
219 OP80( 0xde, i_sbi ) { uint32_t src = fetch(), dst = Breg(AL); src+=CF; SUBB; Breg(AL) = dst; CLK(… variable
227 OP80( 0xe6, i_ani ) { uint32_t src = fetch(), dst = Breg(AL); ANDB; Breg(AL) = dst; CLK(1); } variable
244 OP80( 0xee, i_xri ) { uint32_t src = fetch(), dst = Breg(AL); XORB; Breg(AL) = dst; CLK(1); } variable
252 OP80( 0xf6, i_ori ) { uint32_t src = fetch(), dst = Breg(AL); ORB; Breg(AL) = dst; CLK(1); } variable
259 OP80( 0xfe, i_cpi ) { uint32_t src = fetch(), dst = Breg(AL); SUBB; CLK(1); } variable