73 			val = m_sr;  in read()
91 				m_sr &= ~REG_SR_COM;  in read()
169 			if ((m_sr & REG_SR_ON) == 0)  in write()
171 				m_sr |= REG_SR_ON; // Starts the counter  in write()
187 			if ((m_sr & REG_SR_ON) != 0)  in write()
189 				m_sr &= ~REG_SR_ON; // Stops the counter  in write()
196 				m_sr = (m_sr & ~REG_SR_COM) | 0x00ff;  in write()
220 …m_sr &= ~(data & mem_mask & (REG_SR_TO | REG_SR_TG | REG_SR_TC)); // Clear only the set interrupt …  in write()
221 		if ((m_sr & (REG_SR_IRQ | REG_SR_TO | REG_SR_TG | REG_SR_TC)) == REG_SR_IRQ)  in write()
224 			m_sr &= ~REG_SR_IRQ;  in write()
227 		data = m_sr;  in write()
257 		m_sr &= ~REG_SR_COM;  in write()
284 			m_sr |= REG_SR_TG;  in WRITE_LINE_MEMBER()
291 		m_sr |= REG_SR_TGL;  in WRITE_LINE_MEMBER()
295 		m_sr &= ~REG_SR_TGL;  in WRITE_LINE_MEMBER()
302 	if ((m_sr & REG_SR_ON) != 0)  in TIMER_CALLBACK_MEMBER()
333 	m_sr = (m_sr & REG_SR_TG) | 0x00ff;  in module_reset()
343 	assert((m_sr & (REG_SR_TO | REG_SR_TG | REG_SR_TC)) != 0);  in do_timer_irq()
344 	if ((m_sr & REG_SR_IRQ) == 0)  in do_timer_irq()
347 		m_sr |= REG_SR_IRQ;  in do_timer_irq()
362 			(m_sr & REG_SR_TG) != 0))  in do_timer_tick()
390 			m_sr &= ~REG_SR_COM;  in do_timer_tick()
395 			m_sr |= REG_SR_COM;  in do_timer_tick()
419 					if ((m_sr & REG_SR_OUT) != 0)  in do_timer_tick()
429 					if ((m_sr & REG_SR_OUT) != 0)  in do_timer_tick()
478 			m_sr |= REG_SR_TC;  in do_timer_tick()
487 			m_sr |= REG_SR_TO;  in do_timer_tick()
499 	if ((m_sr & REG_SR_OUT) == 0)  in tout_set()
501 		m_sr |= REG_SR_OUT;  in tout_set()
509 	if ((m_sr & REG_SR_OUT) != 0)  in tout_clear()
511 		m_sr &= ~REG_SR_OUT;  in tout_clear()