Lines Matching refs:u16
20 int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data);
21 int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data);
38 u16 read;
39 u16 clear;
40 u16 set;
44 u16 interrupt_status;
45 u16 interrupt_enable;
46 u16 write_mailbox_ext;
47 u16 write_mailbox;
48 u16 read_mailbox_ext;
49 u16 read_mailbox;
53 u16 version;
54 u16 features;
55 u16 control;
56 u16 xy_size;
57 u16 xy_scale;
58 u16 x_pos;
59 u16 y_pos;
63 u16 control;
64 u16 address_data;
65 u16 rx_data;
69 u16 transmit_data;
70 u16 rx_tx_control;
71 u16 receive_data;
72 u16 rx_tx_status;
73 u16 reserved;
74 u16 device_address;
75 u16 target_address;
80 u16 reflection_low; /* 0x0000 */
81 u16 versions; /* 0x0002 */
82 u16 fpga_features; /* 0x0004 */
83 u16 fpga_version; /* 0x0006 */
84 u16 reserved_0[8187]; /* 0x0008 */
85 u16 reflection_high; /* 0x3ffe */
91 u16 reflection_low; /* 0x0000 */
92 u16 versions; /* 0x0002 */
93 u16 fpga_features; /* 0x0004 */
94 u16 fpga_version; /* 0x0006 */
95 u16 reserved_0[5]; /* 0x0008 */
96 u16 quad_serdes_reset; /* 0x0012 */
97 u16 reserved_1[8181]; /* 0x0014 */
98 u16 reflection_high; /* 0x3ffe */
104 u16 status_int;
105 u16 config_int;
106 u16 switch_connect_config;
107 u16 tx_destination;
111 u16 status_int;
112 u16 config_int;
116 u16 reflection_low; /* 0x0000 */
117 u16 versions; /* 0x0002 */
118 u16 fpga_features; /* 0x0004 */
119 u16 fpga_version; /* 0x0006 */
120 u16 reserved_0[5]; /* 0x0008 */
121 u16 quad_serdes_reset; /* 0x0012 */
122 u16 reserved_1[502]; /* 0x0014 */
125 u16 reserved_2[7487]; /* 0x0580 */
126 u16 reflection_high; /* 0x3ffe */
132 u16 reflection_low; /* 0x0000 */
133 u16 versions; /* 0x0002 */
134 u16 fpga_version; /* 0x0004 */
135 u16 fpga_features; /* 0x0006 */
136 u16 reserved_0[1]; /* 0x0008 */
137 u16 top_interrupt; /* 0x000a */
138 u16 reserved_1[4]; /* 0x000c */
140 u16 mpc3w_control; /* 0x001a */
141 u16 reserved_2[2]; /* 0x001c */
143 u16 reserved_3[9]; /* 0x002e */
145 u16 reserved_4[10]; /* 0x004c */
146 u16 mc_int; /* 0x0060 */
147 u16 mc_int_en; /* 0x0062 */
148 u16 mc_status; /* 0x0064 */
149 u16 mc_control; /* 0x0066 */
150 u16 mc_tx_data; /* 0x0068 */
151 u16 mc_tx_address; /* 0x006a */
152 u16 mc_tx_cmd; /* 0x006c */
153 u16 mc_res; /* 0x006e */
154 u16 mc_rx_cmd_status; /* 0x0070 */
155 u16 mc_rx_data; /* 0x0072 */
156 u16 reserved_5[69]; /* 0x0074 */
157 u16 reflection_high; /* 0x00fe */
159 u16 reserved_6[889]; /* 0x010e */
160 u16 videomem0[2048]; /* 0x0800 */
166 u16 reflection_low; /* 0x0000 */
167 u16 versions; /* 0x0002 */
168 u16 fpga_version; /* 0x0004 */
169 u16 fpga_features; /* 0x0006 */
170 u16 reserved_0[1]; /* 0x0008 */
171 u16 top_interrupt; /* 0x000a */
172 u16 reserved_1[2]; /* 0x000c */
173 u16 control; /* 0x0010 */
174 u16 extended_control; /* 0x0012 */
176 u16 mpc3w_control; /* 0x001a */
177 u16 reserved_2[2]; /* 0x001c */
179 u16 reserved_3[9]; /* 0x002e */
181 u16 reserved_4[10]; /* 0x004c */
182 u16 mc_int; /* 0x0060 */
183 u16 mc_int_en; /* 0x0062 */
184 u16 mc_status; /* 0x0064 */
185 u16 mc_control; /* 0x0066 */
186 u16 mc_tx_data; /* 0x0068 */
187 u16 mc_tx_address; /* 0x006a */
188 u16 mc_tx_cmd; /* 0x006c */
189 u16 mc_res; /* 0x006e */
190 u16 mc_rx_cmd_status; /* 0x0070 */
191 u16 mc_rx_data; /* 0x0072 */
192 u16 reserved_5[69]; /* 0x0074 */
193 u16 reflection_high; /* 0x00fe */
196 u16 reserved_6[57]; /* 0x010e */
198 u16 reserved_7[9]; /* 0x018e */
200 u16 reserved_8[1834]; /* 0x01ac */
201 u16 videomem0[2048]; /* 0x1000 */
202 u16 videomem1[2048]; /* 0x2000 */
204 u16 reserved_6[889]; /* 0x010e */
205 u16 videomem0[2048]; /* 0x0800 */
212 u16 reflection_low; /* 0x0000 */
213 u16 versions; /* 0x0002 */
214 u16 fpga_version; /* 0x0004 */
215 u16 fpga_features; /* 0x0006 */
216 u16 reserved_0[1]; /* 0x0008 */
217 u16 top_interrupt; /* 0x000a */
218 u16 reserved_1[3]; /* 0x000c */
219 u16 extended_control; /* 0x0012 */
221 u16 mpc3w_control; /* 0x001a */
222 u16 reserved_2[2]; /* 0x001c */
224 u16 reserved_3[9]; /* 0x002e */
225 u16 mc_int; /* 0x0040 */
226 u16 mc_int_en; /* 0x0042 */
227 u16 mc_status; /* 0x0044 */
228 u16 mc_control; /* 0x0046 */
229 u16 mc_tx_data; /* 0x0048 */
230 u16 mc_tx_address; /* 0x004a */
231 u16 mc_tx_cmd; /* 0x004c */
232 u16 mc_res; /* 0x004e */
233 u16 mc_rx_cmd_status; /* 0x0050 */
234 u16 mc_rx_data; /* 0x0052 */
235 u16 reserved_4[62]; /* 0x0054 */
242 u16 reflection_low; /* 0x0000 */
243 u16 versions; /* 0x0002 */
244 u16 fpga_version; /* 0x0004 */
245 u16 fpga_features; /* 0x0006 */
246 u16 reserved_0[1]; /* 0x0008 */
247 u16 top_interrupt; /* 0x000a */
248 u16 reserved_1[4]; /* 0x000c */
250 u16 mpc3w_control; /* 0x001a */
251 u16 reserved_2[2]; /* 0x001c */
253 u16 reserved_3[9]; /* 0x002e */
255 u16 reserved_4[10]; /* 0x004c */
256 u16 mc_int; /* 0x0060 */
257 u16 mc_int_en; /* 0x0062 */
258 u16 mc_status; /* 0x0064 */
259 u16 mc_control; /* 0x0066 */
260 u16 mc_tx_data; /* 0x0068 */
261 u16 mc_tx_address; /* 0x006a */
262 u16 mc_tx_cmd; /* 0x006c */
263 u16 mc_res; /* 0x006e */
264 u16 mc_rx_cmd_status; /* 0x0070 */
265 u16 mc_rx_data; /* 0x0072 */
266 u16 reserved_5[70]; /* 0x0074 */
268 u16 reserved_6[889]; /* 0x010e */
269 u16 videomem0[2048]; /* 0x0800 */
275 u16 reflection_low; /* 0x0000 */
276 u16 versions; /* 0x0002 */
277 u16 fpga_version; /* 0x0004 */
278 u16 fpga_features; /* 0x0006 */
279 u16 reserved_0[10]; /* 0x0008 */
280 u16 extended_interrupt; /* 0x001c */
281 u16 reserved_1[29]; /* 0x001e */
282 u16 mpc3w_control; /* 0x0058 */
283 u16 reserved_2[3]; /* 0x005a */
285 u16 reserved_3[2]; /* 0x006c */
287 u16 reserved_4[194]; /* 0x007c */
289 u16 reserved_5[761]; /* 0x020e */
290 u16 videomem0[2048]; /* 0x0800 */