ath/ath9k/ar9485_initvals.h

20 static __unused const u32 ar9485_1_1_mac_core[][2] = {
182 static __unused const u32 ar9485_1_1_baseband_core[][2] = {
319 static __unused const u32 ar9485Common_1_1[][2] = {
327 static __unused const u32 ar9485_1_1_baseband_postamble[][5] = {
372 static __unused const u32 ar9485Modes_high_ob_db_tx_gain_1_1[][5] = {
445 static __unused const u32 ar9485_modes_lowest_ob_db_tx_gain_1_1[][5] = {
518 static __unused const u32 ar9485_1_1_radio_postamble[][2] = {
527 static __unused const u32 ar9485_1_1_mac_postamble[][5] = {
539 static __unused const u32 ar9485_1_1_radio_core[][2] = {
604 static __unused const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_enable_L1[][2] = {
611 static __unused const u32 ar9485Modes_high_power_tx_gain_1_1[][5] = {
684 static __unused const u32 ar9485_1_1[][2] = {
704 static __unused const u32 ar9485_modes_green_ob_db_tx_gain_1_1[][5] = {
777 static __unused const u32 ar9485_1_1_pcie_phy_clkreq_disable_L1[][2] = {
784 static __unused const u32 ar9485_1_1_soc_preamble[][2] = {
796 static __unused const u32 ar9485_1_1_baseband_core_txfir_coeff_japan_2484[][2] = {
803 static __unused const u32 ar9485Modes_low_ob_db_tx_gain_1_1[][5] = {
876 static __unused const u32 ar9485_fast_clock_1_1_baseband_postamble[][3] = {
883 static __unused const u32 ar9485_1_1_pcie_phy_pll_on_clkreq_disable_L1[][2] = {
890 static __unused const u32 ar9485_common_rx_gain_1_1[][2] = {
1022 static __unused const u32 ar9485_1_1_pcie_phy_clkreq_enable_L1[][2] = {
1029 static __unused const u32 ar9485Common_wo_xlna_rx_gain_1_1[][2] = {