Lines Matching refs:mode
220 static void radeon_write_pll_regs(struct radeonfb_info *rinfo, struct radeon_regs *mode) in radeon_write_pll_regs() argument
236 if ((mode->ppll_ref_div == (INPLL(PPLL_REF_DIV) & PPLL_REF_DIV_MASK)) && in radeon_write_pll_regs()
237 (mode->ppll_div_3 == (INPLL(PPLL_DIV_3) & in radeon_write_pll_regs()
243 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, in radeon_write_pll_regs()
263 mode->clk_cntl_index & PPLL_DIV_SEL_MASK, in radeon_write_pll_regs()
271 if (mode->ppll_ref_div & R300_PPLL_REF_DIV_ACC_MASK) { in radeon_write_pll_regs()
275 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, 0); in radeon_write_pll_regs()
279 (mode->ppll_ref_div << R300_PPLL_REF_DIV_ACC_SHIFT), in radeon_write_pll_regs()
283 OUTPLLP(PPLL_REF_DIV, mode->ppll_ref_div, ~PPLL_REF_DIV_MASK); in radeon_write_pll_regs()
286 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_FB3_DIV_MASK); in radeon_write_pll_regs()
287 OUTPLLP(PPLL_DIV_3, mode->ppll_div_3, ~PPLL_POST3_DIV_MASK); in radeon_write_pll_regs()
340 struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); in radeon_setmode() local
342 mode->crtc_gen_cntl = 0x03000200; in radeon_setmode()
343 mode->crtc_ext_cntl = 0x00008048; in radeon_setmode()
344 mode->dac_cntl = 0xff002100; in radeon_setmode()
345 mode->crtc_h_total_disp = 0x4f0063; in radeon_setmode()
346 mode->crtc_h_sync_strt_wid = 0x8c02a2; in radeon_setmode()
347 mode->crtc_v_total_disp = 0x01df020c; in radeon_setmode()
348 mode->crtc_v_sync_strt_wid = 0x8201ea; in radeon_setmode()
349 mode->crtc_pitch = 0x00500050; in radeon_setmode()
351 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); in radeon_setmode()
352 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, in radeon_setmode()
354 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); in radeon_setmode()
355 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); in radeon_setmode()
356 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); in radeon_setmode()
357 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); in radeon_setmode()
358 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); in radeon_setmode()
361 OUTREG(CRTC_PITCH, mode->crtc_pitch); in radeon_setmode()
363 mode->clk_cntl_index = 0x300; in radeon_setmode()
364 mode->ppll_ref_div = 0xc; in radeon_setmode()
365 mode->ppll_div_3 = 0x00030059; in radeon_setmode()
367 radeon_write_pll_regs(rinfo, mode); in radeon_setmode()
383 struct radeon_regs *mode = malloc(sizeof(struct radeon_regs)); in radeon_setmode_9200() local
385 mode->crtc_gen_cntl = CRTC_EN | CRTC_EXT_DISP_EN; in radeon_setmode_9200()
386 mode->crtc_ext_cntl = VGA_ATI_LINEAR | XCRT_CNT_EN | CRTC_CRT_ON; in radeon_setmode_9200()
387 mode->dac_cntl = DAC_MASK_ALL | DAC_VGA_ADR_EN | DAC_8BIT_EN; in radeon_setmode_9200()
388 mode->crtc_offset_cntl = CRTC_OFFSET_CNTL__CRTC_TILE_EN; in radeon_setmode_9200()
392 mode->crtc_gen_cntl |= 0x6 << 8; /* x888 */ in radeon_setmode_9200()
394 mode->surface_cntl = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; in radeon_setmode_9200()
395 mode->surf_info[0] = NONSURF_AP0_SWP_32BPP | NONSURF_AP1_SWP_32BPP; in radeon_setmode_9200()
399 mode->crtc_gen_cntl |= 0x4 << 8; /* 565 */ in radeon_setmode_9200()
401 mode->surface_cntl = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; in radeon_setmode_9200()
402 mode->surf_info[0] = NONSURF_AP0_SWP_16BPP | NONSURF_AP1_SWP_16BPP; in radeon_setmode_9200()
406 mode->crtc_gen_cntl |= 0x2 << 8; /* palette */ in radeon_setmode_9200()
407 mode->surface_cntl = 0x00000000; in radeon_setmode_9200()
413 mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1688,1280); in radeon_setmode_9200()
414 mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(1066,1024); in radeon_setmode_9200()
415 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(1025,3); in radeon_setmode_9200()
417 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1288,18); in radeon_setmode_9200()
418 mode->ppll_div_3 = 0x00010078; in radeon_setmode_9200()
420 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1320,14); in radeon_setmode_9200()
421 mode->ppll_div_3 = 0x00010060; in radeon_setmode_9200()
427 mode->crtc_pitch = RADEON_CRT_PITCH(1280,32); in radeon_setmode_9200()
430 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 4 / 16); in radeon_setmode_9200()
431 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,32); in radeon_setmode_9200()
434 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1280 * 2 / 16); in radeon_setmode_9200()
435 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,16); in radeon_setmode_9200()
438 mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1280 * 1 / 16); in radeon_setmode_9200()
439 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1280,1024,8); in radeon_setmode_9200()
445 mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1312,1024); in radeon_setmode_9200()
446 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1032,12); in radeon_setmode_9200()
447 mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(800,768); in radeon_setmode_9200()
448 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(769,3); in radeon_setmode_9200()
449 mode->ppll_div_3 = 0x0002008c; in radeon_setmode_9200()
451 mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1344,1024); in radeon_setmode_9200()
452 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(1040,17) | CRTC_H_SYNC_POL; in radeon_setmode_9200()
453 mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(806,768); in radeon_setmode_9200()
454 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(771,6) | CRTC_V_SYNC_POL; in radeon_setmode_9200()
455 mode->ppll_div_3 = 0x00020074; in radeon_setmode_9200()
458 mode->crtc_pitch = RADEON_CRT_PITCH(1024,32); in radeon_setmode_9200()
461 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 4 / 16); in radeon_setmode_9200()
462 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,32); in radeon_setmode_9200()
465 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (1024 * 2 / 16); in radeon_setmode_9200()
466 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,16); in radeon_setmode_9200()
469 mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); in radeon_setmode_9200()
470 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,768,8); in radeon_setmode_9200()
475 mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(1056,800); in radeon_setmode_9200()
477 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(808,10); in radeon_setmode_9200()
478 mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(625,600); in radeon_setmode_9200()
479 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,3); in radeon_setmode_9200()
480 mode->ppll_div_3 = 0x000300b0; in radeon_setmode_9200()
482 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(832,16); in radeon_setmode_9200()
483 mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(628,600); in radeon_setmode_9200()
484 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(601,4); in radeon_setmode_9200()
485 mode->ppll_div_3 = 0x0003008e; in radeon_setmode_9200()
489 mode->crtc_pitch = RADEON_CRT_PITCH(832,32); in radeon_setmode_9200()
490 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (832 * 4 / 16); in radeon_setmode_9200()
491 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(832,600,32); in radeon_setmode_9200()
494 mode->crtc_pitch = RADEON_CRT_PITCH(896,16); in radeon_setmode_9200()
495 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (896 * 2 / 16); in radeon_setmode_9200()
496 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(896,600,16); in radeon_setmode_9200()
499 mode->crtc_pitch = RADEON_CRT_PITCH(1024,8); in radeon_setmode_9200()
500 mode->surf_info[0] = R200_SURF_TILE_COLOR_MACRO | (1024 * 1 / 16); in radeon_setmode_9200()
501 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(1024,600,8); in radeon_setmode_9200()
507 mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(840,640); in radeon_setmode_9200()
508 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(648,8) | CRTC_H_SYNC_POL; in radeon_setmode_9200()
509 mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(500,480); in radeon_setmode_9200()
510 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(481,3) | CRTC_V_SYNC_POL; in radeon_setmode_9200()
511 mode->ppll_div_3 = 0x00030070; in radeon_setmode_9200()
513 mode->crtc_h_total_disp = CRTC_H_TOTAL_DISP_VAL(800,640); in radeon_setmode_9200()
514 mode->crtc_h_sync_strt_wid = CRTC_HSYNC_STRT_WID_VAL(674,12) | CRTC_H_SYNC_POL; in radeon_setmode_9200()
515 mode->crtc_v_total_disp = CRTC_V_TOTAL_DISP_VAL(525,480); in radeon_setmode_9200()
516 mode->crtc_v_sync_strt_wid = CRTC_VSYNC_STRT_WID_VAL(491,2) | CRTC_V_SYNC_POL; in radeon_setmode_9200()
517 mode->ppll_div_3 = 0x00030059; in radeon_setmode_9200()
520 mode->crtc_pitch = RADEON_CRT_PITCH(640,32); in radeon_setmode_9200()
523 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 4 / 16); in radeon_setmode_9200()
524 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,32); in radeon_setmode_9200()
527 mode->surf_info[0] |= R200_SURF_TILE_COLOR_MACRO | (640 * 2 / 16); in radeon_setmode_9200()
528 mode->surf_upper_bound[0] = SURF_UPPER_BOUND(640,480,16); in radeon_setmode_9200()
531 mode->crtc_offset_cntl = 0x00000000; in radeon_setmode_9200()
537 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl | CRTC_DISP_REQ_EN_B); in radeon_setmode_9200()
538 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, in radeon_setmode_9200()
540 OUTREGP(DAC_CNTL, mode->dac_cntl, DAC_RANGE_CNTL | DAC_BLANKING); in radeon_setmode_9200()
541 OUTREG(CRTC_H_TOTAL_DISP, mode->crtc_h_total_disp); in radeon_setmode_9200()
542 OUTREG(CRTC_H_SYNC_STRT_WID, mode->crtc_h_sync_strt_wid); in radeon_setmode_9200()
543 OUTREG(CRTC_V_TOTAL_DISP, mode->crtc_v_total_disp); in radeon_setmode_9200()
544 OUTREG(CRTC_V_SYNC_STRT_WID, mode->crtc_v_sync_strt_wid); in radeon_setmode_9200()
546 OUTREG(CRTC_OFFSET_CNTL, mode->crtc_offset_cntl); in radeon_setmode_9200()
547 OUTREG(CRTC_PITCH, mode->crtc_pitch); in radeon_setmode_9200()
548 OUTREG(CRTC_GEN_CNTL, mode->crtc_gen_cntl); in radeon_setmode_9200()
550 mode->clk_cntl_index = 0x300; in radeon_setmode_9200()
551 mode->ppll_ref_div = 0xc; in radeon_setmode_9200()
553 radeon_write_pll_regs(rinfo, mode); in radeon_setmode_9200()
555 OUTREGP(CRTC_EXT_CNTL, mode->crtc_ext_cntl, in radeon_setmode_9200()
557 OUTREG(SURFACE0_INFO, mode->surf_info[0]); in radeon_setmode_9200()
559 OUTREG(SURFACE0_UPPER_BOUND, mode->surf_upper_bound[0]); in radeon_setmode_9200()
560 OUTREG(SURFACE_CNTL, mode->surface_cntl); in radeon_setmode_9200()
565 free(mode); in radeon_setmode_9200()