Lines Matching refs:TG3_BDINFO_SIZE
1795 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 16; in tg3_rings_reset()
1797 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 4; in tg3_rings_reset()
1799 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE * 2; in tg3_rings_reset()
1801 limit = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset()
1803 for (txrcb = NIC_SRAM_SEND_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset()
1804 txrcb < limit; txrcb += TG3_BDINFO_SIZE) in tg3_rings_reset()
1811 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 17; in tg3_rings_reset()
1813 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 16; in tg3_rings_reset()
1816 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE * 4; in tg3_rings_reset()
1818 limit = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset()
1820 for (rxrcb = NIC_SRAM_RCV_RET_RCB + TG3_BDINFO_SIZE; in tg3_rings_reset()
1821 rxrcb < limit; rxrcb += TG3_BDINFO_SIZE) in tg3_rings_reset()
1857 txrcb += TG3_BDINFO_SIZE; in tg3_rings_reset()
1865 rxrcb += TG3_BDINFO_SIZE; in tg3_rings_reset()