434                                                  bool secstate)  in write_v7m_control_spsel_for_secstate()  argument
438     env->v7m.control[secstate] =  in write_v7m_control_spsel_for_secstate()
439         deposit32(env->v7m.control[secstate],  in write_v7m_control_spsel_for_secstate()
443     if (secstate == env->v7m.secure) {  in write_v7m_control_spsel_for_secstate()
2692                               bool secstate, bool priv, bool negpri)  in arm_v7m_mmu_idx_all()  argument
2704     if (secstate) {  in arm_v7m_mmu_idx_all()
2712                                                 bool secstate, bool priv)  in arm_v7m_mmu_idx_for_secstate_and_priv()  argument
2714     bool negpri = armv7m_nvic_neg_prio_requested(env->nvic, secstate);  in arm_v7m_mmu_idx_for_secstate_and_priv()
2716     return arm_v7m_mmu_idx_all(env, secstate, priv, negpri);  in arm_v7m_mmu_idx_for_secstate_and_priv()
2720 ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate)  in arm_v7m_mmu_idx_for_secstate()  argument
2723         !(env->v7m.control[secstate] & 1);  in arm_v7m_mmu_idx_for_secstate()
2725     return arm_v7m_mmu_idx_for_secstate_and_priv(env, secstate, priv);  in arm_v7m_mmu_idx_for_secstate()