Lines Matching refs:B11_8
362 #define B11_8 ((ctx->opcode >> 8) & 0xf) macro
507 tcg_gen_addi_i32(addr, REG(B11_8), B3_0 * 4); in _decode_opc()
516 tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL); in _decode_opc()
525 if (B11_8 == 15 && B7_0s < 0 && in _decode_opc()
531 tcg_gen_movi_i32(REG(B11_8), B7_0s); in _decode_opc()
536 tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW); in _decode_opc()
543 tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL); in _decode_opc()
548 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), B7_0s); in _decode_opc()
565 tcg_gen_mov_i32(REG(B11_8), REG(B7_4)); in _decode_opc()
568 tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_UB); in _decode_opc()
571 tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUW); in _decode_opc()
574 tcg_gen_qemu_st_i32(REG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL); in _decode_opc()
577 tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB); in _decode_opc()
580 tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW); in _decode_opc()
583 tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL); in _decode_opc()
588 tcg_gen_subi_i32(addr, REG(B11_8), 1); in _decode_opc()
591 tcg_gen_mov_i32(REG(B11_8), addr); /* modify register status */ in _decode_opc()
598 tcg_gen_subi_i32(addr, REG(B11_8), 2); in _decode_opc()
600 tcg_gen_mov_i32(REG(B11_8), addr); in _decode_opc()
607 tcg_gen_subi_i32(addr, REG(B11_8), 4); in _decode_opc()
609 tcg_gen_mov_i32(REG(B11_8), addr); in _decode_opc()
614 tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_SB); in _decode_opc()
615 if ( B11_8 != B7_4 ) in _decode_opc()
619 tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESW); in _decode_opc()
620 if ( B11_8 != B7_4 ) in _decode_opc()
624 tcg_gen_qemu_ld_i32(REG(B11_8), REG(B7_4), ctx->memidx, MO_TESL); in _decode_opc()
625 if ( B11_8 != B7_4 ) in _decode_opc()
631 tcg_gen_add_i32(addr, REG(B11_8), REG(0)); in _decode_opc()
639 tcg_gen_add_i32(addr, REG(B11_8), REG(0)); in _decode_opc()
647 tcg_gen_add_i32(addr, REG(B11_8), REG(0)); in _decode_opc()
656 tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_SB); in _decode_opc()
664 tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESW); in _decode_opc()
672 tcg_gen_qemu_ld_i32(REG(B11_8), addr, ctx->memidx, MO_TESL); in _decode_opc()
681 tcg_gen_deposit_i32(REG(B11_8), REG(B7_4), low, 0, 16); in _decode_opc()
686 tcg_gen_rotli_i32(REG(B11_8), REG(B7_4), 16); in _decode_opc()
694 tcg_gen_shri_i32(low, REG(B11_8), 16); in _decode_opc()
695 tcg_gen_or_i32(REG(B11_8), high, low); in _decode_opc()
701 tcg_gen_add_i32(REG(B11_8), REG(B11_8), REG(B7_4)); in _decode_opc()
709 tcg_gen_add2_i32(REG(B11_8), cpu_sr_t, in _decode_opc()
710 REG(B11_8), t0, t1, cpu_sr_t); in _decode_opc()
719 tcg_gen_add_i32(t0, REG(B7_4), REG(B11_8)); in _decode_opc()
721 tcg_gen_xor_i32(t1, t0, REG(B11_8)); in _decode_opc()
723 tcg_gen_xor_i32(t2, REG(B7_4), REG(B11_8)); in _decode_opc()
733 tcg_gen_and_i32(REG(B11_8), REG(B11_8), REG(B7_4)); in _decode_opc()
736 tcg_gen_setcond_i32(TCG_COND_EQ, cpu_sr_t, REG(B11_8), REG(B7_4)); in _decode_opc()
739 tcg_gen_setcond_i32(TCG_COND_GE, cpu_sr_t, REG(B11_8), REG(B7_4)); in _decode_opc()
742 tcg_gen_setcond_i32(TCG_COND_GT, cpu_sr_t, REG(B11_8), REG(B7_4)); in _decode_opc()
745 tcg_gen_setcond_i32(TCG_COND_GTU, cpu_sr_t, REG(B11_8), REG(B7_4)); in _decode_opc()
748 tcg_gen_setcond_i32(TCG_COND_GEU, cpu_sr_t, REG(B11_8), REG(B7_4)); in _decode_opc()
754 tcg_gen_xor_i32(cmp2, REG(B7_4), REG(B11_8)); in _decode_opc()
764 tcg_gen_shri_i32(cpu_sr_q, REG(B11_8), 31); /* SR_Q */ in _decode_opc()
777 tcg_gen_shri_i32(t0, REG(B11_8), 31); in _decode_opc()
778 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); in _decode_opc()
779 tcg_gen_or_i32(REG(B11_8), REG(B11_8), cpu_sr_t); in _decode_opc()
789 tcg_gen_add2_i32(REG(B11_8), t1, REG(B11_8), zero, t2, t1); in _decode_opc()
804 tcg_gen_muls2_i32(cpu_macl, cpu_mach, REG(B7_4), REG(B11_8)); in _decode_opc()
807 tcg_gen_mulu2_i32(cpu_macl, cpu_mach, REG(B7_4), REG(B11_8)); in _decode_opc()
810 tcg_gen_ext8s_i32(REG(B11_8), REG(B7_4)); in _decode_opc()
813 tcg_gen_ext16s_i32(REG(B11_8), REG(B7_4)); in _decode_opc()
816 tcg_gen_ext8u_i32(REG(B11_8), REG(B7_4)); in _decode_opc()
819 tcg_gen_ext16u_i32(REG(B11_8), REG(B7_4)); in _decode_opc()
827 tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, MO_TESL); in _decode_opc()
832 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); in _decode_opc()
841 tcg_gen_qemu_ld_i32(arg1, REG(B11_8), ctx->memidx, MO_TESL); in _decode_opc()
845 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 2); in _decode_opc()
850 tcg_gen_mul_i32(cpu_macl, REG(B7_4), REG(B11_8)); in _decode_opc()
858 tcg_gen_ext16s_i32(arg1, REG(B11_8)); in _decode_opc()
870 tcg_gen_ext16u_i32(arg1, REG(B11_8)); in _decode_opc()
877 tcg_gen_neg_i32(REG(B11_8), REG(B7_4)); in _decode_opc()
882 tcg_gen_add2_i32(REG(B11_8), cpu_sr_t, in _decode_opc()
884 tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t, in _decode_opc()
885 t0, t0, REG(B11_8), cpu_sr_t); in _decode_opc()
891 tcg_gen_not_i32(REG(B11_8), REG(B7_4)); in _decode_opc()
894 tcg_gen_or_i32(REG(B11_8), REG(B11_8), REG(B7_4)); in _decode_opc()
905 tcg_gen_shl_i32(t1, REG(B11_8), t0); in _decode_opc()
910 tcg_gen_sar_i32(t2, REG(B11_8), t0); in _decode_opc()
915 tcg_gen_movcond_i32(TCG_COND_GE, REG(B11_8), REG(B7_4), t0, t1, t2); in _decode_opc()
931 tcg_gen_shl_i32(t1, REG(B11_8), t0); in _decode_opc()
936 tcg_gen_shr_i32(t2, REG(B11_8), t0); in _decode_opc()
941 tcg_gen_movcond_i32(TCG_COND_GE, REG(B11_8), REG(B7_4), t0, t1, t2); in _decode_opc()
949 tcg_gen_sub_i32(REG(B11_8), REG(B11_8), REG(B7_4)); in _decode_opc()
957 tcg_gen_sub2_i32(REG(B11_8), cpu_sr_t, in _decode_opc()
958 REG(B11_8), t0, t1, cpu_sr_t); in _decode_opc()
968 tcg_gen_sub_i32(t0, REG(B11_8), REG(B7_4)); in _decode_opc()
972 tcg_gen_xor_i32(t2, REG(B11_8), REG(B7_4)); in _decode_opc()
977 tcg_gen_mov_i32(REG(B11_8), t0); in _decode_opc()
984 tcg_gen_and_i32(val, REG(B7_4), REG(B11_8)); in _decode_opc()
990 tcg_gen_xor_i32(REG(B11_8), REG(B11_8), REG(B7_4)); in _decode_opc()
996 int xdst = XHACK(B11_8); in _decode_opc()
1000 tcg_gen_mov_i32(FREG(B11_8), FREG(B7_4)); in _decode_opc()
1008 tcg_gen_qemu_st_i64(fp, REG(B11_8), ctx->memidx, MO_TEQ); in _decode_opc()
1011 tcg_gen_qemu_st_i32(FREG(B7_4), REG(B11_8), ctx->memidx, MO_TEUL); in _decode_opc()
1019 gen_store_fpr64(ctx, fp, XHACK(B11_8)); in _decode_opc()
1022 tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TEUL); in _decode_opc()
1030 gen_store_fpr64(ctx, fp, XHACK(B11_8)); in _decode_opc()
1034 tcg_gen_qemu_ld_i32(FREG(B11_8), REG(B7_4), ctx->memidx, MO_TEUL); in _decode_opc()
1045 tcg_gen_subi_i32(addr, REG(B11_8), 8); in _decode_opc()
1049 tcg_gen_subi_i32(addr, REG(B11_8), 4); in _decode_opc()
1052 tcg_gen_mov_i32(REG(B11_8), addr); in _decode_opc()
1064 gen_store_fpr64(ctx, fp, XHACK(B11_8)); in _decode_opc()
1067 tcg_gen_qemu_ld_i32(FREG(B11_8), addr, ctx->memidx, MO_TEUL); in _decode_opc()
1076 tcg_gen_add_i32(addr, REG(B11_8), REG(0)); in _decode_opc()
1104 gen_load_fpr64(ctx, fp0, B11_8); in _decode_opc()
1126 gen_store_fpr64(ctx, fp0, B11_8); in _decode_opc()
1132 gen_helper_fadd_FT(FREG(B11_8), cpu_env, in _decode_opc()
1133 FREG(B11_8), FREG(B7_4)); in _decode_opc()
1136 gen_helper_fsub_FT(FREG(B11_8), cpu_env, in _decode_opc()
1137 FREG(B11_8), FREG(B7_4)); in _decode_opc()
1140 gen_helper_fmul_FT(FREG(B11_8), cpu_env, in _decode_opc()
1141 FREG(B11_8), FREG(B7_4)); in _decode_opc()
1144 gen_helper_fdiv_FT(FREG(B11_8), cpu_env, in _decode_opc()
1145 FREG(B11_8), FREG(B7_4)); in _decode_opc()
1149 FREG(B11_8), FREG(B7_4)); in _decode_opc()
1153 FREG(B11_8), FREG(B7_4)); in _decode_opc()
1162 gen_helper_fmac_FT(FREG(B11_8), cpu_env, in _decode_opc()
1163 FREG(0), FREG(B7_4), FREG(B11_8)); in _decode_opc()
1357 tcg_gen_mov_i32(ALTREG(B6_4), REG(B11_8)); in _decode_opc()
1361 tcg_gen_qemu_ld_i32(ALTREG(B6_4), REG(B11_8), ctx->memidx, MO_TESL); in _decode_opc()
1362 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); in _decode_opc()
1366 tcg_gen_mov_i32(REG(B11_8), ALTREG(B6_4)); in _decode_opc()
1372 tcg_gen_subi_i32(addr, REG(B11_8), 4); in _decode_opc()
1374 tcg_gen_mov_i32(REG(B11_8), addr); in _decode_opc()
1383 tcg_gen_addi_i32(cpu_delayed_pc, REG(B11_8), ctx->base.pc_next + 4); in _decode_opc()
1390 tcg_gen_add_i32(cpu_delayed_pc, REG(B11_8), cpu_pr); in _decode_opc()
1395 tcg_gen_setcondi_i32(TCG_COND_GT, cpu_sr_t, REG(B11_8), 0); in _decode_opc()
1398 tcg_gen_setcondi_i32(TCG_COND_GE, cpu_sr_t, REG(B11_8), 0); in _decode_opc()
1401 tcg_gen_subi_i32(REG(B11_8), REG(B11_8), 1); in _decode_opc()
1402 tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_sr_t, REG(B11_8), 0); in _decode_opc()
1406 tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); in _decode_opc()
1413 tcg_gen_mov_i32(cpu_delayed_pc, REG(B11_8)); in _decode_opc()
1421 tcg_gen_andi_i32(val, REG(B11_8), 0x700083f3); in _decode_opc()
1431 tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, MO_TESL); in _decode_opc()
1435 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); in _decode_opc()
1441 gen_read_sr(REG(B11_8)); in _decode_opc()
1448 tcg_gen_subi_i32(addr, REG(B11_8), 4); in _decode_opc()
1451 tcg_gen_mov_i32(REG(B11_8), addr); in _decode_opc()
1459 tcg_gen_mov_i32 (cpu_##reg, REG(B11_8)); \ in _decode_opc()
1463 tcg_gen_qemu_ld_i32(cpu_##reg, REG(B11_8), ctx->memidx, MO_TESL); \ in _decode_opc()
1464 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); \ in _decode_opc()
1469 tcg_gen_mov_i32 (REG(B11_8), cpu_##reg); \ in _decode_opc()
1475 tcg_gen_subi_i32(addr, REG(B11_8), 4); \ in _decode_opc()
1477 tcg_gen_mov_i32(REG(B11_8), addr); \ in _decode_opc()
1497 gen_helper_ld_fpscr(cpu_env, REG(B11_8)); in _decode_opc()
1504 tcg_gen_qemu_ld_i32(addr, REG(B11_8), ctx->memidx, MO_TESL); in _decode_opc()
1505 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); in _decode_opc()
1513 tcg_gen_andi_i32(REG(B11_8), cpu_fpscr, 0x003fffff); in _decode_opc()
1522 tcg_gen_subi_i32(addr, REG(B11_8), 4); in _decode_opc()
1524 tcg_gen_mov_i32(REG(B11_8), addr); in _decode_opc()
1532 tcg_gen_qemu_ld_i32(val, REG(B11_8), ctx->memidx, MO_TEUL); in _decode_opc()
1533 gen_helper_movcal(cpu_env, REG(B11_8), val); in _decode_opc()
1534 tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL); in _decode_opc()
1542 tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, in _decode_opc()
1548 tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, in _decode_opc()
1550 tcg_gen_addi_i32(REG(B11_8), REG(B11_8), 4); in _decode_opc()
1553 tcg_gen_mov_i32(REG(B11_8), cpu_sr_t); in _decode_opc()
1573 tcg_gen_brcond_i32(TCG_COND_NE, REG(B11_8), in _decode_opc()
1576 tcg_gen_atomic_cmpxchg_i32(tmp, REG(B11_8), cpu_lock_value, in _decode_opc()
1582 tcg_gen_qemu_st_i32(REG(0), REG(B11_8), ctx->memidx, MO_TEUL); in _decode_opc()
1606 tcg_gen_mov_i32(tmp, REG(B11_8)); in _decode_opc()
1607 tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL); in _decode_opc()
1612 tcg_gen_qemu_ld_i32(REG(0), REG(B11_8), ctx->memidx, MO_TESL); in _decode_opc()
1618 gen_helper_ocbi(cpu_env, REG(B11_8)); in _decode_opc()
1643 tcg_gen_shri_i32(cpu_sr_t, REG(B11_8), 31); in _decode_opc()
1644 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); in _decode_opc()
1645 tcg_gen_or_i32(REG(B11_8), REG(B11_8), tmp); in _decode_opc()
1653 tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 1); in _decode_opc()
1654 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1); in _decode_opc()
1655 tcg_gen_or_i32(REG(B11_8), REG(B11_8), tmp); in _decode_opc()
1660 tcg_gen_rotli_i32(REG(B11_8), REG(B11_8), 1); in _decode_opc()
1661 tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 0); in _decode_opc()
1664 tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 0); in _decode_opc()
1665 tcg_gen_rotri_i32(REG(B11_8), REG(B11_8), 1); in _decode_opc()
1669 tcg_gen_shri_i32(cpu_sr_t, REG(B11_8), 31); in _decode_opc()
1670 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 1); in _decode_opc()
1673 tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 1); in _decode_opc()
1674 tcg_gen_sari_i32(REG(B11_8), REG(B11_8), 1); in _decode_opc()
1677 tcg_gen_andi_i32(cpu_sr_t, REG(B11_8), 1); in _decode_opc()
1678 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 1); in _decode_opc()
1681 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 2); in _decode_opc()
1684 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 8); in _decode_opc()
1687 tcg_gen_shli_i32(REG(B11_8), REG(B11_8), 16); in _decode_opc()
1690 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 2); in _decode_opc()
1693 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 8); in _decode_opc()
1696 tcg_gen_shri_i32(REG(B11_8), REG(B11_8), 16); in _decode_opc()
1701 tcg_gen_atomic_fetch_or_i32(val, REG(B11_8), val, in _decode_opc()
1709 tcg_gen_mov_i32(FREG(B11_8), cpu_fpul); in _decode_opc()
1713 tcg_gen_mov_i32(cpu_fpul, FREG(B11_8)); in _decode_opc()
1724 gen_store_fpr64(ctx, fp, B11_8); in _decode_opc()
1728 gen_helper_float_FT(FREG(B11_8), cpu_env, cpu_fpul); in _decode_opc()
1739 gen_load_fpr64(ctx, fp, B11_8); in _decode_opc()
1744 gen_helper_ftrc_FT(cpu_fpul, cpu_env, FREG(B11_8)); in _decode_opc()
1749 tcg_gen_xori_i32(FREG(B11_8), FREG(B11_8), 0x80000000); in _decode_opc()
1753 tcg_gen_andi_i32(FREG(B11_8), FREG(B11_8), 0x7fffffff); in _decode_opc()
1762 gen_load_fpr64(ctx, fp, B11_8); in _decode_opc()
1764 gen_store_fpr64(ctx, fp, B11_8); in _decode_opc()
1767 gen_helper_fsqrt_FT(FREG(B11_8), cpu_env, FREG(B11_8)); in _decode_opc()
1773 gen_helper_fsrra_FT(FREG(B11_8), cpu_env, FREG(B11_8)); in _decode_opc()
1778 tcg_gen_movi_i32(FREG(B11_8), 0); in _decode_opc()
1783 tcg_gen_movi_i32(FREG(B11_8), 0x3f800000); in _decode_opc()
1790 gen_store_fpr64(ctx, fp, B11_8); in _decode_opc()
1798 gen_load_fpr64(ctx, fp, B11_8); in _decode_opc()
1949 ld_dst = B11_8; in decode_gusa()
1967 op_dst = B11_8; in decode_gusa()
2003 if (op_dst != B11_8) { in decode_gusa()
2025 op_dst = B11_8; in decode_gusa()
2031 if (op_dst != B11_8 || mv_src >= 0) { in decode_gusa()
2042 if ((ld_dst == B11_8) + (ld_dst == B7_4) != 1 || mv_src >= 0) { in decode_gusa()
2046 op_src = (ld_dst == B11_8 ? B7_4 : B11_8); in decode_gusa()
2064 mt_dst = B11_8; in decode_gusa()
2077 if (ld_dst != B11_8 || ld_dst != B7_4 || mv_src >= 0) { in decode_gusa()
2117 if (ld_adr != B11_8 || st_mop != (ld_mop & MO_SIZE)) { in decode_gusa()