Lines Matching refs:APU
77 apu_t APU; /* Actual APUs */ member
138 dmc_buffer[cycle] = dmc_buffer[cycle + 1] = apu_dpcm(info, &info->APU.dpcm); in nesapu_runclock()
524 info->APU.squ[chan].regs[0] = value; in apu_regwrite()
532 info->APU.squ[chan].regs[1] = value; in apu_regwrite()
540 info->APU.squ[chan].regs[2] = value; in apu_regwrite()
541 if (info->APU.squ[chan].enabled) in apu_regwrite()
542 info->APU.squ[chan].freq = (info->APU.squ[chan].freq & 0xff00ffff) + (value << 16); in apu_regwrite()
550 info->APU.squ[chan].regs[3] = value; in apu_regwrite()
553 if (info->APU.squ[chan].enabled) in apu_regwrite()
555 info->APU.squ[chan].vbl_length = info->vbl_times[value >> 3]; in apu_regwrite()
556 info->APU.squ[chan].env_vol = 0xff; // env-restart in apu_regwrite()
557 info->APU.squ[chan].freq = (info->APU.squ[chan].freq & 0x00ffffff) + ((value & 0x7) << (16+8)); in apu_regwrite()
558 info->APU.squ[chan].adder = 0; // restart pulse phase in apu_regwrite()
565 info->APU.tri.regs[0] = value; in apu_regwrite()
567 if (info->APU.tri.enabled) in apu_regwrite()
569 if (false == info->APU.tri.counter_started) in apu_regwrite()
570 info->APU.tri.linear_length = info->sync_times2[value & 0x7F]; in apu_regwrite()
577 info->APU.tri.regs[1] = value; in apu_regwrite()
581 info->APU.tri.regs[2] = value; in apu_regwrite()
585 info->APU.tri.regs[3] = value; in apu_regwrite()
603 info->APU.tri.write_latency = (info->samps_per_sync + 239) / 240; in apu_regwrite()
605 if (info->APU.tri.enabled) in apu_regwrite()
607 info->APU.tri.counter_started = false; in apu_regwrite()
608 info->APU.tri.vbl_length = info->vbl_times[value >> 3]; in apu_regwrite()
609 info->APU.tri.linear_length = info->sync_times2[info->APU.tri.regs[0] & 0x7F]; in apu_regwrite()
616 info->APU.noi.regs[0] = value; in apu_regwrite()
621 info->APU.noi.regs[1] = value; in apu_regwrite()
625 info->APU.noi.regs[2] = value; in apu_regwrite()
629 info->APU.noi.regs[3] = value; in apu_regwrite()
631 if (info->APU.noi.enabled) in apu_regwrite()
633 info->APU.noi.vbl_length = info->vbl_times[value >> 3]; in apu_regwrite()
634 info->APU.noi.env_phase = 0x80000; // force restart in apu_regwrite()
640 info->APU.dpcm.regs[0] = value; in apu_regwrite()
643 info->APU.dpcm.irq_occurred = false; in apu_regwrite()
648 info->APU.dpcm.regs[1] = value & 0x7F; in apu_regwrite()
649 info->APU.dpcm.vol = info->APU.dpcm.regs[1]; in apu_regwrite()
653 info->APU.dpcm.regs[2] = value; in apu_regwrite()
657 info->APU.dpcm.regs[3] = value; in apu_regwrite()
672 info->APU.squ[2].enabled = TRUE; in apu_regwrite()
675 info->APU.squ[2].enabled = false; in apu_regwrite()
676 info->APU.squ[2].vbl_length = 0; in apu_regwrite()
680 info->APU.squ[3].enabled = TRUE; in apu_regwrite()
683 info->APU.squ[3].enabled = false; in apu_regwrite()
684 info->APU.squ[3].vbl_length = 0; in apu_regwrite()
690 info->APU.squ[0].enabled = TRUE; in apu_regwrite()
693 info->APU.squ[0].enabled = false; in apu_regwrite()
694 info->APU.squ[0].vbl_length = 0; in apu_regwrite()
698 info->APU.squ[1].enabled = TRUE; in apu_regwrite()
701 info->APU.squ[1].enabled = false; in apu_regwrite()
702 info->APU.squ[1].vbl_length = 0; in apu_regwrite()
706 info->APU.tri.enabled = TRUE; in apu_regwrite()
709 info->APU.tri.enabled = false; in apu_regwrite()
710 info->APU.tri.vbl_length = 0; in apu_regwrite()
711 info->APU.tri.linear_length = 0; in apu_regwrite()
712 info->APU.tri.counter_started = false; in apu_regwrite()
713 info->APU.tri.write_latency = 0; in apu_regwrite()
717 info->APU.noi.enabled = TRUE; in apu_regwrite()
720 info->APU.noi.enabled = false; in apu_regwrite()
721 info->APU.noi.vbl_length = 0; in apu_regwrite()
724 info->APU.dpcm.irq_occurred = false; in apu_regwrite()
730 if (0 == info->APU.dpcm.length) in apu_regwrite()
733 apu_dpcmreset(&info->APU.dpcm); in apu_regwrite()
734 if (info->APU.dpcm.dmc_buffer_filled == 0) { in apu_regwrite()
735 apu_dpcm_loadbyte(&info->APU.dpcm); in apu_regwrite()
740 info->APU.dpcm.length = 0; in apu_regwrite()
782 square1 = apu_square(info, &info->APU.squ[0], 1); in apu_update()
783 square2 = apu_square(info, &info->APU.squ[1], 0); in apu_update()
784 square3 = apu_square(info, &info->APU.squ[2], 0); // mmc5 in apu_update()
785 square4 = apu_square(info, &info->APU.squ[3], 0); // mmc5 in apu_update()
786 INT32 triangle = apu_triangle(info, &info->APU.tri); in apu_update()
787 INT32 noise = apu_noise(info, &info->APU.noi); in apu_update()
848 if (info->APU.squ[2].vbl_length > 0) in nesapuRead()
851 if (info->APU.squ[3].vbl_length > 0) in nesapuRead()
858 if (info->APU.squ[0].vbl_length > 0) in nesapuRead()
861 if (info->APU.squ[1].vbl_length > 0) in nesapuRead()
864 if (info->APU.tri.vbl_length > 0) in nesapuRead()
867 if (info->APU.noi.vbl_length > 0) in nesapuRead()
870 if (info->APU.dpcm.length > 0) { in nesapuRead()
883 if (info->APU.dpcm.irq_occurred == TRUE) in nesapuRead()
888 return info->APU.regs[address&0x1f]; in nesapuRead()
909 info->APU.regs[address]=value; in nesapuWrite()
933 memset(&info->APU.squ, 0, sizeof(info->APU.squ)); in nesapuReset()
934 memset(&info->APU.tri, 0, sizeof(info->APU.tri)); in nesapuReset()
935 memset(&info->APU.noi, 0, sizeof(info->APU.noi)); in nesapuReset()
936 memset(&info->APU.dpcm, 0, sizeof(info->APU.dpcm)); in nesapuReset()
937 memset(&info->APU.regs, 0, sizeof(info->APU.regs)); in nesapuReset()
939 info->APU.dpcm.bits_left = 8; in nesapuReset()
940 info->APU.noi.lfsr = 1; in nesapuReset()
1061 SCAN_VAR(info->APU.squ); in nesapuScan()
1062 SCAN_VAR(info->APU.tri); in nesapuScan()
1063 SCAN_VAR(info->APU.noi); in nesapuScan()
1064 SCAN_VAR(info->APU.dpcm); in nesapuScan()
1065 SCAN_VAR(info->APU.regs); in nesapuScan()