Lines Matching refs:enc
76 static void radeon_enc_op_balance(struct radeon_encoder *enc) in radeon_enc_op_balance() argument
82 static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc) in radeon_enc_slice_header_hevc() argument
90 RADEON_ENC_BEGIN(enc->cmd.slice_header); in radeon_enc_slice_header_hevc()
91 radeon_enc_reset(enc); in radeon_enc_slice_header_hevc()
92 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_slice_header_hevc()
94 cdw_start = enc->cs.current.cdw; in radeon_enc_slice_header_hevc()
95 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header_hevc()
96 radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6); in radeon_enc_slice_header_hevc()
97 radeon_enc_code_fixed_bits(enc, 0x0, 6); in radeon_enc_slice_header_hevc()
98 radeon_enc_code_fixed_bits(enc, 0x1, 3); in radeon_enc_slice_header_hevc()
100 radeon_enc_flush_headers(enc); in radeon_enc_slice_header_hevc()
102 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header_hevc()
103 bits_copied = enc->bits_output; in radeon_enc_slice_header_hevc()
109 if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23)) in radeon_enc_slice_header_hevc()
110 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header_hevc()
112 radeon_enc_code_ue(enc, 0x0); in radeon_enc_slice_header_hevc()
114 radeon_enc_flush_headers(enc); in radeon_enc_slice_header_hevc()
116 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header_hevc()
117 bits_copied = enc->bits_output; in radeon_enc_slice_header_hevc()
126 switch (enc->enc_pic.picture_type) { in radeon_enc_slice_header_hevc()
129 radeon_enc_code_ue(enc, 0x2); in radeon_enc_slice_header_hevc()
133 radeon_enc_code_ue(enc, 0x1); in radeon_enc_slice_header_hevc()
136 radeon_enc_code_ue(enc, 0x0); in radeon_enc_slice_header_hevc()
139 radeon_enc_code_ue(enc, 0x1); in radeon_enc_slice_header_hevc()
142 if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) { in radeon_enc_slice_header_hevc()
143 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, enc->enc_pic.log2_max_poc); in radeon_enc_slice_header_hevc()
144 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) in radeon_enc_slice_header_hevc()
145 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_slice_header_hevc()
147 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header_hevc()
148 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header_hevc()
149 radeon_enc_code_ue(enc, 0x0); in radeon_enc_slice_header_hevc()
150 radeon_enc_code_ue(enc, 0x0); in radeon_enc_slice_header_hevc()
154 if (enc->enc_pic.sample_adaptive_offset_enabled_flag) { in radeon_enc_slice_header_hevc()
155 radeon_enc_flush_headers(enc); in radeon_enc_slice_header_hevc()
157 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header_hevc()
158 bits_copied = enc->bits_output; in radeon_enc_slice_header_hevc()
165 if ((enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) || in radeon_enc_slice_header_hevc()
166 (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)) { in radeon_enc_slice_header_hevc()
167 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header_hevc()
168 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1); in radeon_enc_slice_header_hevc()
169 radeon_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand); in radeon_enc_slice_header_hevc()
172 radeon_enc_flush_headers(enc); in radeon_enc_slice_header_hevc()
174 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header_hevc()
175 bits_copied = enc->bits_output; in radeon_enc_slice_header_hevc()
181 if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) && in radeon_enc_slice_header_hevc()
182 (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled || in radeon_enc_slice_header_hevc()
183 enc->enc_pic.sample_adaptive_offset_enabled_flag)) { in radeon_enc_slice_header_hevc()
184 if (enc->enc_pic.sample_adaptive_offset_enabled_flag) { in radeon_enc_slice_header_hevc()
185 radeon_enc_flush_headers(enc); in radeon_enc_slice_header_hevc()
187 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header_hevc()
188 bits_copied = enc->bits_output; in radeon_enc_slice_header_hevc()
195 … radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1); in radeon_enc_slice_header_hevc()
198 radeon_enc_flush_headers(enc); in radeon_enc_slice_header_hevc()
200 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header_hevc()
201 bits_copied = enc->bits_output; in radeon_enc_slice_header_hevc()
205 cdw_filled = enc->cs.current.cdw - cdw_start; in radeon_enc_slice_header_hevc()
217 static void radeon_enc_quality_params(struct radeon_encoder *enc) in radeon_enc_quality_params() argument
219 enc->enc_pic.quality_params.vbaq_mode = 0; in radeon_enc_quality_params()
220 enc->enc_pic.quality_params.scene_change_sensitivity = 0; in radeon_enc_quality_params()
221 enc->enc_pic.quality_params.scene_change_min_idr_interval = 0; in radeon_enc_quality_params()
222 enc->enc_pic.quality_params.two_pass_search_center_map_mode = 0; in radeon_enc_quality_params()
224 RADEON_ENC_BEGIN(enc->cmd.quality_params); in radeon_enc_quality_params()
225 RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode); in radeon_enc_quality_params()
226 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity); in radeon_enc_quality_params()
227 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval); in radeon_enc_quality_params()
228 RADEON_ENC_CS(enc->enc_pic.quality_params.two_pass_search_center_map_mode); in radeon_enc_quality_params()
232 static void radeon_enc_loop_filter_hevc(struct radeon_encoder *enc) in radeon_enc_loop_filter_hevc() argument
234 RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc); in radeon_enc_loop_filter_hevc()
235 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled); in radeon_enc_loop_filter_hevc()
236 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled); in radeon_enc_loop_filter_hevc()
237 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_enc_loop_filter_hevc()
238 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2); in radeon_enc_loop_filter_hevc()
239 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset); in radeon_enc_loop_filter_hevc()
240 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset); in radeon_enc_loop_filter_hevc()
241 RADEON_ENC_CS(!enc->enc_pic.sample_adaptive_offset_enabled_flag); in radeon_enc_loop_filter_hevc()
245 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc) in radeon_enc_nalu_sps_hevc() argument
247 RADEON_ENC_BEGIN(enc->cmd.nalu); in radeon_enc_nalu_sps_hevc()
249 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_enc_nalu_sps_hevc()
252 radeon_enc_reset(enc); in radeon_enc_nalu_sps_hevc()
253 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_nalu_sps_hevc()
254 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); in radeon_enc_nalu_sps_hevc()
255 radeon_enc_code_fixed_bits(enc, 0x4201, 16); in radeon_enc_nalu_sps_hevc()
256 radeon_enc_byte_align(enc); in radeon_enc_nalu_sps_hevc()
257 radeon_enc_set_emulation_prevention(enc, true); in radeon_enc_nalu_sps_hevc()
258 radeon_enc_code_fixed_bits(enc, 0x0, 4); in radeon_enc_nalu_sps_hevc()
259 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3); in radeon_enc_nalu_sps_hevc()
260 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps_hevc()
261 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_sps_hevc()
262 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1); in radeon_enc_nalu_sps_hevc()
263 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5); in radeon_enc_nalu_sps_hevc()
265 if (enc->enc_pic.general_profile_idc == 2) in radeon_enc_nalu_sps_hevc()
266 radeon_enc_code_fixed_bits(enc, 0x20000000, 32); in radeon_enc_nalu_sps_hevc()
268 radeon_enc_code_fixed_bits(enc, 0x60000000, 32); in radeon_enc_nalu_sps_hevc()
270 radeon_enc_code_fixed_bits(enc, 0xb0000000, 32); in radeon_enc_nalu_sps_hevc()
271 radeon_enc_code_fixed_bits(enc, 0x0, 16); in radeon_enc_nalu_sps_hevc()
272 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8); in radeon_enc_nalu_sps_hevc()
274 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++) in radeon_enc_nalu_sps_hevc()
275 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_sps_hevc()
277 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) { in radeon_enc_nalu_sps_hevc()
278 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++) in radeon_enc_nalu_sps_hevc()
279 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_sps_hevc()
282 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps_hevc()
283 radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc); in radeon_enc_nalu_sps_hevc()
284 radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width); in radeon_enc_nalu_sps_hevc()
285 radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height); in radeon_enc_nalu_sps_hevc()
287 if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right != 0) || in radeon_enc_nalu_sps_hevc()
288 (enc->enc_pic.crop_top != 0) || (enc->enc_pic.crop_bottom != 0)) { in radeon_enc_nalu_sps_hevc()
289 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps_hevc()
290 radeon_enc_code_ue(enc, enc->enc_pic.crop_left); in radeon_enc_nalu_sps_hevc()
291 radeon_enc_code_ue(enc, enc->enc_pic.crop_right); in radeon_enc_nalu_sps_hevc()
292 radeon_enc_code_ue(enc, enc->enc_pic.crop_top); in radeon_enc_nalu_sps_hevc()
293 radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom); in radeon_enc_nalu_sps_hevc()
294 } else if (enc->enc_pic.session_init.padding_width != 0 || in radeon_enc_nalu_sps_hevc()
295 enc->enc_pic.session_init.padding_height != 0) { in radeon_enc_nalu_sps_hevc()
296 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps_hevc()
297 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_width / 2); in radeon_enc_nalu_sps_hevc()
298 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_width / 2); in radeon_enc_nalu_sps_hevc()
299 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_height / 2); in radeon_enc_nalu_sps_hevc()
300 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_height / 2); in radeon_enc_nalu_sps_hevc()
302 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
304 radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8); in radeon_enc_nalu_sps_hevc()
305 radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8); in radeon_enc_nalu_sps_hevc()
306 radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4); in radeon_enc_nalu_sps_hevc()
307 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
308 radeon_enc_code_ue(enc, 1); in radeon_enc_nalu_sps_hevc()
309 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps_hevc()
310 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps_hevc()
311 radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3); in radeon_enc_nalu_sps_hevc()
313 radeon_enc_code_ue(enc, in radeon_enc_nalu_sps_hevc()
314 6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3)); in radeon_enc_nalu_sps_hevc()
315 radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2); in radeon_enc_nalu_sps_hevc()
316 radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size); in radeon_enc_nalu_sps_hevc()
317 radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter); in radeon_enc_nalu_sps_hevc()
318 radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra); in radeon_enc_nalu_sps_hevc()
320 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
321 radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1); in radeon_enc_nalu_sps_hevc()
322 radeon_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1); in radeon_enc_nalu_sps_hevc()
323 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1); in radeon_enc_nalu_sps_hevc()
325 radeon_enc_code_ue(enc, 1); in radeon_enc_nalu_sps_hevc()
326 radeon_enc_code_ue(enc, 1); in radeon_enc_nalu_sps_hevc()
327 radeon_enc_code_ue(enc, 0); in radeon_enc_nalu_sps_hevc()
328 radeon_enc_code_ue(enc, 0); in radeon_enc_nalu_sps_hevc()
329 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps_hevc()
331 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
333 radeon_enc_code_fixed_bits(enc, 0, 1); in radeon_enc_nalu_sps_hevc()
334 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1); in radeon_enc_nalu_sps_hevc()
336 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
338 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
340 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps_hevc()
342 radeon_enc_byte_align(enc); in radeon_enc_nalu_sps_hevc()
343 radeon_enc_flush_headers(enc); in radeon_enc_nalu_sps_hevc()
344 *size_in_bytes = (enc->bits_output + 7) / 8; in radeon_enc_nalu_sps_hevc()
348 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc) in radeon_enc_nalu_pps_hevc() argument
350 RADEON_ENC_BEGIN(enc->cmd.nalu); in radeon_enc_nalu_pps_hevc()
352 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_enc_nalu_pps_hevc()
353 radeon_enc_reset(enc); in radeon_enc_nalu_pps_hevc()
354 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_nalu_pps_hevc()
355 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); in radeon_enc_nalu_pps_hevc()
356 radeon_enc_code_fixed_bits(enc, 0x4401, 16); in radeon_enc_nalu_pps_hevc()
357 radeon_enc_byte_align(enc); in radeon_enc_nalu_pps_hevc()
358 radeon_enc_set_emulation_prevention(enc, true); in radeon_enc_nalu_pps_hevc()
359 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps_hevc()
360 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps_hevc()
361 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
362 radeon_enc_code_fixed_bits(enc, 0x0, 4); in radeon_enc_nalu_pps_hevc()
363 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
364 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
365 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps_hevc()
366 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps_hevc()
367 radeon_enc_code_se(enc, 0x0); in radeon_enc_nalu_pps_hevc()
368 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1); in radeon_enc_nalu_pps_hevc()
369 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
370 if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE) in radeon_enc_nalu_pps_hevc()
371 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
373 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
374 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps_hevc()
376 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset); in radeon_enc_nalu_pps_hevc()
377 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset); in radeon_enc_nalu_pps_hevc()
378 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
379 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_pps_hevc()
380 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
381 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
382 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
383 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1); in radeon_enc_nalu_pps_hevc()
384 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
385 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
386 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1); in radeon_enc_nalu_pps_hevc()
388 if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) { in radeon_enc_nalu_pps_hevc()
389 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_enc_nalu_pps_hevc()
390 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2); in radeon_enc_nalu_pps_hevc()
393 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
394 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
395 radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2); in radeon_enc_nalu_pps_hevc()
396 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_pps_hevc()
398 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
400 radeon_enc_byte_align(enc); in radeon_enc_nalu_pps_hevc()
401 radeon_enc_flush_headers(enc); in radeon_enc_nalu_pps_hevc()
402 *size_in_bytes = (enc->bits_output + 7) / 8; in radeon_enc_nalu_pps_hevc()
406 static void radeon_enc_input_format(struct radeon_encoder *enc) in radeon_enc_input_format() argument
408 RADEON_ENC_BEGIN(enc->cmd.input_format); in radeon_enc_input_format()
409 if (enc->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) { in radeon_enc_input_format()
429 static void radeon_enc_output_format(struct radeon_encoder *enc) in radeon_enc_output_format() argument
431 RADEON_ENC_BEGIN(enc->cmd.output_format); in radeon_enc_output_format()
432 if (enc->base.profile == PIPE_VIDEO_PROFILE_HEVC_MAIN_10) { in radeon_enc_output_format()
446 static void radeon_enc_ctx(struct radeon_encoder *enc) in radeon_enc_ctx() argument
448 enc->enc_pic.ctx_buf.swizzle_mode = 0; in radeon_enc_ctx()
450 uint32_t aligned_width = enc->enc_pic.session_init.aligned_picture_width; in radeon_enc_ctx()
451 uint32_t aligned_height = enc->enc_pic.session_init.aligned_picture_height; in radeon_enc_ctx()
453 enc->enc_pic.ctx_buf.rec_luma_pitch = align(aligned_width, enc->alignment); in radeon_enc_ctx()
454 enc->enc_pic.ctx_buf.rec_chroma_pitch = align(aligned_width, enc->alignment); in radeon_enc_ctx()
456 int luma_size = enc->enc_pic.ctx_buf.rec_luma_pitch * align(aligned_height, enc->alignment); in radeon_enc_ctx()
457 if (enc->enc_pic.bit_depth_luma_minus8 == 2) in radeon_enc_ctx()
459 int chroma_size = align(luma_size / 2, enc->alignment); in radeon_enc_ctx()
462 enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2; in radeon_enc_ctx()
463 for (int i = 0; i < enc->enc_pic.ctx_buf.num_reconstructed_pictures; i++) { in radeon_enc_ctx()
464 enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset = offset; in radeon_enc_ctx()
466 enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset = offset; in radeon_enc_ctx()
470 RADEON_ENC_BEGIN(enc->cmd.ctx); in radeon_enc_ctx()
471 RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0); in radeon_enc_ctx()
472 RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode); in radeon_enc_ctx()
473 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch); in radeon_enc_ctx()
474 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch); in radeon_enc_ctx()
475 RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures); in radeon_enc_ctx()
477 for (int i = 0; i < enc->enc_pic.ctx_buf.num_reconstructed_pictures; i++) { in radeon_enc_ctx()
478 RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].luma_offset); in radeon_enc_ctx()
479 RADEON_ENC_CS(enc->enc_pic.ctx_buf.reconstructed_pictures[i].chroma_offset); in radeon_enc_ctx()
488 static void encode(struct radeon_encoder *enc) in encode() argument
490 enc->session_info(enc); in encode()
491 enc->total_task_size = 0; in encode()
492 enc->task_info(enc, enc->need_feedback); in encode()
494 enc->encode_headers(enc); in encode()
495 enc->ctx(enc); in encode()
496 enc->bitstream(enc); in encode()
497 enc->feedback(enc); in encode()
498 enc->intra_refresh(enc); in encode()
499 enc->input_format(enc); in encode()
500 enc->output_format(enc); in encode()
502 enc->op_preset(enc); in encode()
503 enc->op_enc(enc); in encode()
504 *enc->p_task_size = (enc->total_task_size); in encode()
507 void radeon_enc_2_0_init(struct radeon_encoder *enc) in radeon_enc_2_0_init() argument
509 radeon_enc_1_2_init(enc); in radeon_enc_2_0_init()
510 enc->encode = encode; in radeon_enc_2_0_init()
511 enc->ctx = radeon_enc_ctx; in radeon_enc_2_0_init()
512 enc->quality_params = radeon_enc_quality_params; in radeon_enc_2_0_init()
513 enc->input_format = radeon_enc_input_format; in radeon_enc_2_0_init()
514 enc->output_format = radeon_enc_output_format; in radeon_enc_2_0_init()
516 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) { in radeon_enc_2_0_init()
517 enc->deblocking_filter = radeon_enc_loop_filter_hevc; in radeon_enc_2_0_init()
518 enc->nalu_sps = radeon_enc_nalu_sps_hevc; in radeon_enc_2_0_init()
519 enc->nalu_pps = radeon_enc_nalu_pps_hevc; in radeon_enc_2_0_init()
520 enc->slice_header = radeon_enc_slice_header_hevc; in radeon_enc_2_0_init()
521 enc->op_preset = radeon_enc_op_balance; in radeon_enc_2_0_init()
524 enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO; in radeon_enc_2_0_init()
525 enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO; in radeon_enc_2_0_init()
526 enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT; in radeon_enc_2_0_init()
527 enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL; in radeon_enc_2_0_init()
528 enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT; in radeon_enc_2_0_init()
529 enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT; in radeon_enc_2_0_init()
530 enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT; in radeon_enc_2_0_init()
531 enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE; in radeon_enc_2_0_init()
532 enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS; in radeon_enc_2_0_init()
533 enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU; in radeon_enc_2_0_init()
534 enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER; in radeon_enc_2_0_init()
535 enc->cmd.input_format = RENCODE_IB_PARAM_INPUT_FORMAT; in radeon_enc_2_0_init()
536 enc->cmd.output_format = RENCODE_IB_PARAM_OUTPUT_FORMAT; in radeon_enc_2_0_init()
537 enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS; in radeon_enc_2_0_init()
538 enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH; in radeon_enc_2_0_init()
539 enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER; in radeon_enc_2_0_init()
540 enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER; in radeon_enc_2_0_init()
541 enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER; in radeon_enc_2_0_init()
542 enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL; in radeon_enc_2_0_init()
543 enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC; in radeon_enc_2_0_init()
544 enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_LOOP_FILTER; in radeon_enc_2_0_init()
545 enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL; in radeon_enc_2_0_init()
546 enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC; in radeon_enc_2_0_init()
547 enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS; in radeon_enc_2_0_init()
548 enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER; in radeon_enc_2_0_init()
550 enc->enc_pic.session_info.interface_version = in radeon_enc_2_0_init()