212                          uint64_t ShiftImm, bool SetFlags = false,
216                          uint64_t ShiftImm, bool SetFlags = false,
243                        AArch64_AM::ShiftExtendType ShiftType, uint64_t ShiftImm,
250                             unsigned RHSReg, uint64_t ShiftImm);
1325   unsigned ShiftImm;  in emitAddSub_ri()  local
1327     ShiftImm = 0;  in emitAddSub_ri()
1329     ShiftImm = 12;  in emitAddSub_ri()
1358       .addImm(getShifterImm(AArch64_AM::LSL, ShiftImm));  in emitAddSub_ri()
1365                                         uint64_t ShiftImm, bool SetFlags,  in emitAddSub_rs()  argument
1375   if (ShiftImm >= RetVT.getSizeInBits())  in emitAddSub_rs()
1400       .addImm(getShifterImm(ShiftType, ShiftImm));  in emitAddSub_rs()
1407                                         uint64_t ShiftImm, bool SetFlags,  in emitAddSub_rx()  argument
1416   if (ShiftImm >= 4)  in emitAddSub_rx()
1444       .addImm(getArithExtendImm(ExtType, ShiftImm));  in emitAddSub_rx()
1558                                       uint64_t ShiftImm, bool WantResult) {  in emitSubs_rs()  argument
1560                        ShiftImm, /*SetFlags=*/true, WantResult);  in emitSubs_rs()
1688                                            uint64_t ShiftImm) {  in emitLogicalOp_rs()  argument
1698   if (ShiftImm >= RetVT.getSizeInBits())  in emitLogicalOp_rs()
1720                        AArch64_AM::getShifterImm(AArch64_AM::LSL, ShiftImm));  in emitLogicalOp_rs()