61 static void radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer,
68 static void radv_set_rt_stack_size(struct radv_cmd_buffer *cmd_buffer, uint32_t size);
129 radv_bind_dynamic_state(struct radv_cmd_buffer *cmd_buffer, const struct radv_dynamic_state *src)  in radv_bind_dynamic_state()  argument
131    struct radv_dynamic_state *dest = &cmd_buffer->state.dynamic;  in radv_bind_dynamic_state()
353    cmd_buffer->state.dirty |= dest_mask;  in radv_bind_dynamic_state()
357 radv_cmd_buffer_uses_mec(struct radv_cmd_buffer *cmd_buffer)  in radv_cmd_buffer_uses_mec()  argument
359    return cmd_buffer->qf == RADV_QUEUE_COMPUTE &&  in radv_cmd_buffer_uses_mec()
360           cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;  in radv_cmd_buffer_uses_mec()
380 radv_emit_write_data_packet(struct radv_cmd_buffer *cmd_buffer, unsigned engine_sel, uint64_t va,  in radv_emit_write_data_packet()  argument
383    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_emit_write_data_packet()
385    radeon_check_space(cmd_buffer->device->ws, cs, 4 + count);  in radv_emit_write_data_packet()
395 radv_emit_clear_data(struct radv_cmd_buffer *cmd_buffer, unsigned engine_sel, uint64_t va,  in radv_emit_clear_data()  argument
400    radv_emit_write_data_packet(cmd_buffer, engine_sel, va, size / 4, zeroes);  in radv_emit_clear_data()
404 radv_destroy_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)  in radv_destroy_cmd_buffer()  argument
406    list_del(&cmd_buffer->pool_link);  in radv_destroy_cmd_buffer()
408    list_for_each_entry_safe(struct radv_cmd_buffer_upload, up, &cmd_buffer->upload.list, list)  in radv_destroy_cmd_buffer()
410       cmd_buffer->device->ws->buffer_destroy(cmd_buffer->device->ws, up->upload_bo);  in radv_destroy_cmd_buffer()
415    if (cmd_buffer->upload.upload_bo)  in radv_destroy_cmd_buffer()
416       cmd_buffer->device->ws->buffer_destroy(cmd_buffer->device->ws, cmd_buffer->upload.upload_bo);  in radv_destroy_cmd_buffer()
418    if (cmd_buffer->state.own_render_pass) {  in radv_destroy_cmd_buffer()
419       radv_DestroyRenderPass(radv_device_to_handle(cmd_buffer->device),  in radv_destroy_cmd_buffer()
420                              radv_render_pass_to_handle(cmd_buffer->state.pass), NULL);  in radv_destroy_cmd_buffer()
421       cmd_buffer->state.own_render_pass = false;  in radv_destroy_cmd_buffer()
424    if (cmd_buffer->cs)  in radv_destroy_cmd_buffer()
425       cmd_buffer->device->ws->cs_destroy(cmd_buffer->cs);  in radv_destroy_cmd_buffer()
428       struct radv_descriptor_set_header *set = &cmd_buffer->descriptors[i].push_set.set;  in radv_destroy_cmd_buffer()
431          radv_descriptor_set_layout_unref(cmd_buffer->device, set->layout);  in radv_destroy_cmd_buffer()
435    vk_object_base_finish(&cmd_buffer->meta_push_descriptors.base);  in radv_destroy_cmd_buffer()
437    vk_command_buffer_finish(&cmd_buffer->vk);  in radv_destroy_cmd_buffer()
438    vk_free(&cmd_buffer->pool->vk.alloc, cmd_buffer);  in radv_destroy_cmd_buffer()
445    struct radv_cmd_buffer *cmd_buffer;  in radv_create_cmd_buffer()  local
447    cmd_buffer = vk_zalloc(&pool->vk.alloc, sizeof(*cmd_buffer), 8,  in radv_create_cmd_buffer()
449    if (cmd_buffer == NULL)  in radv_create_cmd_buffer()
453       vk_command_buffer_init(&cmd_buffer->vk, &pool->vk, level);  in radv_create_cmd_buffer()
455       vk_free(&cmd_buffer->pool->vk.alloc, cmd_buffer);  in radv_create_cmd_buffer()
459    cmd_buffer->device = device;  in radv_create_cmd_buffer()
460    cmd_buffer->pool = pool;  in radv_create_cmd_buffer()
462    list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);  in radv_create_cmd_buffer()
463    cmd_buffer->qf = vk_queue_to_radv(device->physical_device, pool->vk.queue_family_index);  in radv_create_cmd_buffer()
465    ring = radv_queue_family_to_ring(device->physical_device, cmd_buffer->qf);  in radv_create_cmd_buffer()
467    cmd_buffer->cs = device->ws->cs_create(device->ws, ring);  in radv_create_cmd_buffer()
468    if (!cmd_buffer->cs) {  in radv_create_cmd_buffer()
469       radv_destroy_cmd_buffer(cmd_buffer);  in radv_create_cmd_buffer()
473    vk_object_base_init(&device->vk, &cmd_buffer->meta_push_descriptors.base,  in radv_create_cmd_buffer()
477       vk_object_base_init(&device->vk, &cmd_buffer->descriptors[i].push_set.set.base,  in radv_create_cmd_buffer()
480    *pCommandBuffer = radv_cmd_buffer_to_handle(cmd_buffer);  in radv_create_cmd_buffer()
482    list_inithead(&cmd_buffer->upload.list);  in radv_create_cmd_buffer()
488 radv_reset_cmd_buffer(struct radv_cmd_buffer *cmd_buffer)  in radv_reset_cmd_buffer()  argument
490    vk_command_buffer_reset(&cmd_buffer->vk);  in radv_reset_cmd_buffer()
492    cmd_buffer->device->ws->cs_reset(cmd_buffer->cs);  in radv_reset_cmd_buffer()
494    list_for_each_entry_safe(struct radv_cmd_buffer_upload, up, &cmd_buffer->upload.list, list)  in radv_reset_cmd_buffer()
496       cmd_buffer->device->ws->buffer_destroy(cmd_buffer->device->ws, up->upload_bo);  in radv_reset_cmd_buffer()
501    if (cmd_buffer->state.own_render_pass) {  in radv_reset_cmd_buffer()
502       radv_DestroyRenderPass(radv_device_to_handle(cmd_buffer->device),  in radv_reset_cmd_buffer()
503                              radv_render_pass_to_handle(cmd_buffer->state.pass), NULL);  in radv_reset_cmd_buffer()
504       cmd_buffer->state.own_render_pass = false;  in radv_reset_cmd_buffer()
507    cmd_buffer->push_constant_stages = 0;  in radv_reset_cmd_buffer()
508    cmd_buffer->scratch_size_per_wave_needed = 0;  in radv_reset_cmd_buffer()
509    cmd_buffer->scratch_waves_wanted = 0;  in radv_reset_cmd_buffer()
510    cmd_buffer->compute_scratch_size_per_wave_needed = 0;  in radv_reset_cmd_buffer()
511    cmd_buffer->compute_scratch_waves_wanted = 0;  in radv_reset_cmd_buffer()
512    cmd_buffer->esgs_ring_size_needed = 0;  in radv_reset_cmd_buffer()
513    cmd_buffer->gsvs_ring_size_needed = 0;  in radv_reset_cmd_buffer()
514    cmd_buffer->tess_rings_needed = false;  in radv_reset_cmd_buffer()
515    cmd_buffer->gds_needed = false;  in radv_reset_cmd_buffer()
516    cmd_buffer->gds_oa_needed = false;  in radv_reset_cmd_buffer()
517    cmd_buffer->sample_positions_needed = false;  in radv_reset_cmd_buffer()
519    if (cmd_buffer->upload.upload_bo)  in radv_reset_cmd_buffer()
520       radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, cmd_buffer->upload.upload_bo);  in radv_reset_cmd_buffer()
521    cmd_buffer->upload.offset = 0;  in radv_reset_cmd_buffer()
523    cmd_buffer->record_result = VK_SUCCESS;  in radv_reset_cmd_buffer()
525    memset(cmd_buffer->vertex_bindings, 0, sizeof(cmd_buffer->vertex_bindings));  in radv_reset_cmd_buffer()
528       cmd_buffer->descriptors[i].dirty = 0;  in radv_reset_cmd_buffer()
529       cmd_buffer->descriptors[i].valid = 0;  in radv_reset_cmd_buffer()
530       cmd_buffer->descriptors[i].push_dirty = false;  in radv_reset_cmd_buffer()
533    if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&  in radv_reset_cmd_buffer()
534        cmd_buffer->qf == RADV_QUEUE_GENERAL) {  in radv_reset_cmd_buffer()
535       unsigned num_db = cmd_buffer->device->physical_device->rad_info.max_render_backends;  in radv_reset_cmd_buffer()
539       radv_cmd_buffer_upload_alloc(cmd_buffer, 8, &fence_offset, &fence_ptr);  in radv_reset_cmd_buffer()
542       cmd_buffer->gfx9_fence_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);  in radv_reset_cmd_buffer()
543       cmd_buffer->gfx9_fence_va += fence_offset;  in radv_reset_cmd_buffer()
545       radv_emit_clear_data(cmd_buffer, V_370_PFP, cmd_buffer->gfx9_fence_va, 8);  in radv_reset_cmd_buffer()
547       if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {  in radv_reset_cmd_buffer()
549          radv_cmd_buffer_upload_alloc(cmd_buffer, 16 * num_db, &eop_bug_offset, &fence_ptr);  in radv_reset_cmd_buffer()
551          cmd_buffer->gfx9_eop_bug_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);  in radv_reset_cmd_buffer()
552          cmd_buffer->gfx9_eop_bug_va += eop_bug_offset;  in radv_reset_cmd_buffer()
554          radv_emit_clear_data(cmd_buffer, V_370_PFP, cmd_buffer->gfx9_eop_bug_va, 16 * num_db);  in radv_reset_cmd_buffer()
558    cmd_buffer->status = RADV_CMD_BUFFER_STATUS_INITIAL;  in radv_reset_cmd_buffer()
560    return cmd_buffer->record_result;  in radv_reset_cmd_buffer()
564 radv_cmd_buffer_resize_upload_buf(struct radv_cmd_buffer *cmd_buffer, uint64_t min_needed)  in radv_cmd_buffer_resize_upload_buf()  argument
569    struct radv_device *device = cmd_buffer->device;  in radv_cmd_buffer_resize_upload_buf()
572    new_size = MAX2(new_size, 2 * cmd_buffer->upload.size);  in radv_cmd_buffer_resize_upload_buf()
581       cmd_buffer->record_result = result;  in radv_cmd_buffer_resize_upload_buf()
585    radv_cs_add_buffer(device->ws, cmd_buffer->cs, bo);  in radv_cmd_buffer_resize_upload_buf()
586    if (cmd_buffer->upload.upload_bo) {  in radv_cmd_buffer_resize_upload_buf()
590          cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;  in radv_cmd_buffer_resize_upload_buf()
595       memcpy(upload, &cmd_buffer->upload, sizeof(*upload));  in radv_cmd_buffer_resize_upload_buf()
596       list_add(&upload->list, &cmd_buffer->upload.list);  in radv_cmd_buffer_resize_upload_buf()
599    cmd_buffer->upload.upload_bo = bo;  in radv_cmd_buffer_resize_upload_buf()
600    cmd_buffer->upload.size = new_size;  in radv_cmd_buffer_resize_upload_buf()
601    cmd_buffer->upload.offset = 0;  in radv_cmd_buffer_resize_upload_buf()
602    cmd_buffer->upload.map = device->ws->buffer_map(cmd_buffer->upload.upload_bo);  in radv_cmd_buffer_resize_upload_buf()
604    if (!cmd_buffer->upload.map) {  in radv_cmd_buffer_resize_upload_buf()
605       cmd_buffer->record_result = VK_ERROR_OUT_OF_DEVICE_MEMORY;  in radv_cmd_buffer_resize_upload_buf()
613 radv_cmd_buffer_upload_alloc(struct radv_cmd_buffer *cmd_buffer, unsigned size,  in radv_cmd_buffer_upload_alloc()  argument
618    struct radeon_info *rad_info = &cmd_buffer->device->physical_device->rad_info;  in radv_cmd_buffer_upload_alloc()
623    unsigned offset = cmd_buffer->upload.offset;  in radv_cmd_buffer_upload_alloc()
629    if (offset + size > cmd_buffer->upload.size) {  in radv_cmd_buffer_upload_alloc()
630       if (!radv_cmd_buffer_resize_upload_buf(cmd_buffer, size))  in radv_cmd_buffer_upload_alloc()
636    *ptr = cmd_buffer->upload.map + offset;  in radv_cmd_buffer_upload_alloc()
638    cmd_buffer->upload.offset = offset + size;  in radv_cmd_buffer_upload_alloc()
643 radv_cmd_buffer_upload_data(struct radv_cmd_buffer *cmd_buffer, unsigned size, const void *data,  in radv_cmd_buffer_upload_data()  argument
648    if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, out_offset, (void **)&ptr))  in radv_cmd_buffer_upload_data()
657 radv_cmd_buffer_trace_emit(struct radv_cmd_buffer *cmd_buffer)  in radv_cmd_buffer_trace_emit()  argument
659    struct radv_device *device = cmd_buffer->device;  in radv_cmd_buffer_trace_emit()
660    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_cmd_buffer_trace_emit()
664    if (cmd_buffer->vk.level == VK_COMMAND_BUFFER_LEVEL_SECONDARY)  in radv_cmd_buffer_trace_emit()
667    ++cmd_buffer->state.trace_id;  in radv_cmd_buffer_trace_emit()
668    radv_emit_write_data_packet(cmd_buffer, V_370_ME, va, 1, &cmd_buffer->state.trace_id);  in radv_cmd_buffer_trace_emit()
670    radeon_check_space(cmd_buffer->device->ws, cs, 2);  in radv_cmd_buffer_trace_emit()
673    radeon_emit(cs, AC_ENCODE_TRACE_POINT(cmd_buffer->state.trace_id));  in radv_cmd_buffer_trace_emit()
677 radv_cmd_buffer_after_draw(struct radv_cmd_buffer *cmd_buffer, enum radv_cmd_flush_bits flags)  in radv_cmd_buffer_after_draw()  argument
679    if (unlikely(cmd_buffer->device->thread_trace.bo)) {  in radv_cmd_buffer_after_draw()
680       radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));  in radv_cmd_buffer_after_draw()
681       radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_THREAD_TRACE_MARKER) | EVENT_INDEX(0));  in radv_cmd_buffer_after_draw()
684    if (cmd_buffer->device->instance->debug_flags & RADV_DEBUG_SYNC_SHADERS) {  in radv_cmd_buffer_after_draw()
688       radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4);  in radv_cmd_buffer_after_draw()
691       si_cs_emit_cache_flush(cmd_buffer->cs,  in radv_cmd_buffer_after_draw()
692                              cmd_buffer->device->physical_device->rad_info.chip_class,  in radv_cmd_buffer_after_draw()
693                              &cmd_buffer->gfx9_fence_idx, cmd_buffer->gfx9_fence_va,  in radv_cmd_buffer_after_draw()
694                              radv_cmd_buffer_uses_mec(cmd_buffer), flags, &sqtt_flush_bits,  in radv_cmd_buffer_after_draw()
695                              cmd_buffer->gfx9_eop_bug_va);  in radv_cmd_buffer_after_draw()
698    if (unlikely(cmd_buffer->device->trace_bo))  in radv_cmd_buffer_after_draw()
699       radv_cmd_buffer_trace_emit(cmd_buffer);  in radv_cmd_buffer_after_draw()
703 radv_save_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_pipeline *pipeline)  in radv_save_pipeline()  argument
705    struct radv_device *device = cmd_buffer->device;  in radv_save_pipeline()
712    ring = radv_queue_family_to_ring(device->physical_device, cmd_buffer->qf);  in radv_save_pipeline()
729    radv_emit_write_data_packet(cmd_buffer, V_370_ME, va, 2, data);  in radv_save_pipeline()
733 radv_save_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, uint64_t vb_ptr)  in radv_save_vertex_descriptors()  argument
735    struct radv_device *device = cmd_buffer->device;  in radv_save_vertex_descriptors()
745    radv_emit_write_data_packet(cmd_buffer, V_370_ME, va, 2, data);  in radv_save_vertex_descriptors()
749 radv_save_vs_prolog(struct radv_cmd_buffer *cmd_buffer, const struct radv_shader_prolog *prolog)  in radv_save_vs_prolog()  argument
751    struct radv_device *device = cmd_buffer->device;  in radv_save_vs_prolog()
762    radv_emit_write_data_packet(cmd_buffer, V_370_ME, va, 2, data);  in radv_save_vs_prolog()
766 radv_set_descriptor_set(struct radv_cmd_buffer *cmd_buffer, VkPipelineBindPoint bind_point,  in radv_set_descriptor_set()  argument
770       radv_get_descriptors_state(cmd_buffer, bind_point);  in radv_set_descriptor_set()
779 radv_save_descriptors(struct radv_cmd_buffer *cmd_buffer, VkPipelineBindPoint bind_point)  in radv_save_descriptors()  argument
782       radv_get_descriptors_state(cmd_buffer, bind_point);  in radv_save_descriptors()
783    struct radv_device *device = cmd_buffer->device;  in radv_save_descriptors()
795    radv_emit_write_data_packet(cmd_buffer, V_370_ME, va, MAX_SETS * 2, data);  in radv_save_descriptors()
806 radv_emit_userdata_address(struct radv_cmd_buffer *cmd_buffer, struct radv_pipeline *pipeline,  in radv_emit_userdata_address()  argument
816    radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, va,  in radv_emit_userdata_address()
821 radv_emit_descriptor_pointers(struct radv_cmd_buffer *cmd_buffer, struct radv_pipeline *pipeline,  in radv_emit_descriptor_pointers()  argument
825    struct radv_device *device = cmd_buffer->device;  in radv_emit_descriptor_pointers()
826    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_emit_descriptor_pointers()
908 radv_compute_centroid_priority(struct radv_cmd_buffer *cmd_buffer, VkOffset2D *sample_locs,  in radv_compute_centroid_priority()  argument
946 radv_emit_sample_locations(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_sample_locations()  argument
948    struct radv_sample_locations_state *sample_location = &cmd_buffer->state.dynamic.sample_location;  in radv_emit_sample_locations()
950    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_emit_sample_locations()
956    if (!cmd_buffer->state.dynamic.sample_location.count)  in radv_emit_sample_locations()
971    centroid_priority = radv_compute_centroid_priority(cmd_buffer, sample_locs[0], num_samples);  in radv_emit_sample_locations()
1024    cmd_buffer->state.context_roll_without_scissor_emitted = true;  in radv_emit_sample_locations()
1028 radv_emit_inline_push_consts(struct radv_cmd_buffer *cmd_buffer, struct radv_pipeline *pipeline,  in radv_emit_inline_push_consts()  argument
1036    radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 2 + loc->num_sgprs);  in radv_emit_inline_push_consts()
1038    radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, loc->num_sgprs);  in radv_emit_inline_push_consts()
1039    radeon_emit_array(cmd_buffer->cs, values, loc->num_sgprs);  in radv_emit_inline_push_consts()
1043 radv_update_multisample_state(struct radv_cmd_buffer *cmd_buffer, struct radv_pipeline *pipeline)  in radv_update_multisample_state()  argument
1046    struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;  in radv_update_multisample_state()
1049       cmd_buffer->sample_positions_needed = true;  in radv_update_multisample_state()
1054    radv_emit_default_sample_locations(cmd_buffer->cs, num_samples);  in radv_update_multisample_state()
1056    cmd_buffer->state.context_roll_without_scissor_emitted = true;  in radv_update_multisample_state()
1060 radv_update_binning_state(struct radv_cmd_buffer *cmd_buffer, struct radv_pipeline *pipeline)  in radv_update_binning_state()  argument
1062    const struct radv_pipeline *old_pipeline = cmd_buffer->state.emitted_pipeline;  in radv_update_binning_state()
1073    if (cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA12 ||  in radv_update_binning_state()
1074        cmd_buffer->device->physical_device->rad_info.family == CHIP_VEGA20 ||  in radv_update_binning_state()
1075        cmd_buffer->device->physical_device->rad_info.family == CHIP_RAVEN2 ||  in radv_update_binning_state()
1076        cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {  in radv_update_binning_state()
1082    radeon_set_context_reg(cmd_buffer->cs, R_028C44_PA_SC_BINNER_CNTL_0,  in radv_update_binning_state()
1086    cmd_buffer->state.context_roll_without_scissor_emitted = true;  in radv_update_binning_state()
1090 radv_emit_shader_prefetch(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *shader)  in radv_emit_shader_prefetch()  argument
1099    si_cp_dma_prefetch(cmd_buffer, va, shader->code_size);  in radv_emit_shader_prefetch()
1103 radv_emit_prefetch_L2(struct radv_cmd_buffer *cmd_buffer, struct radv_pipeline *pipeline,  in radv_emit_prefetch_L2()  argument
1106    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_emit_prefetch_L2()
1114       radv_emit_shader_prefetch(cmd_buffer, pipeline->shaders[MESA_SHADER_VERTEX]);  in radv_emit_prefetch_L2()
1117       radv_emit_shader_prefetch(cmd_buffer, pipeline->shaders[MESA_SHADER_MESH]);  in radv_emit_prefetch_L2()
1120       si_cp_dma_prefetch(cmd_buffer, state->vb_va, pipeline->vb_desc_alloc_size);  in radv_emit_prefetch_L2()
1123       radv_emit_shader_prefetch(cmd_buffer, pipeline->shaders[MESA_SHADER_TESS_CTRL]);  in radv_emit_prefetch_L2()
1126       radv_emit_shader_prefetch(cmd_buffer, pipeline->shaders[MESA_SHADER_TESS_EVAL]);  in radv_emit_prefetch_L2()
1129       radv_emit_shader_prefetch(cmd_buffer, pipeline->shaders[MESA_SHADER_GEOMETRY]);  in radv_emit_prefetch_L2()
1131          radv_emit_shader_prefetch(cmd_buffer, pipeline->gs_copy_shader);  in radv_emit_prefetch_L2()
1135       radv_emit_shader_prefetch(cmd_buffer, pipeline->shaders[MESA_SHADER_FRAGMENT]);  in radv_emit_prefetch_L2()
1141 radv_emit_rbplus_state(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_rbplus_state()  argument
1143    if (!cmd_buffer->device->physical_device->rad_info.rbplus_allowed)  in radv_emit_rbplus_state()
1146    struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;  in radv_emit_rbplus_state()
1147    const struct radv_subpass *subpass = cmd_buffer->state.subpass;  in radv_emit_rbplus_state()
1164       if (cmd_buffer->state.attachments) {  in radv_emit_rbplus_state()
1165          struct radv_color_buffer_info *cb = &cmd_buffer->state.attachments[idx].cb;  in radv_emit_rbplus_state()
1171          VkFormat fmt = cmd_buffer->state.pass->attachments[idx].format;  in radv_emit_rbplus_state()
1285    if (sx_ps_downconvert == cmd_buffer->state.last_sx_ps_downconvert &&  in radv_emit_rbplus_state()
1286        sx_blend_opt_epsilon == cmd_buffer->state.last_sx_blend_opt_epsilon &&  in radv_emit_rbplus_state()
1287        sx_blend_opt_control == cmd_buffer->state.last_sx_blend_opt_control)  in radv_emit_rbplus_state()
1290    radeon_set_context_reg_seq(cmd_buffer->cs, R_028754_SX_PS_DOWNCONVERT, 3);  in radv_emit_rbplus_state()
1291    radeon_emit(cmd_buffer->cs, sx_ps_downconvert);  in radv_emit_rbplus_state()
1292    radeon_emit(cmd_buffer->cs, sx_blend_opt_epsilon);  in radv_emit_rbplus_state()
1293    radeon_emit(cmd_buffer->cs, sx_blend_opt_control);  in radv_emit_rbplus_state()
1295    cmd_buffer->state.context_roll_without_scissor_emitted = true;  in radv_emit_rbplus_state()
1297    cmd_buffer->state.last_sx_ps_downconvert = sx_ps_downconvert;  in radv_emit_rbplus_state()
1298    cmd_buffer->state.last_sx_blend_opt_epsilon = sx_blend_opt_epsilon;  in radv_emit_rbplus_state()
1299    cmd_buffer->state.last_sx_blend_opt_control = sx_blend_opt_control;  in radv_emit_rbplus_state()
1303 radv_emit_batch_break_on_new_ps(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_batch_break_on_new_ps()  argument
1305    if (!cmd_buffer->device->pbb_allowed)  in radv_emit_batch_break_on_new_ps()
1309       radv_get_binning_settings(cmd_buffer->device->physical_device);  in radv_emit_batch_break_on_new_ps()
1311       (!cmd_buffer->state.emitted_pipeline ||  in radv_emit_batch_break_on_new_ps()
1312        cmd_buffer->state.emitted_pipeline->shaders[MESA_SHADER_FRAGMENT] !=  in radv_emit_batch_break_on_new_ps()
1313           cmd_buffer->state.pipeline->shaders[MESA_SHADER_FRAGMENT]) &&  in radv_emit_batch_break_on_new_ps()
1316       (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE) &&  in radv_emit_batch_break_on_new_ps()
1322    radeon_emit(cmd_buffer->cs, PKT3(PKT3_EVENT_WRITE, 0, 0));  in radv_emit_batch_break_on_new_ps()
1323    radeon_emit(cmd_buffer->cs, EVENT_TYPE(V_028A90_BREAK_BATCH) | EVENT_INDEX(0));  in radv_emit_batch_break_on_new_ps()
1327 radv_emit_graphics_pipeline(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_graphics_pipeline()  argument
1329    struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;  in radv_emit_graphics_pipeline()
1331    if (cmd_buffer->state.emitted_pipeline == pipeline)  in radv_emit_graphics_pipeline()
1334    radv_update_multisample_state(cmd_buffer, pipeline);  in radv_emit_graphics_pipeline()
1335    radv_update_binning_state(cmd_buffer, pipeline);  in radv_emit_graphics_pipeline()
1337    cmd_buffer->scratch_size_per_wave_needed =  in radv_emit_graphics_pipeline()
1338       MAX2(cmd_buffer->scratch_size_per_wave_needed, pipeline->scratch_bytes_per_wave);  in radv_emit_graphics_pipeline()
1339    cmd_buffer->scratch_waves_wanted = MAX2(cmd_buffer->scratch_waves_wanted, pipeline->max_waves);  in radv_emit_graphics_pipeline()
1341    if (!cmd_buffer->state.emitted_pipeline ||  in radv_emit_graphics_pipeline()
1342        cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband !=  in radv_emit_graphics_pipeline()
1344       cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_SCISSOR;  in radv_emit_graphics_pipeline()
1346    if (!cmd_buffer->state.emitted_pipeline ||  in radv_emit_graphics_pipeline()
1347        cmd_buffer->state.emitted_pipeline->graphics.pa_su_sc_mode_cntl !=  in radv_emit_graphics_pipeline()
1349       cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_CULL_MODE |  in radv_emit_graphics_pipeline()
1353    if (!cmd_buffer->state.emitted_pipeline ||  in radv_emit_graphics_pipeline()
1354        cmd_buffer->state.emitted_pipeline->graphics.pa_cl_clip_cntl !=  in radv_emit_graphics_pipeline()
1356       cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_RASTERIZER_DISCARD_ENABLE;  in radv_emit_graphics_pipeline()
1358    if (!cmd_buffer->state.emitted_pipeline ||  in radv_emit_graphics_pipeline()
1359        cmd_buffer->state.emitted_pipeline->graphics.cb_color_control !=  in radv_emit_graphics_pipeline()
1361       cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LOGIC_OP;  in radv_emit_graphics_pipeline()
1363    if (!cmd_buffer->state.emitted_pipeline)  in radv_emit_graphics_pipeline()
1364       cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_PRIMITIVE_TOPOLOGY |  in radv_emit_graphics_pipeline()
1369    if (!cmd_buffer->state.emitted_pipeline ||  in radv_emit_graphics_pipeline()
1370        cmd_buffer->state.emitted_pipeline->graphics.db_depth_control !=  in radv_emit_graphics_pipeline()
1372       cmd_buffer->state.dirty |=  in radv_emit_graphics_pipeline()
1377    if (!cmd_buffer->state.emitted_pipeline)  in radv_emit_graphics_pipeline()
1378       cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_OP;  in radv_emit_graphics_pipeline()
1380    if (!cmd_buffer->state.emitted_pipeline ||  in radv_emit_graphics_pipeline()
1381        cmd_buffer->state.emitted_pipeline->graphics.cb_target_mask !=  in radv_emit_graphics_pipeline()
1383       cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_COLOR_WRITE_ENABLE;  in radv_emit_graphics_pipeline()
1386    radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);  in radv_emit_graphics_pipeline()
1390        !cmd_buffer->state.last_nggc_settings) {  in radv_emit_graphics_pipeline()
1396       radeon_set_sh_reg(cmd_buffer->cs, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,  in radv_emit_graphics_pipeline()
1401    if (!cmd_buffer->state.emitted_pipeline ||  in radv_emit_graphics_pipeline()
1402        cmd_buffer->state.emitted_pipeline->ctx_cs.cdw != pipeline->ctx_cs.cdw ||  in radv_emit_graphics_pipeline()
1403        cmd_buffer->state.emitted_pipeline->ctx_cs_hash != pipeline->ctx_cs_hash ||  in radv_emit_graphics_pipeline()
1404        memcmp(cmd_buffer->state.emitted_pipeline->ctx_cs.buf, pipeline->ctx_cs.buf,  in radv_emit_graphics_pipeline()
1406       radeon_emit_array(cmd_buffer->cs, pipeline->ctx_cs.buf, pipeline->ctx_cs.cdw);  in radv_emit_graphics_pipeline()
1407       cmd_buffer->state.context_roll_without_scissor_emitted = true;  in radv_emit_graphics_pipeline()
1410    radv_emit_batch_break_on_new_ps(cmd_buffer);  in radv_emit_graphics_pipeline()
1412    radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->slab->alloc->arena->bo);  in radv_emit_graphics_pipeline()
1414    if (unlikely(cmd_buffer->device->trace_bo))  in radv_emit_graphics_pipeline()
1415       radv_save_pipeline(cmd_buffer, pipeline);  in radv_emit_graphics_pipeline()
1417    cmd_buffer->state.emitted_pipeline = pipeline;  in radv_emit_graphics_pipeline()
1419    cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_PIPELINE;  in radv_emit_graphics_pipeline()
1423 radv_emit_viewport(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_viewport()  argument
1425    bool negative_one_to_one = cmd_buffer->state.pipeline->graphics.negative_one_to_one;  in radv_emit_viewport()
1426    const struct radv_viewport_state *viewport = &cmd_buffer->state.dynamic.viewport;  in radv_emit_viewport()
1431    radeon_set_context_reg_seq(cmd_buffer->cs, R_02843C_PA_CL_VPORT_XSCALE, count * 6);  in radv_emit_viewport()
1434       radeon_emit(cmd_buffer->cs, fui(viewport->xform[i].scale[0]));  in radv_emit_viewport()
1435       radeon_emit(cmd_buffer->cs, fui(viewport->xform[i].translate[0]));  in radv_emit_viewport()
1436       radeon_emit(cmd_buffer->cs, fui(viewport->xform[i].scale[1]));  in radv_emit_viewport()
1437       radeon_emit(cmd_buffer->cs, fui(viewport->xform[i].translate[1]));  in radv_emit_viewport()
1448       radeon_emit(cmd_buffer->cs, fui(scale_z));  in radv_emit_viewport()
1449       radeon_emit(cmd_buffer->cs, fui(translate_z));  in radv_emit_viewport()
1452    radeon_set_context_reg_seq(cmd_buffer->cs, R_0282D0_PA_SC_VPORT_ZMIN_0, count * 2);  in radv_emit_viewport()
1456       radeon_emit(cmd_buffer->cs, fui(zmin));  in radv_emit_viewport()
1457       radeon_emit(cmd_buffer->cs, fui(zmax));  in radv_emit_viewport()
1462 radv_emit_scissor(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_scissor()  argument
1464    uint32_t count = cmd_buffer->state.dynamic.scissor.count;  in radv_emit_scissor()
1466    si_write_scissors(cmd_buffer->cs, 0, count, cmd_buffer->state.dynamic.scissor.scissors,  in radv_emit_scissor()
1467                      cmd_buffer->state.dynamic.viewport.viewports,  in radv_emit_scissor()
1468                      cmd_buffer->state.emitted_pipeline->graphics.can_use_guardband);  in radv_emit_scissor()
1470    cmd_buffer->state.context_roll_without_scissor_emitted = false;  in radv_emit_scissor()
1474 radv_emit_discard_rectangle(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_discard_rectangle()  argument
1476    if (!cmd_buffer->state.dynamic.discard_rectangle.count)  in radv_emit_discard_rectangle()
1479    radeon_set_context_reg_seq(cmd_buffer->cs, R_028210_PA_SC_CLIPRECT_0_TL,  in radv_emit_discard_rectangle()
1480                               cmd_buffer->state.dynamic.discard_rectangle.count * 2);  in radv_emit_discard_rectangle()
1481    for (unsigned i = 0; i < cmd_buffer->state.dynamic.discard_rectangle.count; ++i) {  in radv_emit_discard_rectangle()
1482       VkRect2D rect = cmd_buffer->state.dynamic.discard_rectangle.rectangles[i];  in radv_emit_discard_rectangle()
1483       radeon_emit(cmd_buffer->cs, S_028210_TL_X(rect.offset.x) | S_028210_TL_Y(rect.offset.y));  in radv_emit_discard_rectangle()
1484       radeon_emit(cmd_buffer->cs, S_028214_BR_X(rect.offset.x + rect.extent.width) |  in radv_emit_discard_rectangle()
1490 radv_emit_line_width(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_line_width()  argument
1492    unsigned width = cmd_buffer->state.dynamic.line_width * 8;  in radv_emit_line_width()
1494    radeon_set_context_reg(cmd_buffer->cs, R_028A08_PA_SU_LINE_CNTL,  in radv_emit_line_width()
1499 radv_emit_blend_constants(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_blend_constants()  argument
1501    struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;  in radv_emit_blend_constants()
1503    radeon_set_context_reg_seq(cmd_buffer->cs, R_028414_CB_BLEND_RED, 4);  in radv_emit_blend_constants()
1504    radeon_emit_array(cmd_buffer->cs, (uint32_t *)d->blend_constants, 4);  in radv_emit_blend_constants()
1508 radv_emit_stencil(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_stencil()  argument
1510    struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;  in radv_emit_stencil()
1512    radeon_set_context_reg_seq(cmd_buffer->cs, R_028430_DB_STENCILREFMASK, 2);  in radv_emit_stencil()
1513    radeon_emit(cmd_buffer->cs, S_028430_STENCILTESTVAL(d->stencil_reference.front) |  in radv_emit_stencil()
1517    radeon_emit(cmd_buffer->cs, S_028434_STENCILTESTVAL_BF(d->stencil_reference.back) |  in radv_emit_stencil()
1524 radv_emit_depth_bounds(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_depth_bounds()  argument
1526    struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;  in radv_emit_depth_bounds()
1528    radeon_set_context_reg_seq(cmd_buffer->cs, R_028020_DB_DEPTH_BOUNDS_MIN, 2);  in radv_emit_depth_bounds()
1529    radeon_emit(cmd_buffer->cs, fui(d->depth_bounds.min));  in radv_emit_depth_bounds()
1530    radeon_emit(cmd_buffer->cs, fui(d->depth_bounds.max));  in radv_emit_depth_bounds()
1534 radv_emit_depth_bias(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_depth_bias()  argument
1536    struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;  in radv_emit_depth_bias()
1539    radeon_set_context_reg_seq(cmd_buffer->cs, R_028B7C_PA_SU_POLY_OFFSET_CLAMP, 5);  in radv_emit_depth_bias()
1540    radeon_emit(cmd_buffer->cs, fui(d->depth_bias.clamp)); /* CLAMP */  in radv_emit_depth_bias()
1541    radeon_emit(cmd_buffer->cs, slope);                    /* FRONT SCALE */  in radv_emit_depth_bias()
1542    radeon_emit(cmd_buffer->cs, fui(d->depth_bias.bias));  /* FRONT OFFSET */  in radv_emit_depth_bias()
1543    radeon_emit(cmd_buffer->cs, slope);                    /* BACK SCALE */  in radv_emit_depth_bias()
1544    radeon_emit(cmd_buffer->cs, fui(d->depth_bias.bias));  /* BACK OFFSET */  in radv_emit_depth_bias()
1548 radv_emit_line_stipple(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_line_stipple()  argument
1550    struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;  in radv_emit_line_stipple()
1556    radeon_set_context_reg(cmd_buffer->cs, R_028A0C_PA_SC_LINE_STIPPLE,  in radv_emit_line_stipple()
1563 radv_emit_culling(struct radv_cmd_buffer *cmd_buffer, uint64_t states)  in radv_emit_culling()  argument
1565    unsigned pa_su_sc_mode_cntl = cmd_buffer->state.pipeline->graphics.pa_su_sc_mode_cntl;  in radv_emit_culling()
1566    struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;  in radv_emit_culling()
1582    radeon_set_context_reg(cmd_buffer->cs, R_028814_PA_SU_SC_MODE_CNTL, pa_su_sc_mode_cntl);  in radv_emit_culling()
1586 radv_emit_primitive_topology(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_primitive_topology()  argument
1588    struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;  in radv_emit_primitive_topology()
1590    assert(!cmd_buffer->state.mesh_shading);  in radv_emit_primitive_topology()
1592    if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {  in radv_emit_primitive_topology()
1593       radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device, cmd_buffer->cs,  in radv_emit_primitive_topology()
1596       radeon_set_config_reg(cmd_buffer->cs, R_008958_VGT_PRIMITIVE_TYPE, d->primitive_topology);  in radv_emit_primitive_topology()
1601 radv_emit_depth_control(struct radv_cmd_buffer *cmd_buffer, uint64_t states)  in radv_emit_depth_control()  argument
1603    unsigned db_depth_control = cmd_buffer->state.pipeline->graphics.db_depth_control;  in radv_emit_depth_control()
1604    struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;  in radv_emit_depth_control()
1624    radeon_set_context_reg(cmd_buffer->cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);  in radv_emit_depth_control()
1628 radv_emit_stencil_control(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_stencil_control()  argument
1630    struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;  in radv_emit_stencil_control()
1633       cmd_buffer->cs, R_02842C_DB_STENCIL_CONTROL,  in radv_emit_stencil_control()
1643 radv_emit_fragment_shading_rate(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_fragment_shading_rate()  argument
1645    struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;  in radv_emit_fragment_shading_rate()
1646    const struct radv_subpass *subpass = cmd_buffer->state.subpass;  in radv_emit_fragment_shading_rate()
1647    struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;  in radv_emit_fragment_shading_rate()
1654    assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10_3);  in radv_emit_fragment_shading_rate()
1685    radeon_set_uconfig_reg(cmd_buffer->cs, R_03098C_GE_VRS_RATE,  in radv_emit_fragment_shading_rate()
1691    if (cmd_buffer->state.mesh_shading) {  in radv_emit_fragment_shading_rate()
1704    radeon_set_context_reg(cmd_buffer->cs, R_028848_PA_CL_VRS_CNTL, pa_cl_vrs_cntl);  in radv_emit_fragment_shading_rate()
1708 radv_emit_primitive_restart_enable(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_primitive_restart_enable()  argument
1710    struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;  in radv_emit_primitive_restart_enable()
1712    if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {  in radv_emit_primitive_restart_enable()
1713       radeon_set_uconfig_reg(cmd_buffer->cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,  in radv_emit_primitive_restart_enable()
1716       radeon_set_context_reg(cmd_buffer->cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,  in radv_emit_primitive_restart_enable()
1722 radv_emit_rasterizer_discard_enable(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_rasterizer_discard_enable()  argument
1724    unsigned pa_cl_clip_cntl = cmd_buffer->state.pipeline->graphics.pa_cl_clip_cntl;  in radv_emit_rasterizer_discard_enable()
1725    struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;  in radv_emit_rasterizer_discard_enable()
1730    radeon_set_context_reg(cmd_buffer->cs, R_028810_PA_CL_CLIP_CNTL, pa_cl_clip_cntl);  in radv_emit_rasterizer_discard_enable()
1734 radv_emit_logic_op(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_logic_op()  argument
1736    unsigned cb_color_control = cmd_buffer->state.pipeline->graphics.cb_color_control;  in radv_emit_logic_op()
1737    struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;  in radv_emit_logic_op()
1742    radeon_set_context_reg(cmd_buffer->cs, R_028808_CB_COLOR_CONTROL, cb_color_control);  in radv_emit_logic_op()
1746 radv_emit_color_write_enable(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_color_write_enable()  argument
1748    struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;  in radv_emit_color_write_enable()
1749    struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;  in radv_emit_color_write_enable()
1751    radeon_set_context_reg(cmd_buffer->cs, R_028238_CB_TARGET_MASK,  in radv_emit_color_write_enable()
1756 radv_emit_fb_color_state(struct radv_cmd_buffer *cmd_buffer, int index,  in radv_emit_fb_color_state()  argument
1760    bool is_vi = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8;  in radv_emit_fb_color_state()
1765           cmd_buffer->device, image, iview->base_mip, layout, in_render_loop,  in radv_emit_fb_color_state()
1766           radv_image_queue_family_mask(image, cmd_buffer->qf,  in radv_emit_fb_color_state()
1767                                        cmd_buffer->qf)) ||  in radv_emit_fb_color_state()
1773           cmd_buffer->device, image, layout,  in radv_emit_fb_color_state()
1774           radv_image_queue_family_mask(image, cmd_buffer->qf,  in radv_emit_fb_color_state()
1775                                        cmd_buffer->qf))) {  in radv_emit_fb_color_state()
1779    if (radv_image_is_tc_compat_cmask(image) && (radv_is_fmask_decompress_pipeline(cmd_buffer) ||  in radv_emit_fb_color_state()
1780                                                 radv_is_dcc_decompress_pipeline(cmd_buffer))) {  in radv_emit_fb_color_state()
1787    if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {  in radv_emit_fb_color_state()
1788       radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);  in radv_emit_fb_color_state()
1789       radeon_emit(cmd_buffer->cs, cb->cb_color_base);  in radv_emit_fb_color_state()
1790       radeon_emit(cmd_buffer->cs, 0);  in radv_emit_fb_color_state()
1791       radeon_emit(cmd_buffer->cs, 0);  in radv_emit_fb_color_state()
1792       radeon_emit(cmd_buffer->cs, cb->cb_color_view);  in radv_emit_fb_color_state()
1793       radeon_emit(cmd_buffer->cs, cb_color_info);  in radv_emit_fb_color_state()
1794       radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);  in radv_emit_fb_color_state()
1795       radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);  in radv_emit_fb_color_state()
1796       radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);  in radv_emit_fb_color_state()
1797       radeon_emit(cmd_buffer->cs, 0);  in radv_emit_fb_color_state()
1798       radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);  in radv_emit_fb_color_state()
1799       radeon_emit(cmd_buffer->cs, 0);  in radv_emit_fb_color_state()
1801 …radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, cb->cb_dcc_base…  in radv_emit_fb_color_state()
1803       radeon_set_context_reg(cmd_buffer->cs, R_028E40_CB_COLOR0_BASE_EXT + index * 4,  in radv_emit_fb_color_state()
1805       radeon_set_context_reg(cmd_buffer->cs, R_028E60_CB_COLOR0_CMASK_BASE_EXT + index * 4,  in radv_emit_fb_color_state()
1807       radeon_set_context_reg(cmd_buffer->cs, R_028E80_CB_COLOR0_FMASK_BASE_EXT + index * 4,  in radv_emit_fb_color_state()
1809       radeon_set_context_reg(cmd_buffer->cs, R_028EA0_CB_COLOR0_DCC_BASE_EXT + index * 4,  in radv_emit_fb_color_state()
1811       radeon_set_context_reg(cmd_buffer->cs, R_028EC0_CB_COLOR0_ATTRIB2 + index * 4,  in radv_emit_fb_color_state()
1813       radeon_set_context_reg(cmd_buffer->cs, R_028EE0_CB_COLOR0_ATTRIB3 + index * 4,  in radv_emit_fb_color_state()
1815    } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {  in radv_emit_fb_color_state()
1816       radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);  in radv_emit_fb_color_state()
1817       radeon_emit(cmd_buffer->cs, cb->cb_color_base);  in radv_emit_fb_color_state()
1818       radeon_emit(cmd_buffer->cs, S_028C64_BASE_256B(cb->cb_color_base >> 32));  in radv_emit_fb_color_state()
1819       radeon_emit(cmd_buffer->cs, cb->cb_color_attrib2);  in radv_emit_fb_color_state()
1820       radeon_emit(cmd_buffer->cs, cb->cb_color_view);  in radv_emit_fb_color_state()
1821       radeon_emit(cmd_buffer->cs, cb_color_info);  in radv_emit_fb_color_state()
1822       radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);  in radv_emit_fb_color_state()
1823       radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);  in radv_emit_fb_color_state()
1824       radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);  in radv_emit_fb_color_state()
1825       radeon_emit(cmd_buffer->cs, S_028C80_BASE_256B(cb->cb_color_cmask >> 32));  in radv_emit_fb_color_state()
1826       radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);  in radv_emit_fb_color_state()
1827       radeon_emit(cmd_buffer->cs, S_028C88_BASE_256B(cb->cb_color_fmask >> 32));  in radv_emit_fb_color_state()
1829       radeon_set_context_reg_seq(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c, 2);  in radv_emit_fb_color_state()
1830       radeon_emit(cmd_buffer->cs, cb->cb_dcc_base);  in radv_emit_fb_color_state()
1831       radeon_emit(cmd_buffer->cs, S_028C98_BASE_256B(cb->cb_dcc_base >> 32));  in radv_emit_fb_color_state()
1833       radeon_set_context_reg(cmd_buffer->cs, R_0287A0_CB_MRT0_EPITCH + index * 4,  in radv_emit_fb_color_state()
1836       radeon_set_context_reg_seq(cmd_buffer->cs, R_028C60_CB_COLOR0_BASE + index * 0x3c, 11);  in radv_emit_fb_color_state()
1837       radeon_emit(cmd_buffer->cs, cb->cb_color_base);  in radv_emit_fb_color_state()
1838       radeon_emit(cmd_buffer->cs, cb->cb_color_pitch);  in radv_emit_fb_color_state()
1839       radeon_emit(cmd_buffer->cs, cb->cb_color_slice);  in radv_emit_fb_color_state()
1840       radeon_emit(cmd_buffer->cs, cb->cb_color_view);  in radv_emit_fb_color_state()
1841       radeon_emit(cmd_buffer->cs, cb_color_info);  in radv_emit_fb_color_state()
1842       radeon_emit(cmd_buffer->cs, cb->cb_color_attrib);  in radv_emit_fb_color_state()
1843       radeon_emit(cmd_buffer->cs, cb->cb_dcc_control);  in radv_emit_fb_color_state()
1844       radeon_emit(cmd_buffer->cs, cb->cb_color_cmask);  in radv_emit_fb_color_state()
1845       radeon_emit(cmd_buffer->cs, cb->cb_color_cmask_slice);  in radv_emit_fb_color_state()
1846       radeon_emit(cmd_buffer->cs, cb->cb_color_fmask);  in radv_emit_fb_color_state()
1847       radeon_emit(cmd_buffer->cs, cb->cb_color_fmask_slice);  in radv_emit_fb_color_state()
1850          radeon_set_context_reg(cmd_buffer->cs, R_028C94_CB_COLOR0_DCC_BASE + index * 0x3c,  in radv_emit_fb_color_state()
1865       radv_update_dcc_metadata(cmd_buffer, image, &range, true);  in radv_emit_fb_color_state()
1870 radv_update_zrange_precision(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_buffer_info *ds,  in radv_update_zrange_precision()  argument
1878    if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug ||  in radv_update_zrange_precision()
1883           cmd_buffer->device, image, layout, in_render_loop,  in radv_update_zrange_precision()
1884           radv_image_queue_family_mask(image, cmd_buffer->qf,  in radv_update_zrange_precision()
1885                                        cmd_buffer->qf))) {  in radv_update_zrange_precision()
1891    if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {  in radv_update_zrange_precision()
1904       radeon_emit(cmd_buffer->cs, PKT3(PKT3_COND_EXEC, 3, 0));  in radv_update_zrange_precision()
1905       radeon_emit(cmd_buffer->cs, va);  in radv_update_zrange_precision()
1906       radeon_emit(cmd_buffer->cs, va >> 32);  in radv_update_zrange_precision()
1907       radeon_emit(cmd_buffer->cs, 0);  in radv_update_zrange_precision()
1908       radeon_emit(cmd_buffer->cs, 3); /* SET_CONTEXT_REG size */  in radv_update_zrange_precision()
1911    radeon_set_context_reg(cmd_buffer->cs, db_z_info_reg, db_z_info);  in radv_update_zrange_precision()
1915 radv_emit_fb_ds_state(struct radv_cmd_buffer *cmd_buffer, struct radv_ds_buffer_info *ds,  in radv_emit_fb_ds_state()  argument
1924           cmd_buffer->device, image, layout, in_render_loop,  in radv_emit_fb_ds_state()
1925           radv_image_queue_family_mask(image, cmd_buffer->qf,  in radv_emit_fb_ds_state()
1926                                        cmd_buffer->qf))) {  in radv_emit_fb_ds_state()
1931    if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10_3 &&  in radv_emit_fb_ds_state()
1932        !cmd_buffer->state.subpass->vrs_attachment) {  in radv_emit_fb_ds_state()
1936    radeon_set_context_reg(cmd_buffer->cs, R_028008_DB_DEPTH_VIEW, ds->db_depth_view);  in radv_emit_fb_ds_state()
1937    radeon_set_context_reg(cmd_buffer->cs, R_028ABC_DB_HTILE_SURFACE, db_htile_surface);  in radv_emit_fb_ds_state()
1939    if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {  in radv_emit_fb_ds_state()
1940       radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);  in radv_emit_fb_ds_state()
1941       radeon_set_context_reg(cmd_buffer->cs, R_02801C_DB_DEPTH_SIZE_XY, ds->db_depth_size);  in radv_emit_fb_ds_state()
1943       radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 7);  in radv_emit_fb_ds_state()
1944       radeon_emit(cmd_buffer->cs, S_02803C_RESOURCE_LEVEL(1));  in radv_emit_fb_ds_state()
1945       radeon_emit(cmd_buffer->cs, db_z_info);  in radv_emit_fb_ds_state()
1946       radeon_emit(cmd_buffer->cs, db_stencil_info);  in radv_emit_fb_ds_state()
1947       radeon_emit(cmd_buffer->cs, ds->db_z_read_base);  in radv_emit_fb_ds_state()
1948       radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  in radv_emit_fb_ds_state()
1949       radeon_emit(cmd_buffer->cs, ds->db_z_read_base);  in radv_emit_fb_ds_state()
1950       radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  in radv_emit_fb_ds_state()
1952       radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_READ_BASE_HI, 5);  in radv_emit_fb_ds_state()
1953       radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);  in radv_emit_fb_ds_state()
1954       radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);  in radv_emit_fb_ds_state()
1955       radeon_emit(cmd_buffer->cs, ds->db_z_read_base >> 32);  in radv_emit_fb_ds_state()
1956       radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base >> 32);  in radv_emit_fb_ds_state()
1957       radeon_emit(cmd_buffer->cs, ds->db_htile_data_base >> 32);  in radv_emit_fb_ds_state()
1958    } else if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {  in radv_emit_fb_ds_state()
1959       radeon_set_context_reg_seq(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, 3);  in radv_emit_fb_ds_state()
1960       radeon_emit(cmd_buffer->cs, ds->db_htile_data_base);  in radv_emit_fb_ds_state()
1961       radeon_emit(cmd_buffer->cs, S_028018_BASE_HI(ds->db_htile_data_base >> 32));  in radv_emit_fb_ds_state()
1962       radeon_emit(cmd_buffer->cs, ds->db_depth_size);  in radv_emit_fb_ds_state()
1964       radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 10);  in radv_emit_fb_ds_state()
1965       radeon_emit(cmd_buffer->cs, db_z_info);          /* DB_Z_INFO */  in radv_emit_fb_ds_state()
1966       radeon_emit(cmd_buffer->cs, db_stencil_info);    /* DB_STENCIL_INFO */  in radv_emit_fb_ds_state()
1967       radeon_emit(cmd_buffer->cs, ds->db_z_read_base); /* DB_Z_READ_BASE */  in radv_emit_fb_ds_state()
1968       radeon_emit(cmd_buffer->cs,  in radv_emit_fb_ds_state()
1970       radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);   /* DB_STENCIL_READ_BASE */  in radv_emit_fb_ds_state()
1971       radeon_emit(cmd_buffer->cs,  in radv_emit_fb_ds_state()
1973       radeon_emit(cmd_buffer->cs, ds->db_z_write_base);              /* DB_Z_WRITE_BASE */  in radv_emit_fb_ds_state()
1974       radeon_emit(cmd_buffer->cs,  in radv_emit_fb_ds_state()
1976       radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base);   /* DB_STENCIL_WRITE_BASE */  in radv_emit_fb_ds_state()
1977       radeon_emit(cmd_buffer->cs,  in radv_emit_fb_ds_state()
1980       radeon_set_context_reg_seq(cmd_buffer->cs, R_028068_DB_Z_INFO2, 2);  in radv_emit_fb_ds_state()
1981       radeon_emit(cmd_buffer->cs, ds->db_z_info2);  in radv_emit_fb_ds_state()
1982       radeon_emit(cmd_buffer->cs, ds->db_stencil_info2);  in radv_emit_fb_ds_state()
1984       radeon_set_context_reg(cmd_buffer->cs, R_028014_DB_HTILE_DATA_BASE, ds->db_htile_data_base);  in radv_emit_fb_ds_state()
1986       radeon_set_context_reg_seq(cmd_buffer->cs, R_02803C_DB_DEPTH_INFO, 9);  in radv_emit_fb_ds_state()
1987       radeon_emit(cmd_buffer->cs, ds->db_depth_info);         /* R_02803C_DB_DEPTH_INFO */  in radv_emit_fb_ds_state()
1988       radeon_emit(cmd_buffer->cs, db_z_info);                 /* R_028040_DB_Z_INFO */  in radv_emit_fb_ds_state()
1989       radeon_emit(cmd_buffer->cs, db_stencil_info);           /* R_028044_DB_STENCIL_INFO */  in radv_emit_fb_ds_state()
1990       radeon_emit(cmd_buffer->cs, ds->db_z_read_base);        /* R_028048_DB_Z_READ_BASE */  in radv_emit_fb_ds_state()
1991       radeon_emit(cmd_buffer->cs, ds->db_stencil_read_base);  /* R_02804C_DB_STENCIL_READ_BASE */  in radv_emit_fb_ds_state()
1992       radeon_emit(cmd_buffer->cs, ds->db_z_write_base);       /* R_028050_DB_Z_WRITE_BASE */  in radv_emit_fb_ds_state()
1993       radeon_emit(cmd_buffer->cs, ds->db_stencil_write_base); /* R_028054_DB_STENCIL_WRITE_BASE */  in radv_emit_fb_ds_state()
1994       radeon_emit(cmd_buffer->cs, ds->db_depth_size);         /* R_028058_DB_DEPTH_SIZE */  in radv_emit_fb_ds_state()
1995       radeon_emit(cmd_buffer->cs, ds->db_depth_slice);        /* R_02805C_DB_DEPTH_SLICE */  in radv_emit_fb_ds_state()
1999    radv_update_zrange_precision(cmd_buffer, ds, iview, layout, in_render_loop, true);  in radv_emit_fb_ds_state()
2001    radeon_set_context_reg(cmd_buffer->cs, R_028B78_PA_SU_POLY_OFFSET_DB_FMT_CNTL,  in radv_emit_fb_ds_state()
2010 radv_update_bound_fast_clear_ds(struct radv_cmd_buffer *cmd_buffer,  in radv_update_bound_fast_clear_ds()  argument
2014    const struct radv_subpass *subpass = cmd_buffer->state.subpass;  in radv_update_bound_fast_clear_ds()
2016    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_update_bound_fast_clear_ds()
2019    if (!cmd_buffer->state.attachments || !subpass)  in radv_update_bound_fast_clear_ds()
2026    if (cmd_buffer->state.attachments[att_idx].iview->image != image)  in radv_update_bound_fast_clear_ds()
2047       radv_update_zrange_precision(cmd_buffer, &cmd_buffer->state.attachments[att_idx].ds, iview,  in radv_update_bound_fast_clear_ds()
2051    cmd_buffer->state.context_roll_without_scissor_emitted = true;  in radv_update_bound_fast_clear_ds()
2058 radv_set_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,  in radv_set_ds_clear_metadata()  argument
2062    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_set_ds_clear_metadata()
2069       radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + 2 * level_count, cmd_buffer->state.predicating));  in radv_set_ds_clear_metadata()
2092          radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, cmd_buffer->state.predicating));  in radv_set_ds_clear_metadata()
2106 radv_set_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,  in radv_set_tc_compat_zrange_metadata()  argument
2109    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_set_tc_compat_zrange_metadata()
2111    if (!cmd_buffer->device->physical_device->rad_info.has_tc_compat_zrange_bug)  in radv_set_tc_compat_zrange_metadata()
2117    radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + level_count, cmd_buffer->state.predicating));  in radv_set_tc_compat_zrange_metadata()
2127 radv_update_tc_compat_zrange_metadata(struct radv_cmd_buffer *cmd_buffer,  in radv_update_tc_compat_zrange_metadata()  argument
2145    radv_set_tc_compat_zrange_metadata(cmd_buffer, iview->image, &range, cond_val);  in radv_update_tc_compat_zrange_metadata()
2152 radv_update_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer,  in radv_update_ds_clear_metadata()  argument
2167    radv_set_ds_clear_metadata(cmd_buffer, iview->image, &range, ds_clear_value, aspects);  in radv_update_ds_clear_metadata()
2170       radv_update_tc_compat_zrange_metadata(cmd_buffer, iview, ds_clear_value);  in radv_update_ds_clear_metadata()
2173    radv_update_bound_fast_clear_ds(cmd_buffer, iview, ds_clear_value, aspects);  in radv_update_ds_clear_metadata()
2180 radv_load_ds_clear_metadata(struct radv_cmd_buffer *cmd_buffer, const struct radv_image_view *iview)  in radv_load_ds_clear_metadata()  argument
2182    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_load_ds_clear_metadata()
2201    if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {  in radv_load_ds_clear_metadata()
2227 radv_update_fce_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,  in radv_update_fce_metadata()  argument
2238    radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));  in radv_update_fce_metadata()
2239    radeon_emit(cmd_buffer->cs,  in radv_update_fce_metadata()
2241    radeon_emit(cmd_buffer->cs, va);  in radv_update_fce_metadata()
2242    radeon_emit(cmd_buffer->cs, va >> 32);  in radv_update_fce_metadata()
2245       radeon_emit(cmd_buffer->cs, pred_val);  in radv_update_fce_metadata()
2246       radeon_emit(cmd_buffer->cs, pred_val >> 32);  in radv_update_fce_metadata()
2254 radv_update_dcc_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,  in radv_update_dcc_metadata()  argument
2267    radeon_emit(cmd_buffer->cs, PKT3(PKT3_WRITE_DATA, 2 + count, 0));  in radv_update_dcc_metadata()
2268    radeon_emit(cmd_buffer->cs,  in radv_update_dcc_metadata()
2270    radeon_emit(cmd_buffer->cs, va);  in radv_update_dcc_metadata()
2271    radeon_emit(cmd_buffer->cs, va >> 32);  in radv_update_dcc_metadata()
2274       radeon_emit(cmd_buffer->cs, pred_val);  in radv_update_dcc_metadata()
2275       radeon_emit(cmd_buffer->cs, pred_val >> 32);  in radv_update_dcc_metadata()
2283 radv_update_bound_fast_clear_color(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,  in radv_update_bound_fast_clear_color()  argument
2286    const struct radv_subpass *subpass = cmd_buffer->state.subpass;  in radv_update_bound_fast_clear_color()
2287    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_update_bound_fast_clear_color()
2290    if (!cmd_buffer->state.attachments || !subpass)  in radv_update_bound_fast_clear_color()
2297    if (cmd_buffer->state.attachments[att_idx].iview->image != image)  in radv_update_bound_fast_clear_color()
2304    cmd_buffer->state.context_roll_without_scissor_emitted = true;  in radv_update_bound_fast_clear_color()
2311 radv_set_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,  in radv_set_color_clear_metadata()  argument
2314    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_set_color_clear_metadata()
2323       radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 2 + count, cmd_buffer->state.predicating));  in radv_set_color_clear_metadata()
2342 radv_update_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer,  in radv_update_color_clear_metadata()  argument
2363    radv_set_color_clear_metadata(cmd_buffer, image, &range, color_values);  in radv_update_color_clear_metadata()
2365    radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx, color_values);  in radv_update_color_clear_metadata()
2372 radv_load_color_clear_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image_view *iview,  in radv_load_color_clear_metadata()  argument
2375    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_load_color_clear_metadata()
2386       radv_update_bound_fast_clear_color(cmd_buffer, image, cb_idx, color_values);  in radv_load_color_clear_metadata()
2393    if (cmd_buffer->device->physical_device->rad_info.has_load_ctx_reg_pkt) {  in radv_load_color_clear_metadata()
2394       radeon_emit(cs, PKT3(PKT3_LOAD_CONTEXT_REG_INDEX, 3, cmd_buffer->state.predicating));  in radv_load_color_clear_metadata()
2400       radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));  in radv_load_color_clear_metadata()
2408       radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, cmd_buffer->state.predicating));  in radv_load_color_clear_metadata()
2420 radv_emit_fb_mip_change_flush(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_fb_mip_change_flush()  argument
2422    struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;  in radv_emit_fb_mip_change_flush()
2423    const struct radv_subpass *subpass = cmd_buffer->state.subpass;  in radv_emit_fb_mip_change_flush()
2427    if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9)  in radv_emit_fb_mip_change_flush()
2438       struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;  in radv_emit_fb_mip_change_flush()
2442            radv_dcc_enabled(iview->image, cmd_buffer->state.cb_mip[i])) &&  in radv_emit_fb_mip_change_flush()
2443           cmd_buffer->state.cb_mip[i] != iview->base_mip)  in radv_emit_fb_mip_change_flush()
2446       cmd_buffer->state.cb_mip[i] = iview->base_mip;  in radv_emit_fb_mip_change_flush()
2450       cmd_buffer->state.flush_bits |=  in radv_emit_fb_mip_change_flush()
2460 radv_emit_mip_change_flush_default(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_mip_change_flush_default()  argument
2463    if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9)  in radv_emit_mip_change_flush_default()
2468       if (cmd_buffer->state.cb_mip[i]) {  in radv_emit_mip_change_flush_default()
2475       cmd_buffer->state.flush_bits |=  in radv_emit_mip_change_flush_default()
2479    memset(cmd_buffer->state.cb_mip, 0, sizeof(cmd_buffer->state.cb_mip));  in radv_emit_mip_change_flush_default()
2483 radv_cmd_buffer_get_vrs_image(struct radv_cmd_buffer *cmd_buffer)  in radv_cmd_buffer_get_vrs_image()  argument
2485    struct radv_device *device = cmd_buffer->device;  in radv_cmd_buffer_get_vrs_image()
2493          cmd_buffer->record_result = result;  in radv_cmd_buffer_get_vrs_image()
2502 radv_emit_framebuffer_state(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_framebuffer_state()  argument
2505    struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;  in radv_emit_framebuffer_state()
2506    const struct radv_subpass *subpass = cmd_buffer->state.subpass;  in radv_emit_framebuffer_state()
2512          radeon_set_context_reg(cmd_buffer->cs, R_028C70_CB_COLOR0_INFO + i * 0x3C,  in radv_emit_framebuffer_state()
2518       struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;  in radv_emit_framebuffer_state()
2522       radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, iview->image->bo);  in radv_emit_framebuffer_state()
2526       radv_emit_fb_color_state(cmd_buffer, i, &cmd_buffer->state.attachments[idx].cb, iview, layout,  in radv_emit_framebuffer_state()
2527                                in_render_loop, cmd_buffer->state.attachments[idx].disable_dcc);  in radv_emit_framebuffer_state()
2529       radv_load_color_clear_metadata(cmd_buffer, iview, i);  in radv_emit_framebuffer_state()
2531       if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9 &&  in radv_emit_framebuffer_state()
2544       struct radv_image_view *iview = cmd_buffer->state.attachments[idx].iview;  in radv_emit_framebuffer_state()
2545       radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs,  in radv_emit_framebuffer_state()
2546                          cmd_buffer->state.attachments[idx].iview->image->bo);  in radv_emit_framebuffer_state()
2548       radv_emit_fb_ds_state(cmd_buffer, &cmd_buffer->state.attachments[idx].ds, iview, layout,  in radv_emit_framebuffer_state()
2552              cmd_buffer->device, iview->image, layout, in_render_loop,  in radv_emit_framebuffer_state()
2553              radv_image_queue_family_mask(iview->image, cmd_buffer->qf,  in radv_emit_framebuffer_state()
2554                                           cmd_buffer->qf))) {  in radv_emit_framebuffer_state()
2558          radv_load_ds_clear_metadata(cmd_buffer, iview);  in radv_emit_framebuffer_state()
2560    } else if (subpass->vrs_attachment && radv_cmd_buffer_get_vrs_image(cmd_buffer)) {  in radv_emit_framebuffer_state()
2565       struct radv_buffer *htile_buffer = cmd_buffer->device->vrs.buffer;  in radv_emit_framebuffer_state()
2566       struct radv_image *image = cmd_buffer->device->vrs.image;  in radv_emit_framebuffer_state()
2570       radv_image_view_init(&iview, cmd_buffer->device,  in radv_emit_framebuffer_state()
2589       radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, htile_buffer->bo);  in radv_emit_framebuffer_state()
2591       radv_emit_fb_ds_state(cmd_buffer, &ds, &iview, layout, false);  in radv_emit_framebuffer_state()
2595       if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9)  in radv_emit_framebuffer_state()
2596          radeon_set_context_reg_seq(cmd_buffer->cs, R_028038_DB_Z_INFO, 2);  in radv_emit_framebuffer_state()
2598          radeon_set_context_reg_seq(cmd_buffer->cs, R_028040_DB_Z_INFO, 2);  in radv_emit_framebuffer_state()
2600       radeon_emit(cmd_buffer->cs, S_028040_FORMAT(V_028040_Z_INVALID));       /* DB_Z_INFO */  in radv_emit_framebuffer_state()
2601       radeon_emit(cmd_buffer->cs, S_028044_FORMAT(V_028044_STENCIL_INVALID)); /* DB_STENCIL_INFO */  in radv_emit_framebuffer_state()
2603    radeon_set_context_reg(cmd_buffer->cs, R_028208_PA_SC_WINDOW_SCISSOR_BR,  in radv_emit_framebuffer_state()
2606    if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX8) {  in radv_emit_framebuffer_state()
2608          cmd_buffer->device->physical_device->rad_info.has_dcc_constant_encode;  in radv_emit_framebuffer_state()
2609       enum chip_class chip_class = cmd_buffer->device->physical_device->rad_info.chip_class;  in radv_emit_framebuffer_state()
2612       radeon_set_context_reg(cmd_buffer->cs, R_028424_CB_DCC_CONTROL,  in radv_emit_framebuffer_state()
2619    cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_FRAMEBUFFER;  in radv_emit_framebuffer_state()
2623 radv_emit_index_buffer(struct radv_cmd_buffer *cmd_buffer, bool indirect)  in radv_emit_index_buffer()  argument
2625    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_emit_index_buffer()
2626    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_emit_index_buffer()
2629       if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX9) {  in radv_emit_index_buffer()
2630          radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device, cs,  in radv_emit_index_buffer()
2652    cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_INDEX_BUFFER;  in radv_emit_index_buffer()
2656 radv_set_db_count_control(struct radv_cmd_buffer *cmd_buffer)  in radv_set_db_count_control()  argument
2658    bool has_perfect_queries = cmd_buffer->state.perfect_occlusion_queries_enabled;  in radv_set_db_count_control()
2659    struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;  in radv_set_db_count_control()
2663    if (!cmd_buffer->state.active_occlusion_queries) {  in radv_set_db_count_control()
2664       if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {  in radv_set_db_count_control()
2672             radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, pa_sc_mode_cntl_1);  in radv_set_db_count_control()
2677       const struct radv_subpass *subpass = cmd_buffer->state.subpass;  in radv_set_db_count_control()
2680          cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10 && has_perfect_queries;  in radv_set_db_count_control()
2682       if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {  in radv_set_db_count_control()
2700             radeon_set_context_reg(cmd_buffer->cs, R_028A4C_PA_SC_MODE_CNTL_1, pa_sc_mode_cntl_1);  in radv_set_db_count_control()
2707    radeon_set_context_reg(cmd_buffer->cs, R_028004_DB_COUNT_CONTROL, db_count_control);  in radv_set_db_count_control()
2709    cmd_buffer->state.context_roll_without_scissor_emitted = true;  in radv_set_db_count_control()
2784 lookup_vs_prolog(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *vs_shader,  in lookup_vs_prolog()  argument
2790    const struct radv_vs_input_state *state = &cmd_buffer->state.dynamic_vs_input;  in lookup_vs_prolog()
2791    const struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;  in lookup_vs_prolog()
2792    struct radv_device *device = cmd_buffer->device;  in lookup_vs_prolog()
2800 …const uint32_t misaligned_mask = chip == GFX6 || chip >= GFX10 ? cmd_buffer->state.vbo_misaligned_…  in lookup_vs_prolog()
2879    if (cmd_buffer->state.emitted_vs_prolog &&  in lookup_vs_prolog()
2880        cmd_buffer->state.emitted_vs_prolog_key_hash == hash &&  in lookup_vs_prolog()
2881        radv_cmp_vs_prolog(key_words, cmd_buffer->state.emitted_vs_prolog_key))  in lookup_vs_prolog()
2882       return cmd_buffer->state.emitted_vs_prolog;  in lookup_vs_prolog()
2916 emit_prolog_regs(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *vs_shader,  in emit_prolog_regs()  argument
2920    if (cmd_buffer->state.emitted_vs_prolog == prolog && !pipeline_is_dirty)  in emit_prolog_regs()
2923    enum chip_class chip = cmd_buffer->device->physical_device->rad_info.chip_class;  in emit_prolog_regs()
2924    struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;  in emit_prolog_regs()
2927    assert(cmd_buffer->state.emitted_pipeline == cmd_buffer->state.pipeline);  in emit_prolog_regs()
2954    radeon_set_sh_reg(cmd_buffer->cs, pgm_lo_reg, prolog_va >> 8);  in emit_prolog_regs()
2957       radeon_set_sh_reg(cmd_buffer->cs, rsrc1_reg, rsrc1);  in emit_prolog_regs()
2961    radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, prolog->bo);  in emit_prolog_regs()
2965 emit_prolog_inputs(struct radv_cmd_buffer *cmd_buffer, struct radv_shader *vs_shader,  in emit_prolog_inputs()  argument
2969    if (!nontrivial_divisors && !pipeline_is_dirty && cmd_buffer->state.emitted_vs_prolog &&  in emit_prolog_inputs()
2970        !cmd_buffer->state.emitted_vs_prolog->nontrivial_divisors)  in emit_prolog_inputs()
2973    const struct radv_vs_input_state *state = &cmd_buffer->state.dynamic_vs_input;  in emit_prolog_inputs()
2980       if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, &inputs_offset, (void **)&inputs))  in emit_prolog_inputs()
3002       input_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + inputs_offset;  in emit_prolog_inputs()
3007    uint32_t base_reg = cmd_buffer->state.pipeline->user_data_0[MESA_SHADER_VERTEX];  in emit_prolog_inputs()
3010    radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,  in emit_prolog_inputs()
3015 radv_emit_vertex_input(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)  in radv_emit_vertex_input()  argument
3017    struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;  in radv_emit_vertex_input()
3020    assert(!cmd_buffer->state.mesh_shading);  in radv_emit_vertex_input()
3027       lookup_vs_prolog(cmd_buffer, vs_shader, &nontrivial_divisors);  in radv_emit_vertex_input()
3029       cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;  in radv_emit_vertex_input()
3032    emit_prolog_regs(cmd_buffer, vs_shader, prolog, pipeline_is_dirty);  in radv_emit_vertex_input()
3033    emit_prolog_inputs(cmd_buffer, vs_shader, nontrivial_divisors, pipeline_is_dirty);  in radv_emit_vertex_input()
3035    cmd_buffer->state.emitted_vs_prolog = prolog;  in radv_emit_vertex_input()
3037    if (unlikely(cmd_buffer->device->trace_bo))  in radv_emit_vertex_input()
3038       radv_save_vs_prolog(cmd_buffer, prolog);  in radv_emit_vertex_input()
3042 radv_cmd_buffer_flush_dynamic_state(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)  in radv_cmd_buffer_flush_dynamic_state()  argument
3045       cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;  in radv_cmd_buffer_flush_dynamic_state()
3048       radv_emit_viewport(cmd_buffer);  in radv_cmd_buffer_flush_dynamic_state()
3051        !cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)  in radv_cmd_buffer_flush_dynamic_state()
3052       radv_emit_scissor(cmd_buffer);  in radv_cmd_buffer_flush_dynamic_state()
3055       radv_emit_line_width(cmd_buffer);  in radv_cmd_buffer_flush_dynamic_state()
3058       radv_emit_blend_constants(cmd_buffer);  in radv_cmd_buffer_flush_dynamic_state()
3063       radv_emit_stencil(cmd_buffer);  in radv_cmd_buffer_flush_dynamic_state()
3066       radv_emit_depth_bounds(cmd_buffer);  in radv_cmd_buffer_flush_dynamic_state()
3069       radv_emit_depth_bias(cmd_buffer);  in radv_cmd_buffer_flush_dynamic_state()
3072       radv_emit_discard_rectangle(cmd_buffer);  in radv_cmd_buffer_flush_dynamic_state()
3075       radv_emit_sample_locations(cmd_buffer);  in radv_cmd_buffer_flush_dynamic_state()
3078       radv_emit_line_stipple(cmd_buffer);  in radv_cmd_buffer_flush_dynamic_state()
3082       radv_emit_culling(cmd_buffer, states);  in radv_cmd_buffer_flush_dynamic_state()
3085       radv_emit_primitive_topology(cmd_buffer);  in radv_cmd_buffer_flush_dynamic_state()
3091       radv_emit_depth_control(cmd_buffer, states);  in radv_cmd_buffer_flush_dynamic_state()
3094       radv_emit_stencil_control(cmd_buffer);  in radv_cmd_buffer_flush_dynamic_state()
3097       radv_emit_fragment_shading_rate(cmd_buffer);  in radv_cmd_buffer_flush_dynamic_state()
3100       radv_emit_primitive_restart_enable(cmd_buffer);  in radv_cmd_buffer_flush_dynamic_state()
3103       radv_emit_rasterizer_discard_enable(cmd_buffer);  in radv_cmd_buffer_flush_dynamic_state()
3106       radv_emit_logic_op(cmd_buffer);  in radv_cmd_buffer_flush_dynamic_state()
3109       radv_emit_color_write_enable(cmd_buffer);  in radv_cmd_buffer_flush_dynamic_state()
3112       radv_emit_vertex_input(cmd_buffer, pipeline_is_dirty);  in radv_cmd_buffer_flush_dynamic_state()
3114    cmd_buffer->state.dirty &= ~states;  in radv_cmd_buffer_flush_dynamic_state()
3118 radv_flush_push_descriptors(struct radv_cmd_buffer *cmd_buffer, VkPipelineBindPoint bind_point)  in radv_flush_push_descriptors()  argument
3121       radv_get_descriptors_state(cmd_buffer, bind_point);  in radv_flush_push_descriptors()
3125    if (!radv_cmd_buffer_upload_data(cmd_buffer, set->header.size, set->header.mapped_ptr,  in radv_flush_push_descriptors()
3129    set->header.va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);  in radv_flush_push_descriptors()
3134 radv_flush_indirect_descriptor_sets(struct radv_cmd_buffer *cmd_buffer,  in radv_flush_indirect_descriptor_sets()  argument
3138       radv_get_descriptors_state(cmd_buffer, bind_point);  in radv_flush_indirect_descriptor_sets()
3143    if (!radv_cmd_buffer_upload_alloc(cmd_buffer, size, &offset, &ptr))  in radv_flush_indirect_descriptor_sets()
3155    uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);  in radv_flush_indirect_descriptor_sets()
3160          radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX,  in radv_flush_indirect_descriptor_sets()
3164          radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_FRAGMENT,  in radv_flush_indirect_descriptor_sets()
3168          radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_MESH,  in radv_flush_indirect_descriptor_sets()
3172          radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_GEOMETRY,  in radv_flush_indirect_descriptor_sets()
3176          radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_CTRL,  in radv_flush_indirect_descriptor_sets()
3180          radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_TESS_EVAL,  in radv_flush_indirect_descriptor_sets()
3183       radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_COMPUTE,  in radv_flush_indirect_descriptor_sets()
3189 radv_flush_descriptors(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stages,  in radv_flush_descriptors()  argument
3193       radv_get_descriptors_state(cmd_buffer, bind_point);  in radv_flush_descriptors()
3200       radv_flush_push_descriptors(cmd_buffer, bind_point);  in radv_flush_descriptors()
3205       radv_flush_indirect_descriptor_sets(cmd_buffer, pipeline, bind_point);  in radv_flush_descriptors()
3208 …radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, MAX_SETS * MESA_VULKAN_SHADER_STAGES * …  in radv_flush_descriptors()
3211       radv_emit_descriptor_pointers(cmd_buffer, pipeline, descriptors_state, MESA_SHADER_COMPUTE);  in radv_flush_descriptors()
3215          if (!cmd_buffer->state.pipeline->shaders[stage])  in radv_flush_descriptors()
3218          radv_emit_descriptor_pointers(cmd_buffer, pipeline, descriptors_state, stage);  in radv_flush_descriptors()
3225    assert(cmd_buffer->cs->cdw <= cdw_max);  in radv_flush_descriptors()
3227    if (unlikely(cmd_buffer->device->trace_bo))  in radv_flush_descriptors()
3228       radv_save_descriptors(cmd_buffer, bind_point);  in radv_flush_descriptors()
3240 radv_flush_constants(struct radv_cmd_buffer *cmd_buffer, VkShaderStageFlags stages,  in radv_flush_constants()  argument
3244       radv_get_descriptors_state(cmd_buffer, bind_point);  in radv_flush_constants()
3253    stages &= cmd_buffer->push_constant_stages;  in radv_flush_constants()
3282       radv_emit_inline_push_consts(cmd_buffer, pipeline, stage, AC_UD_INLINE_PUSH_CONSTANTS,  in radv_flush_constants()
3283                                    (uint32_t *)cmd_buffer->push_constants + base);  in radv_flush_constants()
3288 …           cmd_buffer, pipeline->push_constant_size + 16 * pipeline->dynamic_offset_count, &offset,  in radv_flush_constants()
3292       memcpy(ptr, cmd_buffer->push_constants, pipeline->push_constant_size);  in radv_flush_constants()
3296       va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);  in radv_flush_constants()
3300          radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, MESA_VULKAN_SHADER_STAGES * 4);  in radv_flush_constants()
3309             radv_emit_userdata_address(cmd_buffer, pipeline, stage, AC_UD_PUSH_CONSTANTS, va);  in radv_flush_constants()
3314       assert(cmd_buffer->cs->cdw <= cdw_max);  in radv_flush_constants()
3317    cmd_buffer->push_constant_stages &= ~stages;  in radv_flush_constants()
3318    cmd_buffer->push_constant_stages |= dirty_stages;  in radv_flush_constants()
3355 radv_flush_vertex_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)  in radv_flush_vertex_descriptors()  argument
3357    if ((pipeline_is_dirty || (cmd_buffer->state.dirty & RADV_CMD_DIRTY_VERTEX_BUFFER)) &&  in radv_flush_vertex_descriptors()
3358        cmd_buffer->state.pipeline->vb_desc_usage_mask) {  in radv_flush_vertex_descriptors()
3360       assert(!cmd_buffer->state.mesh_shading);  in radv_flush_vertex_descriptors()
3362       struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;  in radv_flush_vertex_descriptors()
3364       enum chip_class chip = cmd_buffer->device->physical_device->rad_info.chip_class;  in radv_flush_vertex_descriptors()
3371          vs_shader->info.vs.dynamic_inputs ? &cmd_buffer->state.dynamic_vs_input : NULL;  in radv_flush_vertex_descriptors()
3374 …  if (!radv_cmd_buffer_upload_alloc(cmd_buffer, pipeline->vb_desc_alloc_size, &vb_offset, &vb_ptr))  in radv_flush_vertex_descriptors()
3384             vs_state ? cmd_buffer->state.dynamic_vs_input.bindings[i]  in radv_flush_vertex_descriptors()
3386          struct radv_buffer *buffer = cmd_buffer->vertex_bindings[binding].buffer;  in radv_flush_vertex_descriptors()
3428          offset = cmd_buffer->vertex_bindings[binding].offset;  in radv_flush_vertex_descriptors()
3433          if (cmd_buffer->vertex_bindings[binding].size) {  in radv_flush_vertex_descriptors()
3434             num_records = cmd_buffer->vertex_bindings[binding].size;  in radv_flush_vertex_descriptors()
3440             stride = cmd_buffer->vertex_bindings[binding].stride;  in radv_flush_vertex_descriptors()
3502       va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);  in radv_flush_vertex_descriptors()
3505       radv_emit_userdata_address(cmd_buffer, pipeline, MESA_SHADER_VERTEX, AC_UD_VS_VERTEX_BUFFERS,  in radv_flush_vertex_descriptors()
3508       cmd_buffer->state.vb_va = va;  in radv_flush_vertex_descriptors()
3509       cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_VBO_DESCRIPTORS;  in radv_flush_vertex_descriptors()
3511       if (unlikely(cmd_buffer->device->trace_bo))  in radv_flush_vertex_descriptors()
3512          radv_save_vertex_descriptors(cmd_buffer, (uintptr_t)vb_ptr);  in radv_flush_vertex_descriptors()
3514    cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_VERTEX_BUFFER;  in radv_flush_vertex_descriptors()
3518 radv_emit_streamout_buffers(struct radv_cmd_buffer *cmd_buffer, uint64_t va)  in radv_emit_streamout_buffers()  argument
3520    struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;  in radv_emit_streamout_buffers()
3534       radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, va,  in radv_emit_streamout_buffers()
3543          radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4,  in radv_emit_streamout_buffers()
3550 radv_flush_streamout_descriptors(struct radv_cmd_buffer *cmd_buffer)  in radv_flush_streamout_descriptors()  argument
3552    if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_STREAMOUT_BUFFER) {  in radv_flush_streamout_descriptors()
3553       struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;  in radv_flush_streamout_descriptors()
3554       struct radv_streamout_state *so = &cmd_buffer->state.streamout;  in radv_flush_streamout_descriptors()
3560       if (!radv_cmd_buffer_upload_alloc(cmd_buffer, MAX_SO_BUFFERS * 16, &so_offset, &so_ptr))  in radv_flush_streamout_descriptors()
3586          if (cmd_buffer->device->physical_device->use_ngg_streamout)  in radv_flush_streamout_descriptors()
3593          if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {  in radv_flush_streamout_descriptors()
3606       va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);  in radv_flush_streamout_descriptors()
3609       radv_emit_streamout_buffers(cmd_buffer, va);  in radv_flush_streamout_descriptors()
3612    cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_STREAMOUT_BUFFER;  in radv_flush_streamout_descriptors()
3616 radv_flush_ngg_gs_state(struct radv_cmd_buffer *cmd_buffer)  in radv_flush_ngg_gs_state()  argument
3618    struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;  in radv_flush_ngg_gs_state()
3630    if (cmd_buffer->state.active_pipeline_gds_queries ||  in radv_flush_ngg_gs_state()
3631        (cmd_buffer->state.inherited_pipeline_statistics &  in radv_flush_ngg_gs_state()
3639    radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, ngg_gs_state);  in radv_flush_ngg_gs_state()
3643 radv_flush_force_vrs_state(struct radv_cmd_buffer *cmd_buffer)  in radv_flush_force_vrs_state()  argument
3645    struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;  in radv_flush_force_vrs_state()
3653       cmd_buffer->state.last_vrs_rates_sgpr_idx = -1;  in radv_flush_force_vrs_state()
3662    switch (cmd_buffer->device->force_vrs) {  in radv_flush_force_vrs_state()
3676    if (cmd_buffer->state.last_vrs_rates != vrs_rates ||  in radv_flush_force_vrs_state()
3677        cmd_buffer->state.last_vrs_rates_sgpr_idx != loc->sgpr_idx) {  in radv_flush_force_vrs_state()
3678       radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, vrs_rates);  in radv_flush_force_vrs_state()
3681    cmd_buffer->state.last_vrs_rates = vrs_rates;  in radv_flush_force_vrs_state()
3682    cmd_buffer->state.last_vrs_rates_sgpr_idx = loc->sgpr_idx;  in radv_flush_force_vrs_state()
3686 radv_upload_graphics_shader_descriptors(struct radv_cmd_buffer *cmd_buffer, bool pipeline_is_dirty)  in radv_upload_graphics_shader_descriptors()  argument
3688    radv_flush_vertex_descriptors(cmd_buffer, pipeline_is_dirty);  in radv_upload_graphics_shader_descriptors()
3689    radv_flush_streamout_descriptors(cmd_buffer);  in radv_upload_graphics_shader_descriptors()
3692    radv_flush_descriptors(cmd_buffer, stages, cmd_buffer->state.pipeline,  in radv_upload_graphics_shader_descriptors()
3694    radv_flush_constants(cmd_buffer, stages, cmd_buffer->state.pipeline,  in radv_upload_graphics_shader_descriptors()
3696    radv_flush_ngg_gs_state(cmd_buffer);  in radv_upload_graphics_shader_descriptors()
3697    radv_flush_force_vrs_state(cmd_buffer);  in radv_upload_graphics_shader_descriptors()
3742 radv_get_primitive_reset_index(struct radv_cmd_buffer *cmd_buffer)  in radv_get_primitive_reset_index()  argument
3744    switch (cmd_buffer->state.index_type) {  in radv_get_primitive_reset_index()
3757 si_emit_ia_multi_vgt_param(struct radv_cmd_buffer *cmd_buffer, bool instanced_draw,  in si_emit_ia_multi_vgt_param()  argument
3761    struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;  in si_emit_ia_multi_vgt_param()
3762    struct radv_cmd_state *state = &cmd_buffer->state;  in si_emit_ia_multi_vgt_param()
3765    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in si_emit_ia_multi_vgt_param()
3769       si_get_ia_multi_vgt_param(cmd_buffer, instanced_draw, indirect_draw, count_from_stream_output,  in si_emit_ia_multi_vgt_param()
3774          radeon_set_uconfig_reg_idx(cmd_buffer->device->physical_device, cs,  in si_emit_ia_multi_vgt_param()
3786 radv_emit_draw_registers(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *draw_info)  in radv_emit_draw_registers()  argument
3788    struct radeon_info *info = &cmd_buffer->device->physical_device->rad_info;  in radv_emit_draw_registers()
3789    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_emit_draw_registers()
3790    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_emit_draw_registers()
3794       si_emit_ia_multi_vgt_param(cmd_buffer, draw_info->instance_count > 1, draw_info->indirect,  in radv_emit_draw_registers()
3800       uint32_t primitive_reset_index = radv_get_primitive_reset_index(cmd_buffer);  in radv_emit_draw_registers()
3823       radv_cs_add_buffer(cmd_buffer->device->ws, cs, draw_info->strmout_buffer->bo);  in radv_emit_draw_registers()
3828 radv_stage_flush(struct radv_cmd_buffer *cmd_buffer, VkPipelineStageFlags2KHR src_stage_mask)  in radv_stage_flush()  argument
3843       cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;  in radv_stage_flush()
3851       cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;  in radv_stage_flush()
3861       cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;  in radv_stage_flush()
3903 radv_src_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags2KHR src_flags,  in radv_src_access_flush()  argument
3983 radv_dst_access_flush(struct radv_cmd_buffer *cmd_buffer, VkAccessFlags2KHR dst_flags,  in radv_dst_access_flush()  argument
4006       can_skip_buffer_l2_flushes(cmd_buffer->device) && !cmd_buffer->state.rb_noncoherent_dirty;  in radv_dst_access_flush()
4013          if (!cmd_buffer->device->load_grid_size_from_user_sgpr)  in radv_dst_access_flush()
4038          if (!cmd_buffer->device->physical_device->use_llvm && !image)  in radv_dst_access_flush()
4048          if (cmd_buffer->device->physical_device->rad_info.chip_class < GFX9)  in radv_dst_access_flush()
4091 radv_emit_subpass_barrier(struct radv_cmd_buffer *cmd_buffer,  in radv_emit_subpass_barrier()  argument
4094    struct radv_render_pass *pass = cmd_buffer->state.pass;  in radv_emit_subpass_barrier()
4097       struct radv_image_view *iview = cmd_buffer->state.attachments[i].iview;  in radv_emit_subpass_barrier()
4099       cmd_buffer->state.flush_bits |=  in radv_emit_subpass_barrier()
4100          radv_src_access_flush(cmd_buffer, barrier->src_access_mask, iview->image);  in radv_emit_subpass_barrier()
4103    radv_stage_flush(cmd_buffer, barrier->src_stage_mask);  in radv_emit_subpass_barrier()
4106       struct radv_image_view *iview = cmd_buffer->state.attachments[i].iview;  in radv_emit_subpass_barrier()
4108       cmd_buffer->state.flush_bits |=  in radv_emit_subpass_barrier()
4109          radv_dst_access_flush(cmd_buffer, barrier->dst_access_mask, iview->image);  in radv_emit_subpass_barrier()
4114 radv_get_subpass_id(struct radv_cmd_buffer *cmd_buffer)  in radv_get_subpass_id()  argument
4116    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_get_subpass_id()
4127 radv_get_attachment_sample_locations(struct radv_cmd_buffer *cmd_buffer, uint32_t att_idx,  in radv_get_attachment_sample_locations()  argument
4130    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_get_attachment_sample_locations()
4131    uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);  in radv_get_attachment_sample_locations()
4167 radv_handle_subpass_image_transition(struct radv_cmd_buffer *cmd_buffer,  in radv_handle_subpass_image_transition()  argument
4171    struct radv_image_view *view = cmd_buffer->state.attachments[idx].iview;  in radv_handle_subpass_image_transition()
4178    range.layerCount = cmd_buffer->state.framebuffer->layers;  in radv_handle_subpass_image_transition()
4180    if (cmd_buffer->state.subpass->view_mask) {  in radv_handle_subpass_image_transition()
4188       range.layerCount = util_last_bit(cmd_buffer->state.subpass->view_mask);  in radv_handle_subpass_image_transition()
4194    sample_locs = radv_get_attachment_sample_locations(cmd_buffer, idx, begin_subpass);  in radv_handle_subpass_image_transition()
4198    if ((cmd_buffer->state.attachments[idx].current_layout !=  in radv_handle_subpass_image_transition()
4199         cmd_buffer->state.attachments[idx].current_stencil_layout) ||  in radv_handle_subpass_image_transition()
4211       radv_handle_image_transition(cmd_buffer, view->image,  in radv_handle_subpass_image_transition()
4212                                    cmd_buffer->state.attachments[idx].current_layout,  in radv_handle_subpass_image_transition()
4213                                    cmd_buffer->state.attachments[idx].current_in_render_loop,  in radv_handle_subpass_image_transition()
4219          cmd_buffer, view->image, cmd_buffer->state.attachments[idx].current_stencil_layout,  in radv_handle_subpass_image_transition()
4220          cmd_buffer->state.attachments[idx].current_in_render_loop, att.stencil_layout,  in radv_handle_subpass_image_transition()
4223       radv_handle_image_transition(cmd_buffer, view->image,  in radv_handle_subpass_image_transition()
4224                                    cmd_buffer->state.attachments[idx].current_layout,  in radv_handle_subpass_image_transition()
4225                                    cmd_buffer->state.attachments[idx].current_in_render_loop,  in radv_handle_subpass_image_transition()
4229    cmd_buffer->state.attachments[idx].current_layout = att.layout;  in radv_handle_subpass_image_transition()
4230    cmd_buffer->state.attachments[idx].current_stencil_layout = att.stencil_layout;  in radv_handle_subpass_image_transition()
4231    cmd_buffer->state.attachments[idx].current_in_render_loop = att.in_render_loop;  in radv_handle_subpass_image_transition()
4235 radv_cmd_buffer_set_subpass(struct radv_cmd_buffer *cmd_buffer, const struct radv_subpass *subpass)  in radv_cmd_buffer_set_subpass()  argument
4237    cmd_buffer->state.subpass = subpass;  in radv_cmd_buffer_set_subpass()
4239    cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;  in radv_cmd_buffer_set_subpass()
4243 radv_cmd_state_setup_sample_locations(struct radv_cmd_buffer *cmd_buffer,  in radv_cmd_state_setup_sample_locations()  argument
4249    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_cmd_state_setup_sample_locations()
4260       struct radv_image *image = cmd_buffer->state.attachments[att_idx].iview->image;  in radv_cmd_state_setup_sample_locations()
4287       vk_alloc(&cmd_buffer->pool->vk.alloc,  in radv_cmd_state_setup_sample_locations()
4291       cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;  in radv_cmd_state_setup_sample_locations()
4292       return cmd_buffer->record_result;  in radv_cmd_state_setup_sample_locations()
4317 radv_cmd_state_setup_attachments(struct radv_cmd_buffer *cmd_buffer, struct radv_render_pass *pass,  in radv_cmd_state_setup_attachments()  argument
4321    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_cmd_state_setup_attachments()
4334       vk_alloc(&cmd_buffer->pool->vk.alloc, pass->attachment_count * sizeof(state->attachments[0]),  in radv_cmd_state_setup_attachments()
4337       cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;  in radv_cmd_state_setup_attachments()
4338       return cmd_buffer->record_result;  in radv_cmd_state_setup_attachments()
4388          radv_initialise_ds_surface(cmd_buffer->device, &state->attachments[i].ds, iview);  in radv_cmd_state_setup_attachments()
4390          radv_initialise_color_surface(cmd_buffer->device, &state->attachments[i].cb, iview);  in radv_cmd_state_setup_attachments()
4410          struct radv_cmd_buffer *cmd_buffer =  in radv_AllocateCommandBuffers()  local
4413          list_del(&cmd_buffer->pool_link);  in radv_AllocateCommandBuffers()
4414          list_addtail(&cmd_buffer->pool_link, &pool->cmd_buffers);  in radv_AllocateCommandBuffers()
4416          result = radv_reset_cmd_buffer(cmd_buffer);  in radv_AllocateCommandBuffers()
4417          vk_command_buffer_finish(&cmd_buffer->vk);  in radv_AllocateCommandBuffers()
4419             vk_command_buffer_init(&cmd_buffer->vk, &pool->vk, pAllocateInfo->level);  in radv_AllocateCommandBuffers()
4423          pCommandBuffers[i] = radv_cmd_buffer_to_handle(cmd_buffer);  in radv_AllocateCommandBuffers()
4456       RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, pCommandBuffers[i]);  in radv_FreeCommandBuffers()
4458       if (!cmd_buffer)  in radv_FreeCommandBuffers()
4460       assert(cmd_buffer->pool == pool);  in radv_FreeCommandBuffers()
4462       list_del(&cmd_buffer->pool_link);  in radv_FreeCommandBuffers()
4463       list_addtail(&cmd_buffer->pool_link, &pool->free_cmd_buffers);  in radv_FreeCommandBuffers()
4470    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_ResetCommandBuffer()
4471    return radv_reset_cmd_buffer(cmd_buffer);  in radv_ResetCommandBuffer()
4475 radv_inherit_dynamic_rendering(struct radv_cmd_buffer *cmd_buffer,  in radv_inherit_dynamic_rendering()  argument
4560       radv_CreateRenderPass2(radv_device_to_handle(cmd_buffer->device), &rp_create_info, NULL, &rp);  in radv_inherit_dynamic_rendering()
4562       cmd_buffer->record_result = result;  in radv_inherit_dynamic_rendering()
4566    cmd_buffer->state.pass = radv_render_pass_from_handle(rp);  in radv_inherit_dynamic_rendering()
4567    cmd_buffer->state.own_render_pass = true;  in radv_inherit_dynamic_rendering()
4573    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_BeginCommandBuffer()
4576    if (cmd_buffer->status != RADV_CMD_BUFFER_STATUS_INITIAL) {  in radv_BeginCommandBuffer()
4580       result = radv_reset_cmd_buffer(cmd_buffer);  in radv_BeginCommandBuffer()
4585    memset(&cmd_buffer->state, 0, sizeof(cmd_buffer->state));  in radv_BeginCommandBuffer()
4586    cmd_buffer->state.last_primitive_reset_en = -1;  in radv_BeginCommandBuffer()
4587    cmd_buffer->state.last_index_type = -1;  in radv_BeginCommandBuffer()
4588    cmd_buffer->state.last_num_instances = -1;  in radv_BeginCommandBuffer()
4589    cmd_buffer->state.last_vertex_offset = -1;  in radv_BeginCommandBuffer()
4590    cmd_buffer->state.last_first_instance = -1;  in radv_BeginCommandBuffer()
4591    cmd_buffer->state.last_drawid = -1;  in radv_BeginCommandBuffer()
4592    cmd_buffer->state.predication_type = -1;  in radv_BeginCommandBuffer()
4593    cmd_buffer->state.last_sx_ps_downconvert = -1;  in radv_BeginCommandBuffer()
4594    cmd_buffer->state.last_sx_blend_opt_epsilon = -1;  in radv_BeginCommandBuffer()
4595    cmd_buffer->state.last_sx_blend_opt_control = -1;  in radv_BeginCommandBuffer()
4596    cmd_buffer->state.last_nggc_settings = -1;  in radv_BeginCommandBuffer()
4597    cmd_buffer->state.last_nggc_settings_sgpr_idx = -1;  in radv_BeginCommandBuffer()
4598    cmd_buffer->state.mesh_shading = false;  in radv_BeginCommandBuffer()
4599    cmd_buffer->state.last_vrs_rates = -1;  in radv_BeginCommandBuffer()
4600    cmd_buffer->state.last_vrs_rates_sgpr_idx = -1;  in radv_BeginCommandBuffer()
4601    cmd_buffer->usage_flags = pBeginInfo->flags;  in radv_BeginCommandBuffer()
4603    if (cmd_buffer->vk.level == VK_COMMAND_BUFFER_LEVEL_SECONDARY &&  in radv_BeginCommandBuffer()
4609       cmd_buffer->state.framebuffer =  in radv_BeginCommandBuffer()
4613          cmd_buffer->state.pass =  in radv_BeginCommandBuffer()
4615          assert(pBeginInfo->pInheritanceInfo->subpass < cmd_buffer->state.pass->subpass_count);  in radv_BeginCommandBuffer()
4616          subpass = &cmd_buffer->state.pass->subpasses[pBeginInfo->pInheritanceInfo->subpass];  in radv_BeginCommandBuffer()
4622             radv_inherit_dynamic_rendering(cmd_buffer, pBeginInfo->pInheritanceInfo, dyn_info);  in radv_BeginCommandBuffer()
4623             subpass = &cmd_buffer->state.pass->subpasses[0];  in radv_BeginCommandBuffer()
4627       if (cmd_buffer->state.framebuffer) {  in radv_BeginCommandBuffer()
4628          result = radv_cmd_state_setup_attachments(cmd_buffer, cmd_buffer->state.pass, NULL, NULL);  in radv_BeginCommandBuffer()
4633       cmd_buffer->state.inherited_pipeline_statistics =  in radv_BeginCommandBuffer()
4636       if (cmd_buffer->state.pass) {  in radv_BeginCommandBuffer()
4637          cmd_buffer->state.subpass = subpass;  in radv_BeginCommandBuffer()
4638          if (cmd_buffer->state.framebuffer)  in radv_BeginCommandBuffer()
4639             cmd_buffer->state.dirty |= RADV_CMD_DIRTY_FRAMEBUFFER;  in radv_BeginCommandBuffer()
4643    if (unlikely(cmd_buffer->device->trace_bo))  in radv_BeginCommandBuffer()
4644       radv_cmd_buffer_trace_emit(cmd_buffer);  in radv_BeginCommandBuffer()
4646    radv_describe_begin_cmd_buffer(cmd_buffer);  in radv_BeginCommandBuffer()
4648    cmd_buffer->status = RADV_CMD_BUFFER_STATUS_RECORDING;  in radv_BeginCommandBuffer()
4668    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdBindVertexBuffers2EXT()
4669    struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;  in radv_CmdBindVertexBuffers2EXT()
4670    const struct radv_vs_input_state *state = &cmd_buffer->state.dynamic_vs_input;  in radv_CmdBindVertexBuffers2EXT()
4676    cmd_buffer->state.vbo_misaligned_mask = state->misaligned_mask;  in radv_CmdBindVertexBuffers2EXT()
4677    enum chip_class chip = cmd_buffer->device->physical_device->rad_info.chip_class;  in radv_CmdBindVertexBuffers2EXT()
4691             cmd_buffer->state.vbo_misaligned_mask &= ~bit;  in radv_CmdBindVertexBuffers2EXT()
4692             cmd_buffer->state.vbo_bound_mask &= ~bit;  in radv_CmdBindVertexBuffers2EXT()
4694             cmd_buffer->state.vbo_bound_mask |= bit;  in radv_CmdBindVertexBuffers2EXT()
4697                   cmd_buffer->state.vbo_misaligned_mask |= bit;  in radv_CmdBindVertexBuffers2EXT()
4699                   cmd_buffer->state.vbo_misaligned_mask &= ~bit;  in radv_CmdBindVertexBuffers2EXT()
4703                cmd_buffer->state.vbo_misaligned_mask |= bit;  in radv_CmdBindVertexBuffers2EXT()
4712          radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, vb[idx].buffer->bo);  in radv_CmdBindVertexBuffers2EXT()
4716    cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER |  in radv_CmdBindVertexBuffers2EXT()
4754    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdBindIndexBuffer()
4757    cmd_buffer->state.index_buffer = index_buffer;  in radv_CmdBindIndexBuffer()
4758    cmd_buffer->state.index_offset = offset;  in radv_CmdBindIndexBuffer()
4759    cmd_buffer->state.index_type = vk_to_index_type(indexType);  in radv_CmdBindIndexBuffer()
4760    cmd_buffer->state.index_va = radv_buffer_get_va(index_buffer->bo);  in radv_CmdBindIndexBuffer()
4761    cmd_buffer->state.index_va += index_buffer->offset + offset;  in radv_CmdBindIndexBuffer()
4764    cmd_buffer->state.max_index_count = (index_buffer->size - offset) / index_size;  in radv_CmdBindIndexBuffer()
4765    cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;  in radv_CmdBindIndexBuffer()
4766    radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, index_buffer->bo);  in radv_CmdBindIndexBuffer()
4770 radv_bind_descriptor_set(struct radv_cmd_buffer *cmd_buffer, VkPipelineBindPoint bind_point,  in radv_bind_descriptor_set()  argument
4773    struct radeon_winsys *ws = cmd_buffer->device->ws;  in radv_bind_descriptor_set()
4775    radv_set_descriptor_set(cmd_buffer, bind_point, set, idx);  in radv_bind_descriptor_set()
4780    if (!cmd_buffer->device->use_global_bo_list) {  in radv_bind_descriptor_set()
4783             radv_cs_add_buffer(ws, cmd_buffer->cs, set->descriptors[j]);  in radv_bind_descriptor_set()
4787       radv_cs_add_buffer(ws, cmd_buffer->cs, set->header.bo);  in radv_bind_descriptor_set()
4796    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdBindDescriptorSets()
4801       cmd_buffer->device->instance->debug_flags & RADV_DEBUG_NO_DYNAMIC_BOUNDS;  in radv_CmdBindDescriptorSets()
4803       radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);  in radv_CmdBindDescriptorSets()
4813          radv_bind_descriptor_set(cmd_buffer, pipelineBindPoint, set, set_idx);  in radv_CmdBindDescriptorSets()
4833             if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10) {  in radv_CmdBindDescriptorSets()
4842          cmd_buffer->push_constant_stages |= set->header.layout->dynamic_shader_stages;  in radv_CmdBindDescriptorSets()
4848 radv_init_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer, struct radv_descriptor_set *set,  in radv_init_push_descriptor_set()  argument
4853       radv_get_descriptors_state(cmd_buffer, bind_point);  in radv_init_push_descriptor_set()
4858          radv_descriptor_set_layout_unref(cmd_buffer->device, set->header.layout);  in radv_init_push_descriptor_set()
4873          cmd_buffer->record_result = VK_ERROR_OUT_OF_HOST_MEMORY;  in radv_init_push_descriptor_set()
4884 radv_meta_push_descriptor_set(struct radv_cmd_buffer *cmd_buffer,  in radv_meta_push_descriptor_set()  argument
4891       (struct radv_descriptor_set *)&cmd_buffer->meta_push_descriptors;  in radv_meta_push_descriptor_set()
4900    if (!radv_cmd_buffer_upload_alloc(cmd_buffer, push_set->header.size, &bo_offset,  in radv_meta_push_descriptor_set()
4904    push_set->header.va = radv_buffer_get_va(cmd_buffer->upload.upload_bo);  in radv_meta_push_descriptor_set()
4907    radv_cmd_update_descriptor_sets(cmd_buffer->device, cmd_buffer,  in radv_meta_push_descriptor_set()
4911    radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);  in radv_meta_push_descriptor_set()
4919    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdPushDescriptorSetKHR()
4922       radv_get_descriptors_state(cmd_buffer, pipelineBindPoint);  in radv_CmdPushDescriptorSetKHR()
4928    if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout,  in radv_CmdPushDescriptorSetKHR()
4940    radv_cmd_update_descriptor_sets(cmd_buffer->device, cmd_buffer,  in radv_CmdPushDescriptorSetKHR()
4944    radv_set_descriptor_set(cmd_buffer, pipelineBindPoint, push_set, set);  in radv_CmdPushDescriptorSetKHR()
4953    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdPushDescriptorSetWithTemplateKHR()
4957       radv_get_descriptors_state(cmd_buffer, templ->bind_point);  in radv_CmdPushDescriptorSetWithTemplateKHR()
4963    if (!radv_init_push_descriptor_set(cmd_buffer, push_set, layout->set[set].layout,  in radv_CmdPushDescriptorSetWithTemplateKHR()
4967    radv_cmd_update_descriptor_set_with_template(cmd_buffer->device, cmd_buffer, push_set,  in radv_CmdPushDescriptorSetWithTemplateKHR()
4970    radv_set_descriptor_set(cmd_buffer, templ->bind_point, push_set, set);  in radv_CmdPushDescriptorSetWithTemplateKHR()
4979    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdPushConstants()
4980    memcpy(cmd_buffer->push_constants + offset, pValues, size);  in radv_CmdPushConstants()
4981    cmd_buffer->push_constant_stages |= stageFlags;  in radv_CmdPushConstants()
4987    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_EndCommandBuffer()
4989    radv_emit_mip_change_flush_default(cmd_buffer);  in radv_EndCommandBuffer()
4991    if (cmd_buffer->qf != RADV_QUEUE_TRANSFER) {  in radv_EndCommandBuffer()
4992       if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX6)  in radv_EndCommandBuffer()
4993          cmd_buffer->state.flush_bits |=  in radv_EndCommandBuffer()
4999       cmd_buffer->state.flush_bits |= cmd_buffer->active_query_flush_bits;  in radv_EndCommandBuffer()
5004       if (cmd_buffer->state.rb_noncoherent_dirty && can_skip_buffer_l2_flushes(cmd_buffer->device))  in radv_EndCommandBuffer()
5005          cmd_buffer->state.flush_bits |= radv_src_access_flush(  in radv_EndCommandBuffer()
5006             cmd_buffer,  in radv_EndCommandBuffer()
5015       if (cmd_buffer->gds_needed)  in radv_EndCommandBuffer()
5016          cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH;  in radv_EndCommandBuffer()
5018       si_emit_cache_flush(cmd_buffer);  in radv_EndCommandBuffer()
5024    si_cp_dma_wait_for_idle(cmd_buffer);  in radv_EndCommandBuffer()
5026    radv_describe_end_cmd_buffer(cmd_buffer);  in radv_EndCommandBuffer()
5028    vk_free(&cmd_buffer->pool->vk.alloc, cmd_buffer->state.attachments);  in radv_EndCommandBuffer()
5029    vk_free(&cmd_buffer->pool->vk.alloc, cmd_buffer->state.subpass_sample_locs);  in radv_EndCommandBuffer()
5031    VkResult result = cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs);  in radv_EndCommandBuffer()
5033       return vk_error(cmd_buffer, result);  in radv_EndCommandBuffer()
5035    cmd_buffer->status = RADV_CMD_BUFFER_STATUS_EXECUTABLE;  in radv_EndCommandBuffer()
5037    return cmd_buffer->record_result;  in radv_EndCommandBuffer()
5041 radv_emit_compute_pipeline(struct radv_cmd_buffer *cmd_buffer, struct radv_pipeline *pipeline)  in radv_emit_compute_pipeline()  argument
5043    if (pipeline == cmd_buffer->state.emitted_compute_pipeline)  in radv_emit_compute_pipeline()
5048    cmd_buffer->state.emitted_compute_pipeline = pipeline;  in radv_emit_compute_pipeline()
5050    radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->cs.cdw);  in radv_emit_compute_pipeline()
5051    radeon_emit_array(cmd_buffer->cs, pipeline->cs.buf, pipeline->cs.cdw);  in radv_emit_compute_pipeline()
5053    cmd_buffer->compute_scratch_size_per_wave_needed =  in radv_emit_compute_pipeline()
5054       MAX2(cmd_buffer->compute_scratch_size_per_wave_needed, pipeline->scratch_bytes_per_wave);  in radv_emit_compute_pipeline()
5055    cmd_buffer->compute_scratch_waves_wanted =  in radv_emit_compute_pipeline()
5056       MAX2(cmd_buffer->compute_scratch_waves_wanted, pipeline->max_waves);  in radv_emit_compute_pipeline()
5058    radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, pipeline->slab->alloc->arena->bo);  in radv_emit_compute_pipeline()
5060    if (unlikely(cmd_buffer->device->trace_bo))  in radv_emit_compute_pipeline()
5061       radv_save_pipeline(cmd_buffer, pipeline);  in radv_emit_compute_pipeline()
5065 radv_mark_descriptor_sets_dirty(struct radv_cmd_buffer *cmd_buffer, VkPipelineBindPoint bind_point)  in radv_mark_descriptor_sets_dirty()  argument
5068       radv_get_descriptors_state(cmd_buffer, bind_point);  in radv_mark_descriptor_sets_dirty()
5077    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdBindPipeline()
5082       if (cmd_buffer->state.compute_pipeline == pipeline)  in radv_CmdBindPipeline()
5084       radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);  in radv_CmdBindPipeline()
5086       cmd_buffer->state.compute_pipeline = pipeline;  in radv_CmdBindPipeline()
5087       cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;  in radv_CmdBindPipeline()
5090       if (cmd_buffer->state.rt_pipeline == pipeline)  in radv_CmdBindPipeline()
5092       radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);  in radv_CmdBindPipeline()
5094       cmd_buffer->state.rt_pipeline = pipeline;  in radv_CmdBindPipeline()
5095       cmd_buffer->push_constant_stages |=  in radv_CmdBindPipeline()
5099       radv_set_rt_stack_size(cmd_buffer, cmd_buffer->state.rt_stack_size);  in radv_CmdBindPipeline()
5102       if (cmd_buffer->state.pipeline == pipeline)  in radv_CmdBindPipeline()
5104       radv_mark_descriptor_sets_dirty(cmd_buffer, pipelineBindPoint);  in radv_CmdBindPipeline()
5107          !pipeline || !cmd_buffer->state.pipeline ||  in radv_CmdBindPipeline()
5108          cmd_buffer->state.pipeline->graphics.vtx_emit_num != pipeline->graphics.vtx_emit_num ||  in radv_CmdBindPipeline()
5109          cmd_buffer->state.pipeline->graphics.vtx_base_sgpr != pipeline->graphics.vtx_base_sgpr;  in radv_CmdBindPipeline()
5110       cmd_buffer->state.pipeline = pipeline;  in radv_CmdBindPipeline()
5115       if (mesh_shading != cmd_buffer->state.mesh_shading) {  in radv_CmdBindPipeline()
5119          cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_FRAGMENT_SHADING_RATE |  in radv_CmdBindPipeline()
5123       cmd_buffer->state.mesh_shading = mesh_shading;  in radv_CmdBindPipeline()
5124       cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE | RADV_CMD_DIRTY_DYNAMIC_VERTEX_INPUT;  in radv_CmdBindPipeline()
5125       cmd_buffer->push_constant_stages |= pipeline->active_stages;  in radv_CmdBindPipeline()
5129          cmd_buffer->state.last_first_instance = -1;  in radv_CmdBindPipeline()
5130          cmd_buffer->state.last_vertex_offset = -1;  in radv_CmdBindPipeline()
5131          cmd_buffer->state.last_drawid = -1;  in radv_CmdBindPipeline()
5135       cmd_buffer->state.prefetch_L2_mask |= RADV_PREFETCH_SHADERS;  in radv_CmdBindPipeline()
5137       if (cmd_buffer->device->physical_device->rad_info.has_vgt_flush_ngg_legacy_bug &&  in radv_CmdBindPipeline()
5138           cmd_buffer->state.emitted_pipeline &&  in radv_CmdBindPipeline()
5139           cmd_buffer->state.emitted_pipeline->graphics.is_ngg &&  in radv_CmdBindPipeline()
5140           !cmd_buffer->state.pipeline->graphics.is_ngg) {  in radv_CmdBindPipeline()
5146          cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_FLUSH;  in radv_CmdBindPipeline()
5149       radv_bind_dynamic_state(cmd_buffer, &pipeline->dynamic_state);  in radv_CmdBindPipeline()
5151       if (pipeline->graphics.esgs_ring_size > cmd_buffer->esgs_ring_size_needed)  in radv_CmdBindPipeline()
5152          cmd_buffer->esgs_ring_size_needed = pipeline->graphics.esgs_ring_size;  in radv_CmdBindPipeline()
5153       if (pipeline->graphics.gsvs_ring_size > cmd_buffer->gsvs_ring_size_needed)  in radv_CmdBindPipeline()
5154          cmd_buffer->gsvs_ring_size_needed = pipeline->graphics.gsvs_ring_size;  in radv_CmdBindPipeline()
5157          cmd_buffer->tess_rings_needed = true;  in radv_CmdBindPipeline()
5169    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetViewport()
5170    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetViewport()
5194    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetScissor()
5195    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetScissor()
5213    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetLineWidth()
5215    cmd_buffer->state.dynamic.line_width = lineWidth;  in radv_CmdSetLineWidth()
5216    cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_LINE_WIDTH;  in radv_CmdSetLineWidth()
5223    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetDepthBias()
5224    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetDepthBias()
5236    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetBlendConstants()
5237    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetBlendConstants()
5247    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetDepthBounds()
5248    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetDepthBounds()
5260    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetStencilCompareMask()
5261    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetStencilCompareMask()
5275    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetStencilWriteMask()
5276    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetStencilWriteMask()
5290    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetStencilReference()
5293       cmd_buffer->state.dynamic.stencil_reference.front = reference;  in radv_CmdSetStencilReference()
5295       cmd_buffer->state.dynamic.stencil_reference.back = reference;  in radv_CmdSetStencilReference()
5297    cmd_buffer->state.dirty |= RADV_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE;  in radv_CmdSetStencilReference()
5304    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetDiscardRectangleEXT()
5305    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetDiscardRectangleEXT()
5321    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetSampleLocationsEXT()
5322    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetSampleLocationsEXT()
5339    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetLineStippleEXT()
5340    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetLineStippleEXT()
5351    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetCullModeEXT()
5352    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetCullModeEXT()
5362    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetFrontFaceEXT()
5363    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetFrontFaceEXT()
5374    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetPrimitiveTopologyEXT()
5375    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetPrimitiveTopologyEXT()
5401    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetDepthTestEnableEXT()
5402    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetDepthTestEnableEXT()
5412    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetDepthWriteEnableEXT()
5413    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetDepthWriteEnableEXT()
5423    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetDepthCompareOpEXT()
5424    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetDepthCompareOpEXT()
5434    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetDepthBoundsTestEnableEXT()
5435    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetDepthBoundsTestEnableEXT()
5445    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetStencilTestEnableEXT()
5446    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetStencilTestEnableEXT()
5458    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetStencilOpEXT()
5459    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetStencilOpEXT()
5482    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetFragmentShadingRateKHR()
5483    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetFragmentShadingRateKHR()
5495    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetDepthBiasEnableEXT()
5496    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetDepthBiasEnableEXT()
5506    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetPrimitiveRestartEnableEXT()
5507    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetPrimitiveRestartEnableEXT()
5518    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetRasterizerDiscardEnableEXT()
5519    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetRasterizerDiscardEnableEXT()
5535    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetLogicOpEXT()
5536    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetLogicOpEXT()
5548    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetColorWriteEnableEXT()
5549    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_CmdSetColorWriteEnableEXT()
5569    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetVertexInputEXT()
5570    struct radv_vs_input_state *state = &cmd_buffer->state.dynamic_vs_input;  in radv_CmdSetVertexInputEXT()
5576    cmd_buffer->state.vbo_misaligned_mask = 0;  in radv_CmdSetVertexInputEXT()
5580    enum chip_class chip = cmd_buffer->device->physical_device->rad_info.chip_class;  in radv_CmdSetVertexInputEXT()
5598       cmd_buffer->vertex_bindings[attrib->binding].stride = binding->stride;  in radv_CmdSetVertexInputEXT()
5601       radv_translate_vertex_format(cmd_buffer->device->physical_device, attrib->format, format_desc,  in radv_CmdSetVertexInputEXT()
5611          const struct radv_vertex_binding *vb = cmd_buffer->vertex_bindings;  in radv_CmdSetVertexInputEXT()
5615             if (cmd_buffer->state.vbo_bound_mask & bit)  in radv_CmdSetVertexInputEXT()
5616                cmd_buffer->state.vbo_misaligned_mask |= bit;  in radv_CmdSetVertexInputEXT()
5619             if (cmd_buffer->state.vbo_bound_mask & bit &&  in radv_CmdSetVertexInputEXT()
5621                cmd_buffer->state.vbo_misaligned_mask |= bit;  in radv_CmdSetVertexInputEXT()
5634    cmd_buffer->state.dirty |= RADV_CMD_DIRTY_VERTEX_BUFFER |  in radv_CmdSetVertexInputEXT()
5795    list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer, &pool->cmd_buffers, pool_link)  in radv_DestroyCommandPool()
5797       radv_destroy_cmd_buffer(cmd_buffer);  in radv_DestroyCommandPool()
5800    list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer, &pool->free_cmd_buffers, pool_link)  in radv_DestroyCommandPool()
5802       radv_destroy_cmd_buffer(cmd_buffer);  in radv_DestroyCommandPool()
5815    list_for_each_entry(struct radv_cmd_buffer, cmd_buffer, &pool->cmd_buffers, pool_link)  in radv_ResetCommandPool()
5817       result = radv_reset_cmd_buffer(cmd_buffer);  in radv_ResetCommandPool()
5830    list_for_each_entry_safe(struct radv_cmd_buffer, cmd_buffer, &pool->free_cmd_buffers, pool_link)  in radv_TrimCommandPool()
5832       radv_destroy_cmd_buffer(cmd_buffer);  in radv_TrimCommandPool()
5837 radv_cmd_buffer_begin_subpass(struct radv_cmd_buffer *cmd_buffer, uint32_t subpass_id)  in radv_cmd_buffer_begin_subpass()  argument
5839    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_cmd_buffer_begin_subpass()
5842    ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4096);  in radv_cmd_buffer_begin_subpass()
5844    radv_emit_subpass_barrier(cmd_buffer, &subpass->start_barrier);  in radv_cmd_buffer_begin_subpass()
5846    radv_cmd_buffer_set_subpass(cmd_buffer, subpass);  in radv_cmd_buffer_begin_subpass()
5848    radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);  in radv_cmd_buffer_begin_subpass()
5855       radv_handle_subpass_image_transition(cmd_buffer, subpass->attachments[i], true);  in radv_cmd_buffer_begin_subpass()
5858    radv_describe_barrier_end(cmd_buffer);  in radv_cmd_buffer_begin_subpass()
5860    radv_cmd_buffer_clear_subpass(cmd_buffer);  in radv_cmd_buffer_begin_subpass()
5864       struct radv_image_view *vrs_iview = cmd_buffer->state.attachments[idx].iview;  in radv_cmd_buffer_begin_subpass()
5871          struct radv_image_view *ds_iview = cmd_buffer->state.attachments[ds_idx].iview;  in radv_cmd_buffer_begin_subpass()
5886 …       radv_buffer_init(&htile_buffer, cmd_buffer->device, ds_image->bo, htile_size, htile_offset);  in radv_cmd_buffer_begin_subpass()
5889          radv_copy_vrs_htile(cmd_buffer, vrs_iview->image, &extent, ds_image, &htile_buffer, true);  in radv_cmd_buffer_begin_subpass()
5896          struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;  in radv_cmd_buffer_begin_subpass()
5897          struct radv_image *ds_image = radv_cmd_buffer_get_vrs_image(cmd_buffer);  in radv_cmd_buffer_begin_subpass()
5901             struct radv_buffer *htile_buffer = cmd_buffer->device->vrs.buffer;  in radv_cmd_buffer_begin_subpass()
5909 …         radv_copy_vrs_htile(cmd_buffer, vrs_iview->image, &extent, ds_image, htile_buffer, false);  in radv_cmd_buffer_begin_subpass()
5914    assert(cmd_buffer->cs->cdw <= cdw_max);  in radv_cmd_buffer_begin_subpass()
5918 radv_mark_noncoherent_rb(struct radv_cmd_buffer *cmd_buffer)  in radv_mark_noncoherent_rb()  argument
5920    const struct radv_subpass *subpass = cmd_buffer->state.subpass;  in radv_mark_noncoherent_rb()
5923    if (!cmd_buffer->state.attachments) {  in radv_mark_noncoherent_rb()
5924       cmd_buffer->state.rb_noncoherent_dirty = true;  in radv_mark_noncoherent_rb()
5932       if (!cmd_buffer->state.attachments[a].iview->image->l2_coherent) {  in radv_mark_noncoherent_rb()
5933          cmd_buffer->state.rb_noncoherent_dirty = true;  in radv_mark_noncoherent_rb()
5938        !cmd_buffer->state.attachments[subpass->depth_stencil_attachment->attachment]  in radv_mark_noncoherent_rb()
5940       cmd_buffer->state.rb_noncoherent_dirty = true;  in radv_mark_noncoherent_rb()
5944 radv_cmd_buffer_restore_subpass(struct radv_cmd_buffer *cmd_buffer,  in radv_cmd_buffer_restore_subpass()  argument
5947    radv_mark_noncoherent_rb(cmd_buffer);  in radv_cmd_buffer_restore_subpass()
5948    radv_cmd_buffer_set_subpass(cmd_buffer, subpass);  in radv_cmd_buffer_restore_subpass()
5952 radv_cmd_buffer_end_subpass(struct radv_cmd_buffer *cmd_buffer)  in radv_cmd_buffer_end_subpass()  argument
5954    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_cmd_buffer_end_subpass()
5956    uint32_t subpass_id = radv_get_subpass_id(cmd_buffer);  in radv_cmd_buffer_end_subpass()
5958    radv_cmd_buffer_resolve_subpass(cmd_buffer);  in radv_cmd_buffer_end_subpass()
5960    radv_describe_barrier_start(cmd_buffer, RGP_BARRIER_EXTERNAL_RENDER_PASS_SYNC);  in radv_cmd_buffer_end_subpass()
5973       radv_handle_subpass_image_transition(cmd_buffer, att, false);  in radv_cmd_buffer_end_subpass()
5976    radv_describe_barrier_end(cmd_buffer);  in radv_cmd_buffer_end_subpass()
5980 radv_cmd_buffer_begin_render_pass(struct radv_cmd_buffer *cmd_buffer,  in radv_cmd_buffer_begin_render_pass()  argument
5988    cmd_buffer->state.framebuffer = framebuffer;  in radv_cmd_buffer_begin_render_pass()
5989    cmd_buffer->state.pass = pass;  in radv_cmd_buffer_begin_render_pass()
5990    cmd_buffer->state.render_area = pRenderPassBegin->renderArea;  in radv_cmd_buffer_begin_render_pass()
5992    result = radv_cmd_state_setup_attachments(cmd_buffer, pass, pRenderPassBegin, extra_info);  in radv_cmd_buffer_begin_render_pass()
5996    result = radv_cmd_state_setup_sample_locations(cmd_buffer, pass, pRenderPassBegin);  in radv_cmd_buffer_begin_render_pass()
6006    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdBeginRenderPass2()
6008    radv_cmd_buffer_begin_render_pass(cmd_buffer, pRenderPassBeginInfo, NULL);  in radv_CmdBeginRenderPass2()
6010    radv_cmd_buffer_begin_subpass(cmd_buffer, 0);  in radv_CmdBeginRenderPass2()
6017    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdNextSubpass2()
6019    radv_mark_noncoherent_rb(cmd_buffer);  in radv_CmdNextSubpass2()
6021    uint32_t prev_subpass = radv_get_subpass_id(cmd_buffer);  in radv_CmdNextSubpass2()
6022    radv_cmd_buffer_end_subpass(cmd_buffer);  in radv_CmdNextSubpass2()
6023    radv_cmd_buffer_begin_subpass(cmd_buffer, prev_subpass + 1);  in radv_CmdNextSubpass2()
6027 radv_emit_view_index(struct radv_cmd_buffer *cmd_buffer, unsigned index)  in radv_emit_view_index()  argument
6029    struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;  in radv_emit_view_index()
6038       radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);  in radv_emit_view_index()
6045          radeon_set_sh_reg(cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, index);  in radv_emit_view_index()
6051 radv_cs_emit_draw_packet(struct radv_cmd_buffer *cmd_buffer, uint32_t vertex_count,  in radv_cs_emit_draw_packet()  argument
6054    radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, cmd_buffer->state.predicating));  in radv_cs_emit_draw_packet()
6055    radeon_emit(cmd_buffer->cs, vertex_count);  in radv_cs_emit_draw_packet()
6056    radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX | use_opaque);  in radv_cs_emit_draw_packet()
6067 radv_cs_emit_draw_indexed_packet(struct radv_cmd_buffer *cmd_buffer, uint64_t index_va,  in radv_cs_emit_draw_indexed_packet()  argument
6070    radeon_emit(cmd_buffer->cs, PKT3(PKT3_DRAW_INDEX_2, 4, cmd_buffer->state.predicating));  in radv_cs_emit_draw_indexed_packet()
6071    radeon_emit(cmd_buffer->cs, max_index_count);  in radv_cs_emit_draw_indexed_packet()
6072    radeon_emit(cmd_buffer->cs, index_va);  in radv_cs_emit_draw_indexed_packet()
6073    radeon_emit(cmd_buffer->cs, index_va >> 32);  in radv_cs_emit_draw_indexed_packet()
6074    radeon_emit(cmd_buffer->cs, index_count);  in radv_cs_emit_draw_indexed_packet()
6079    radeon_emit(cmd_buffer->cs, V_0287F0_DI_SRC_SEL_DMA | S_0287F0_NOT_EOP(not_eop));  in radv_cs_emit_draw_indexed_packet()
6084 radv_cs_emit_indirect_draw_packet(struct radv_cmd_buffer *cmd_buffer, bool indexed,  in radv_cs_emit_indirect_draw_packet()  argument
6087    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_cs_emit_indirect_draw_packet()
6089    bool draw_id_enable = cmd_buffer->state.pipeline->graphics.uses_drawid;  in radv_cs_emit_indirect_draw_packet()
6090    uint32_t base_reg = cmd_buffer->state.pipeline->graphics.vtx_base_sgpr;  in radv_cs_emit_indirect_draw_packet()
6092    bool predicating = cmd_buffer->state.predicating;  in radv_cs_emit_indirect_draw_packet()
6093    bool mesh = cmd_buffer->state.mesh_shading;  in radv_cs_emit_indirect_draw_packet()
6097    cmd_buffer->state.last_first_instance = -1;  in radv_cs_emit_indirect_draw_packet()
6098    cmd_buffer->state.last_num_instances = -1;  in radv_cs_emit_indirect_draw_packet()
6099    cmd_buffer->state.last_drawid = -1;  in radv_cs_emit_indirect_draw_packet()
6100    cmd_buffer->state.last_vertex_offset = -1;  in radv_cs_emit_indirect_draw_packet()
6103    if (cmd_buffer->state.pipeline->graphics.uses_baseinstance)  in radv_cs_emit_indirect_draw_packet()
6129       cmd_buffer->state.uses_draw_indirect_multi = true;  in radv_cs_emit_indirect_draw_packet()
6134 radv_emit_userdata_vertex_internal(struct radv_cmd_buffer *cmd_buffer,  in radv_emit_userdata_vertex_internal()  argument
6137    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_emit_userdata_vertex_internal()
6138    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_emit_userdata_vertex_internal()
6157 radv_emit_userdata_vertex(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *info,  in radv_emit_userdata_vertex()  argument
6160    const struct radv_cmd_state *state = &cmd_buffer->state;  in radv_emit_userdata_vertex()
6168       radv_emit_userdata_vertex_internal(cmd_buffer, info, vertex_offset);  in radv_emit_userdata_vertex()
6170       radv_emit_userdata_vertex_internal(cmd_buffer, info, vertex_offset);  in radv_emit_userdata_vertex()
6172       radv_emit_userdata_vertex_internal(cmd_buffer, info, vertex_offset);  in radv_emit_userdata_vertex()
6177 radv_emit_userdata_vertex_drawid(struct radv_cmd_buffer *cmd_buffer, uint32_t vertex_offset, uint32…  in radv_emit_userdata_vertex_drawid()  argument
6179    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_emit_userdata_vertex_drawid()
6180    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_emit_userdata_vertex_drawid()
6190 radv_emit_userdata_mesh(struct radv_cmd_buffer *cmd_buffer,  in radv_emit_userdata_mesh()  argument
6194    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_emit_userdata_mesh()
6195    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_emit_userdata_mesh()
6212 radv_emit_draw_packets_indexed(struct radv_cmd_buffer *cmd_buffer,  in radv_emit_draw_packets_indexed()  argument
6219    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_emit_draw_packets_indexed()
6220    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_emit_draw_packets_indexed()
6224 …const bool can_eop = !uses_drawid && cmd_buffer->device->physical_device->rad_info.chip_class >= G…  in radv_emit_draw_packets_indexed()
6228          radv_emit_userdata_vertex(cmd_buffer, info, *vertexOffset);  in radv_emit_draw_packets_indexed()
6234                 cmd_buffer->device->physical_device->rad_info.has_zero_index_buffer_bug)  in radv_emit_draw_packets_indexed()
6243 …radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, remaining_indexes, draw->indexCount, false);  in radv_emit_draw_packets_indexed()
6246                   radv_emit_view_index(cmd_buffer, view);  in radv_emit_draw_packets_indexed()
6248 …radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, remaining_indexes, draw->indexCount, false);  in radv_emit_draw_packets_indexed()
6258                 cmd_buffer->device->physical_device->rad_info.has_zero_index_buffer_bug)  in radv_emit_draw_packets_indexed()
6263                   radv_emit_userdata_vertex_drawid(cmd_buffer, draw->vertexOffset, i);  in radv_emit_draw_packets_indexed()
6267                radv_emit_userdata_vertex(cmd_buffer, info, draw->vertexOffset);  in radv_emit_draw_packets_indexed()
6272 …radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, remaining_indexes, draw->indexCount, false);  in radv_emit_draw_packets_indexed()
6275                   radv_emit_view_index(cmd_buffer, view);  in radv_emit_draw_packets_indexed()
6277 …radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, remaining_indexes, draw->indexCount, false);  in radv_emit_draw_packets_indexed()
6287          if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX10) {  in radv_emit_draw_packets_indexed()
6299          radv_emit_userdata_vertex(cmd_buffer, info, *vertexOffset);  in radv_emit_draw_packets_indexed()
6305                 cmd_buffer->device->physical_device->rad_info.has_zero_index_buffer_bug)  in radv_emit_draw_packets_indexed()
6311 …radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, remaining_indexes, draw->indexCount, can_eo…  in radv_emit_draw_packets_indexed()
6314                   radv_emit_view_index(cmd_buffer, view);  in radv_emit_draw_packets_indexed()
6316 …radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, remaining_indexes, draw->indexCount, false);  in radv_emit_draw_packets_indexed()
6326                 cmd_buffer->device->physical_device->rad_info.has_zero_index_buffer_bug)  in radv_emit_draw_packets_indexed()
6331             radv_emit_userdata_vertex(cmd_buffer, info, draw->vertexOffset);  in radv_emit_draw_packets_indexed()
6336 …radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, remaining_indexes, draw->indexCount, can_eo…  in radv_emit_draw_packets_indexed()
6339                   radv_emit_view_index(cmd_buffer, view);  in radv_emit_draw_packets_indexed()
6341 …radv_cs_emit_draw_indexed_packet(cmd_buffer, index_va, remaining_indexes, draw->indexCount, false);  in radv_emit_draw_packets_indexed()
6353 radv_emit_direct_draw_packets(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *info,  in radv_emit_direct_draw_packets()  argument
6358    const uint32_t view_mask = cmd_buffer->state.subpass->view_mask;  in radv_emit_direct_draw_packets()
6359    const bool uses_drawid = cmd_buffer->state.pipeline->graphics.uses_drawid;  in radv_emit_direct_draw_packets()
6364          radv_emit_userdata_vertex(cmd_buffer, info, draw->firstVertex);  in radv_emit_direct_draw_packets()
6366          radv_emit_userdata_vertex_drawid(cmd_buffer, draw->firstVertex, uses_drawid ? i : 0);  in radv_emit_direct_draw_packets()
6369          radv_cs_emit_draw_packet(cmd_buffer, draw->vertexCount, use_opaque);  in radv_emit_direct_draw_packets()
6372             radv_emit_view_index(cmd_buffer, view);  in radv_emit_direct_draw_packets()
6373             radv_cs_emit_draw_packet(cmd_buffer, draw->vertexCount, use_opaque);  in radv_emit_direct_draw_packets()
6379        struct radv_cmd_state *state = &cmd_buffer->state;  in radv_emit_direct_draw_packets()
6387 radv_emit_direct_mesh_draw_packet(struct radv_cmd_buffer *cmd_buffer,  in radv_emit_direct_mesh_draw_packet()  argument
6391    const uint32_t view_mask = cmd_buffer->state.subpass->view_mask;  in radv_emit_direct_mesh_draw_packet()
6394    radv_emit_userdata_mesh(cmd_buffer, x, y, z, first_task);  in radv_emit_direct_mesh_draw_packet()
6397       radv_cs_emit_draw_packet(cmd_buffer, count, 0);  in radv_emit_direct_mesh_draw_packet()
6400          radv_emit_view_index(cmd_buffer, view);  in radv_emit_direct_mesh_draw_packet()
6401          radv_cs_emit_draw_packet(cmd_buffer, count, 0);  in radv_emit_direct_mesh_draw_packet()
6407 radv_emit_indirect_draw_packets(struct radv_cmd_buffer *cmd_buffer,  in radv_emit_indirect_draw_packets()  argument
6410    const struct radv_cmd_state *state = &cmd_buffer->state;  in radv_emit_indirect_draw_packets()
6411    struct radeon_winsys *ws = cmd_buffer->device->ws;  in radv_emit_indirect_draw_packets()
6412    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_emit_indirect_draw_packets()
6432       radv_cs_emit_indirect_draw_packet(cmd_buffer, info->indexed, info->count, count_va,  in radv_emit_indirect_draw_packets()
6437          radv_emit_view_index(cmd_buffer, i);  in radv_emit_indirect_draw_packets()
6439          radv_cs_emit_indirect_draw_packet(cmd_buffer, info->indexed, info->count, count_va,  in radv_emit_indirect_draw_packets()
6462 radv_need_late_scissor_emission(struct radv_cmd_buffer *cmd_buffer,  in radv_need_late_scissor_emission()  argument
6465    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_need_late_scissor_emission()
6467    if (!cmd_buffer->device->physical_device->rad_info.has_gfx9_scissor_bug)  in radv_need_late_scissor_emission()
6470    if (cmd_buffer->state.context_roll_without_scissor_emitted || info->strmout_buffer)  in radv_need_late_scissor_emission()
6474       cmd_buffer->state.pipeline->graphics.needed_dynamic_state | ~RADV_CMD_DIRTY_DYNAMIC_ALL;  in radv_need_late_scissor_emission()
6483    if (cmd_buffer->state.dirty & used_states)  in radv_need_late_scissor_emission()
6486    uint32_t primitive_reset_index = radv_get_primitive_reset_index(cmd_buffer);  in radv_need_late_scissor_emission()
6517 radv_get_ngg_culling_settings(struct radv_cmd_buffer *cmd_buffer, bool vp_y_inverted)  in radv_get_ngg_culling_settings()  argument
6519    const struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;  in radv_get_ngg_culling_settings()
6520    const struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;  in radv_get_ngg_culling_settings()
6524        G_028810_DX_RASTERIZATION_KILL(cmd_buffer->state.pipeline->graphics.pa_cl_clip_cntl))  in radv_get_ngg_culling_settings()
6527    uint32_t pa_su_sc_mode_cntl = cmd_buffer->state.pipeline->graphics.pa_su_sc_mode_cntl;  in radv_get_ngg_culling_settings()
6568 radv_emit_ngg_culling_state(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *draw_i…  in radv_emit_ngg_culling_state()  argument
6570    struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;  in radv_emit_ngg_culling_state()
6574    if (!nggc_supported && !cmd_buffer->state.last_nggc_settings) {  in radv_emit_ngg_culling_state()
6578       cmd_buffer->state.last_nggc_settings_sgpr_idx = -1;  in radv_emit_ngg_culling_state()
6587       cmd_buffer->state.dirty &  in radv_emit_ngg_culling_state()
6599    if (!dirty && skip == cmd_buffer->state.last_nggc_skip)  in radv_emit_ngg_culling_state()
6603    cmd_buffer->state.last_nggc_skip = skip;  in radv_emit_ngg_culling_state()
6614    memcpy(vp_scale, cmd_buffer->state.dynamic.viewport.xform[0].scale, 2 * sizeof(float));  in radv_emit_ngg_culling_state()
6615    memcpy(vp_translate, cmd_buffer->state.dynamic.viewport.xform[0].translate, 2 * sizeof(float));  in radv_emit_ngg_culling_state()
6620                             ? radv_get_ngg_culling_settings(cmd_buffer, vp_y_inverted)  in radv_emit_ngg_culling_state()
6624                         (cmd_buffer->state.dirty & RADV_CMD_DIRTY_DYNAMIC_VIEWPORT ||  in radv_emit_ngg_culling_state()
6625                          cmd_buffer->state.last_nggc_settings_sgpr_idx != nggc_sgpr_idx ||  in radv_emit_ngg_culling_state()
6626                          !cmd_buffer->state.last_nggc_settings);  in radv_emit_ngg_culling_state()
6644       radeon_set_sh_reg_seq(cmd_buffer->cs, base_reg + vp_sgpr_idx * 4, 4);  in radv_emit_ngg_culling_state()
6645       radeon_emit_array(cmd_buffer->cs, vp_reg_values, 4);  in radv_emit_ngg_culling_state()
6649                         (cmd_buffer->state.last_nggc_settings != nggc_settings ||  in radv_emit_ngg_culling_state()
6650                          cmd_buffer->state.last_nggc_settings_sgpr_idx != nggc_sgpr_idx);  in radv_emit_ngg_culling_state()
6657       radeon_set_sh_reg(cmd_buffer->cs, base_reg + nggc_sgpr_idx * 4, nggc_settings);  in radv_emit_ngg_culling_state()
6663    if (!!cmd_buffer->state.last_nggc_settings != !!nggc_settings) {  in radv_emit_ngg_culling_state()
6675       if (!(cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) ||  in radv_emit_ngg_culling_state()
6676           cmd_buffer->state.emitted_pipeline == pipeline) {  in radv_emit_ngg_culling_state()
6677          radeon_set_sh_reg(cmd_buffer->cs, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);  in radv_emit_ngg_culling_state()
6681    cmd_buffer->state.last_nggc_settings = nggc_settings;  in radv_emit_ngg_culling_state()
6682    cmd_buffer->state.last_nggc_settings_sgpr_idx = nggc_sgpr_idx;  in radv_emit_ngg_culling_state()
6686 radv_emit_all_graphics_states(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *info,  in radv_emit_all_graphics_states()  argument
6691    if ((cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER) ||  in radv_emit_all_graphics_states()
6692        cmd_buffer->state.emitted_pipeline != cmd_buffer->state.pipeline)  in radv_emit_all_graphics_states()
6693       radv_emit_rbplus_state(cmd_buffer);  in radv_emit_all_graphics_states()
6695    if (cmd_buffer->device->physical_device->use_ngg_culling &&  in radv_emit_all_graphics_states()
6696        cmd_buffer->state.pipeline->graphics.is_ngg)  in radv_emit_all_graphics_states()
6697       radv_emit_ngg_culling_state(cmd_buffer, info);  in radv_emit_all_graphics_states()
6699    if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE)  in radv_emit_all_graphics_states()
6700       radv_emit_graphics_pipeline(cmd_buffer);  in radv_emit_all_graphics_states()
6705    late_scissor_emission = radv_need_late_scissor_emission(cmd_buffer, info);  in radv_emit_all_graphics_states()
6707    if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)  in radv_emit_all_graphics_states()
6708       radv_emit_framebuffer_state(cmd_buffer);  in radv_emit_all_graphics_states()
6711       if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_INDEX_BUFFER)  in radv_emit_all_graphics_states()
6712          radv_emit_index_buffer(cmd_buffer, info->indirect);  in radv_emit_all_graphics_states()
6718       if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {  in radv_emit_all_graphics_states()
6719          cmd_buffer->state.last_index_type = -1;  in radv_emit_all_graphics_states()
6720          cmd_buffer->state.dirty |= RADV_CMD_DIRTY_INDEX_BUFFER;  in radv_emit_all_graphics_states()
6724    if (cmd_buffer->device->force_vrs != RADV_FORCE_VRS_1x1) {  in radv_emit_all_graphics_states()
6725       struct radv_dynamic_state *d = &cmd_buffer->state.dynamic;  in radv_emit_all_graphics_states()
6727 …       cmd_buffer->state.dirty & cmd_buffer->state.emitted_pipeline->graphics.needed_dynamic_state;  in radv_emit_all_graphics_states()
6737          cmd_buffer->state.dirty &= ~RADV_CMD_DIRTY_DYNAMIC_FRAGMENT_SHADING_RATE;  in radv_emit_all_graphics_states()
6741    radv_cmd_buffer_flush_dynamic_state(cmd_buffer, pipeline_is_dirty);  in radv_emit_all_graphics_states()
6743    radv_emit_draw_registers(cmd_buffer, info);  in radv_emit_all_graphics_states()
6746       radv_emit_scissor(cmd_buffer);  in radv_emit_all_graphics_states()
6751 radv_before_draw(struct radv_cmd_buffer *cmd_buffer, const struct radv_draw_info *info, uint32_t dr…  in radv_before_draw()  argument
6753    const bool has_prefetch = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;  in radv_before_draw()
6754    const bool pipeline_is_dirty = (cmd_buffer->state.dirty & RADV_CMD_DIRTY_PIPELINE) &&  in radv_before_draw()
6755                                   cmd_buffer->state.pipeline != cmd_buffer->state.emitted_pipeline;  in radv_before_draw()
6758       radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 4096 + 128 * (drawCount - 1));  in radv_before_draw()
6774    if (cmd_buffer->state.dirty & RADV_CMD_DIRTY_FRAMEBUFFER)  in radv_before_draw()
6775       radv_emit_fb_mip_change_flush(cmd_buffer);  in radv_before_draw()
6780    if (cmd_buffer->state.flush_bits &  in radv_before_draw()
6790       radv_emit_all_graphics_states(cmd_buffer, info, pipeline_is_dirty);  in radv_before_draw()
6791       si_emit_cache_flush(cmd_buffer);  in radv_before_draw()
6794       radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);  in radv_before_draw()
6799       si_emit_cache_flush(cmd_buffer);  in radv_before_draw()
6801       if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {  in radv_before_draw()
6805          radv_emit_prefetch_L2(cmd_buffer, cmd_buffer->state.pipeline, true);  in radv_before_draw()
6808       radv_upload_graphics_shader_descriptors(cmd_buffer, pipeline_is_dirty);  in radv_before_draw()
6810       radv_emit_all_graphics_states(cmd_buffer, info, pipeline_is_dirty);  in radv_before_draw()
6813    radv_describe_draw(cmd_buffer);  in radv_before_draw()
6815       struct radv_cmd_state *state = &cmd_buffer->state;  in radv_before_draw()
6816       struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_before_draw()
6824    assert(cmd_buffer->cs->cdw <= cdw_max);  in radv_before_draw()
6830 radv_after_draw(struct radv_cmd_buffer *cmd_buffer)  in radv_after_draw()  argument
6832    const struct radeon_info *rad_info = &cmd_buffer->device->physical_device->rad_info;  in radv_after_draw()
6833    bool has_prefetch = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;  in radv_after_draw()
6838    if (has_prefetch && cmd_buffer->state.prefetch_L2_mask) {  in radv_after_draw()
6839       radv_emit_prefetch_L2(cmd_buffer, cmd_buffer->state.pipeline, false);  in radv_after_draw()
6845    if (cmd_buffer->state.streamout.streamout_enabled &&  in radv_after_draw()
6848       cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VGT_STREAMOUT_SYNC;  in radv_after_draw()
6851    radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_PS_PARTIAL_FLUSH);  in radv_after_draw()
6855 radv_nv_mesh_indirect_bo(struct radv_cmd_buffer *cmd_buffer,  in radv_nv_mesh_indirect_bo()  argument
6863    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_nv_mesh_indirect_bo()
6864    struct radeon_winsys *ws = cmd_buffer->device->ws;  in radv_nv_mesh_indirect_bo()
6887    radv_cmd_buffer_upload_data(cmd_buffer, dst_stride * draw_count, fill_data, &out_offset);  in radv_nv_mesh_indirect_bo()
6888    const uint64_t new_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + out_offset;  in radv_nv_mesh_indirect_bo()
6905       radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));  in radv_nv_mesh_indirect_bo()
6913       radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, cmd_buffer->state.predicating));  in radv_nv_mesh_indirect_bo()
6928    buf.bo = cmd_buffer->upload.upload_bo;  in radv_nv_mesh_indirect_bo()
6931    assert(cmd_buffer->cs->cdw <= cdw_max);  in radv_nv_mesh_indirect_bo()
6940    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdDraw()
6950    if (!radv_before_draw(cmd_buffer, &info, 1))  in radv_CmdDraw()
6953    radv_emit_direct_draw_packets(cmd_buffer, &info, 1, &minfo, 0, 0);  in radv_CmdDraw()
6954    radv_after_draw(cmd_buffer);  in radv_CmdDraw()
6961    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdDrawMultiEXT()
6974    if (!radv_before_draw(cmd_buffer, &info, drawCount))  in radv_CmdDrawMultiEXT()
6976    radv_emit_direct_draw_packets(cmd_buffer, &info, drawCount, pVertexInfo, 0, stride);  in radv_CmdDrawMultiEXT()
6977    radv_after_draw(cmd_buffer);  in radv_CmdDrawMultiEXT()
6984    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdDrawIndexed()
6994    if (!radv_before_draw(cmd_buffer, &info, 1))  in radv_CmdDrawIndexed()
6997    radv_emit_draw_packets_indexed(cmd_buffer, &info, 1, &minfo, 0, NULL);  in radv_CmdDrawIndexed()
6998    radv_after_draw(cmd_buffer);  in radv_CmdDrawIndexed()
7005    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdDrawMultiIndexedEXT()
7019    if (!radv_before_draw(cmd_buffer, &info, drawCount))  in radv_CmdDrawMultiIndexedEXT()
7021    radv_emit_draw_packets_indexed(cmd_buffer, &info, drawCount, pIndexInfo, stride, pVertexOffset);  in radv_CmdDrawMultiIndexedEXT()
7022    radv_after_draw(cmd_buffer);  in radv_CmdDrawMultiIndexedEXT()
7029    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdDrawIndirect()
7042    if (!radv_before_draw(cmd_buffer, &info, 1))  in radv_CmdDrawIndirect()
7044    radv_emit_indirect_draw_packets(cmd_buffer, &info);  in radv_CmdDrawIndirect()
7045    radv_after_draw(cmd_buffer);  in radv_CmdDrawIndirect()
7052    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdDrawIndexedIndirect()
7065    if (!radv_before_draw(cmd_buffer, &info, 1))  in radv_CmdDrawIndexedIndirect()
7067    radv_emit_indirect_draw_packets(cmd_buffer, &info);  in radv_CmdDrawIndexedIndirect()
7068    radv_after_draw(cmd_buffer);  in radv_CmdDrawIndexedIndirect()
7076    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdDrawIndirectCount()
7091    if (!radv_before_draw(cmd_buffer, &info, 1))  in radv_CmdDrawIndirectCount()
7093    radv_emit_indirect_draw_packets(cmd_buffer, &info);  in radv_CmdDrawIndirectCount()
7094    radv_after_draw(cmd_buffer);  in radv_CmdDrawIndirectCount()
7103    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdDrawIndexedIndirectCount()
7118    if (!radv_before_draw(cmd_buffer, &info, 1))  in radv_CmdDrawIndexedIndirectCount()
7120    radv_emit_indirect_draw_packets(cmd_buffer, &info);  in radv_CmdDrawIndexedIndirectCount()
7121    radv_after_draw(cmd_buffer);  in radv_CmdDrawIndexedIndirectCount()
7127    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdDrawMeshTasksNV()
7129    ASSERTED struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;  in radv_CmdDrawMeshTasksNV()
7149    if (!radv_before_draw(cmd_buffer, &info, 1))  in radv_CmdDrawMeshTasksNV()
7152    radv_emit_direct_mesh_draw_packet(cmd_buffer, taskCount, 1, 1, firstTask);  in radv_CmdDrawMeshTasksNV()
7153    radv_after_draw(cmd_buffer);  in radv_CmdDrawMeshTasksNV()
7160    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdDrawMeshTasksIndirectNV()
7163    ASSERTED struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;  in radv_CmdDrawMeshTasksIndirectNV()
7180    struct radv_buffer buf = radv_nv_mesh_indirect_bo(cmd_buffer, buffer, offset,  in radv_CmdDrawMeshTasksIndirectNV()
7193    if (!radv_before_draw(cmd_buffer, &info, drawCount))  in radv_CmdDrawMeshTasksIndirectNV()
7195    radv_emit_indirect_draw_packets(cmd_buffer, &info);  in radv_CmdDrawMeshTasksIndirectNV()
7196    radv_after_draw(cmd_buffer);  in radv_CmdDrawMeshTasksIndirectNV()
7205    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdDrawMeshTasksIndirectCountNV()
7209    ASSERTED struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;  in radv_CmdDrawMeshTasksIndirectCountNV()
7212    struct radv_buffer buf = radv_nv_mesh_indirect_bo(cmd_buffer, buffer, offset,  in radv_CmdDrawMeshTasksIndirectCountNV()
7226    if (!radv_before_draw(cmd_buffer, &info, maxDrawCount))  in radv_CmdDrawMeshTasksIndirectCountNV()
7228    radv_emit_indirect_draw_packets(cmd_buffer, &info);  in radv_CmdDrawMeshTasksIndirectCountNV()
7229    radv_after_draw(cmd_buffer);  in radv_CmdDrawMeshTasksIndirectCountNV()
7256 radv_emit_dispatch_packets(struct radv_cmd_buffer *cmd_buffer, struct radv_pipeline *pipeline,  in radv_emit_dispatch_packets()  argument
7260    unsigned dispatch_initiator = cmd_buffer->device->dispatch_initiator;  in radv_emit_dispatch_packets()
7261    struct radeon_winsys *ws = cmd_buffer->device->ws;  in radv_emit_dispatch_packets()
7262    bool predicating = cmd_buffer->state.predicating;  in radv_emit_dispatch_packets()
7263    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_emit_dispatch_packets()
7266    radv_describe_dispatch(cmd_buffer, info->blocks[0], info->blocks[1], info->blocks[2]);  in radv_emit_dispatch_packets()
7273       assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);  in radv_emit_dispatch_packets()
7283          if (cmd_buffer->device->load_grid_size_from_user_sgpr) {  in radv_emit_dispatch_packets()
7284             assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10_3);  in radv_emit_dispatch_packets()
7291             radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, reg, info->va, true);  in radv_emit_dispatch_packets()
7295       if (radv_cmd_buffer_uses_mec(cmd_buffer)) {  in radv_emit_dispatch_packets()
7346          if (cmd_buffer->device->load_grid_size_from_user_sgpr) {  in radv_emit_dispatch_packets()
7355             if (!radv_cmd_buffer_upload_data(cmd_buffer, 12, blocks, &offset))  in radv_emit_dispatch_packets()
7358             uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + offset;  in radv_emit_dispatch_packets()
7359             radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs,  in radv_emit_dispatch_packets()
7384    assert(cmd_buffer->cs->cdw <= cdw_max);  in radv_emit_dispatch_packets()
7388 radv_upload_compute_shader_descriptors(struct radv_cmd_buffer *cmd_buffer,  in radv_upload_compute_shader_descriptors()  argument
7392    radv_flush_descriptors(cmd_buffer, VK_SHADER_STAGE_COMPUTE_BIT, pipeline, bind_point);  in radv_upload_compute_shader_descriptors()
7393    radv_flush_constants(cmd_buffer,  in radv_upload_compute_shader_descriptors()
7401 radv_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_info *info,  in radv_dispatch()  argument
7404    bool has_prefetch = cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7;  in radv_dispatch()
7405    bool pipeline_is_dirty = pipeline != cmd_buffer->state.emitted_compute_pipeline;  in radv_dispatch()
7408       cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH |  in radv_dispatch()
7411    if (cmd_buffer->state.flush_bits &  in radv_dispatch()
7421       radv_emit_compute_pipeline(cmd_buffer, pipeline);  in radv_dispatch()
7422       si_emit_cache_flush(cmd_buffer);  in radv_dispatch()
7425       radv_upload_compute_shader_descriptors(cmd_buffer, pipeline, bind_point);  in radv_dispatch()
7427       radv_emit_dispatch_packets(cmd_buffer, pipeline, info);  in radv_dispatch()
7435          radv_emit_shader_prefetch(cmd_buffer, pipeline->shaders[MESA_SHADER_COMPUTE]);  in radv_dispatch()
7441       si_emit_cache_flush(cmd_buffer);  in radv_dispatch()
7444          radv_emit_shader_prefetch(cmd_buffer, pipeline->shaders[MESA_SHADER_COMPUTE]);  in radv_dispatch()
7447       radv_upload_compute_shader_descriptors(cmd_buffer, pipeline, bind_point);  in radv_dispatch()
7449       radv_emit_compute_pipeline(cmd_buffer, pipeline);  in radv_dispatch()
7450       radv_emit_dispatch_packets(cmd_buffer, pipeline, info);  in radv_dispatch()
7461       radv_mark_descriptor_sets_dirty(cmd_buffer, bind_point == VK_PIPELINE_BIND_POINT_COMPUTE  in radv_dispatch()
7467       cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;  in radv_dispatch()
7469    radv_cmd_buffer_after_draw(cmd_buffer, RADV_CMD_FLAG_CS_PARTIAL_FLUSH);  in radv_dispatch()
7473 radv_compute_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_info *info)  in radv_compute_dispatch()  argument
7475    radv_dispatch(cmd_buffer, info, cmd_buffer->state.compute_pipeline,  in radv_compute_dispatch()
7483    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdDispatchBase()
7493    radv_compute_dispatch(cmd_buffer, &info);  in radv_CmdDispatchBase()
7505    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdDispatchIndirect()
7512    radv_compute_dispatch(cmd_buffer, &info);  in radv_CmdDispatchIndirect()
7516 radv_unaligned_dispatch(struct radv_cmd_buffer *cmd_buffer, uint32_t x, uint32_t y, uint32_t z)  in radv_unaligned_dispatch()  argument
7525    radv_compute_dispatch(cmd_buffer, &info);  in radv_unaligned_dispatch()
7529 radv_indirect_dispatch(struct radv_cmd_buffer *cmd_buffer, struct radeon_winsys_bo *bo, uint64_t va)  in radv_indirect_dispatch()  argument
7536    radv_compute_dispatch(cmd_buffer, &info);  in radv_indirect_dispatch()
7540 radv_rt_dispatch(struct radv_cmd_buffer *cmd_buffer, const struct radv_dispatch_info *info)  in radv_rt_dispatch()  argument
7542    radv_dispatch(cmd_buffer, info, cmd_buffer->state.rt_pipeline,  in radv_rt_dispatch()
7547 radv_rt_bind_tables(struct radv_cmd_buffer *cmd_buffer,  in radv_rt_bind_tables()  argument
7550    struct radv_pipeline *pipeline = cmd_buffer->state.rt_pipeline;  in radv_rt_bind_tables()
7556    if (!radv_cmd_buffer_upload_alloc(cmd_buffer, 64, &offset, &ptr))  in radv_rt_bind_tables()
7567    uint64_t va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + offset;  in radv_rt_bind_tables()
7574    radv_emit_shader_pointer(cmd_buffer->device, cmd_buffer->cs, base_reg + loc->sgpr_idx * 4, va,  in radv_rt_bind_tables()
7587    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdTraceRaysKHR()
7602    if (!radv_rt_bind_tables(cmd_buffer, tables)) {  in radv_CmdTraceRaysKHR()
7607       cmd_buffer->state.rt_pipeline, MESA_SHADER_COMPUTE, AC_UD_CS_RAY_LAUNCH_SIZE);  in radv_CmdTraceRaysKHR()
7612       radeon_set_sh_reg_seq(cmd_buffer->cs, R_00B900_COMPUTE_USER_DATA_0 + loc->sgpr_idx * 4, 3);  in radv_CmdTraceRaysKHR()
7613       radeon_emit(cmd_buffer->cs, width);  in radv_CmdTraceRaysKHR()
7614       radeon_emit(cmd_buffer->cs, height);  in radv_CmdTraceRaysKHR()
7615       radeon_emit(cmd_buffer->cs, depth);  in radv_CmdTraceRaysKHR()
7618    radv_rt_dispatch(cmd_buffer, &info);  in radv_CmdTraceRaysKHR()
7633 radv_set_rt_stack_size(struct radv_cmd_buffer *cmd_buffer, uint32_t size)  in radv_set_rt_stack_size()  argument
7638    if (cmd_buffer->state.rt_pipeline) {  in radv_set_rt_stack_size()
7639       scratch_bytes_per_wave = cmd_buffer->state.rt_pipeline->scratch_bytes_per_wave;  in radv_set_rt_stack_size()
7640       wave_size = cmd_buffer->state.rt_pipeline->shaders[MESA_SHADER_COMPUTE]->info.wave_size;  in radv_set_rt_stack_size()
7646    cmd_buffer->compute_scratch_size_per_wave_needed =  in radv_set_rt_stack_size()
7647       MAX2(cmd_buffer->compute_scratch_size_per_wave_needed, scratch_bytes_per_wave);  in radv_set_rt_stack_size()
7653    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetRayTracingPipelineStackSizeKHR()
7655    radv_set_rt_stack_size(cmd_buffer, size);  in radv_CmdSetRayTracingPipelineStackSizeKHR()
7656    cmd_buffer->state.rt_stack_size = size;  in radv_CmdSetRayTracingPipelineStackSizeKHR()
7660 radv_cmd_buffer_end_render_pass(struct radv_cmd_buffer *cmd_buffer)  in radv_cmd_buffer_end_render_pass()  argument
7662    vk_free(&cmd_buffer->pool->vk.alloc, cmd_buffer->state.attachments);  in radv_cmd_buffer_end_render_pass()
7663    vk_free(&cmd_buffer->pool->vk.alloc, cmd_buffer->state.subpass_sample_locs);  in radv_cmd_buffer_end_render_pass()
7665    cmd_buffer->state.pass = NULL;  in radv_cmd_buffer_end_render_pass()
7666    cmd_buffer->state.subpass = NULL;  in radv_cmd_buffer_end_render_pass()
7667    cmd_buffer->state.attachments = NULL;  in radv_cmd_buffer_end_render_pass()
7668    cmd_buffer->state.framebuffer = NULL;  in radv_cmd_buffer_end_render_pass()
7669    cmd_buffer->state.subpass_sample_locs = NULL;  in radv_cmd_buffer_end_render_pass()
7675    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdEndRenderPass2()
7677    radv_mark_noncoherent_rb(cmd_buffer);  in radv_CmdEndRenderPass2()
7679    radv_emit_subpass_barrier(cmd_buffer, &cmd_buffer->state.pass->end_barrier);  in radv_CmdEndRenderPass2()
7681    radv_cmd_buffer_end_subpass(cmd_buffer);  in radv_CmdEndRenderPass2()
7683    radv_cmd_buffer_end_render_pass(cmd_buffer);  in radv_CmdEndRenderPass2()
7689    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdBeginRenderingKHR()
7945       radv_CreateRenderPass2(radv_device_to_handle(cmd_buffer->device), &rp_create_info, NULL, &rp);  in radv_CmdBeginRenderingKHR()
7947       cmd_buffer->record_result = result;  in radv_CmdBeginRenderingKHR()
7974       radv_CreateFramebuffer(radv_device_to_handle(cmd_buffer->device), &fb_create_info, NULL, &fb);  in radv_CmdBeginRenderingKHR()
7976       radv_DestroyRenderPass(radv_device_to_handle(cmd_buffer->device), rp, NULL);  in radv_CmdBeginRenderingKHR()
7977       cmd_buffer->record_result = result;  in radv_CmdBeginRenderingKHR()
8001    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdEndRenderingKHR()
8002    struct radv_render_pass *pass = cmd_buffer->state.pass;  in radv_CmdEndRenderingKHR()
8003    struct radv_framebuffer *framebuffer = cmd_buffer->state.framebuffer;  in radv_CmdEndRenderingKHR()
8007    radv_DestroyFramebuffer(radv_device_to_handle(cmd_buffer->device),  in radv_CmdEndRenderingKHR()
8009    radv_DestroyRenderPass(radv_device_to_handle(cmd_buffer->device),  in radv_CmdEndRenderingKHR()
8021 radv_initialize_htile(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,  in radv_initialize_htile()  argument
8024    struct radv_cmd_state *state = &cmd_buffer->state;  in radv_initialize_htile()
8025    uint32_t htile_value = radv_get_htile_initial_value(cmd_buffer->device, image);  in radv_initialize_htile()
8030    radv_describe_layout_transition(cmd_buffer, &barrier);  in radv_initialize_htile()
8035       radv_src_access_flush(cmd_buffer, VK_ACCESS_2_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT_KHR, image);  in radv_initialize_htile()
8042 …    state->flush_bits |= radv_dst_access_flush(cmd_buffer, VK_ACCESS_2_SHADER_READ_BIT_KHR, image);  in radv_initialize_htile()
8045    state->flush_bits |= radv_clear_htile(cmd_buffer, image, range, htile_value);  in radv_initialize_htile()
8047    radv_set_ds_clear_metadata(cmd_buffer, image, range, value, range->aspectMask);  in radv_initialize_htile()
8055       radv_set_tc_compat_zrange_metadata(cmd_buffer, image, range, 0);  in radv_initialize_htile()
8060 radv_handle_depth_image_transition(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,  in radv_handle_depth_image_transition()  argument
8067    struct radv_device *device = cmd_buffer->device;  in radv_handle_depth_image_transition()
8073       radv_initialize_htile(cmd_buffer, image, range);  in radv_handle_depth_image_transition()
8078       radv_initialize_htile(cmd_buffer, image, range);  in radv_handle_depth_image_transition()
8083       cmd_buffer->state.flush_bits |=  in radv_handle_depth_image_transition()
8086       radv_expand_depth_stencil(cmd_buffer, image, range, sample_locs);  in radv_handle_depth_image_transition()
8088       cmd_buffer->state.flush_bits |=  in radv_handle_depth_image_transition()
8094 radv_init_cmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,  in radv_init_cmask()  argument
8100    radv_describe_layout_transition(cmd_buffer, &barrier);  in radv_init_cmask()
8102    return radv_clear_cmask(cmd_buffer, image, range, value);  in radv_init_cmask()
8106 radv_init_fmask(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,  in radv_init_fmask()  argument
8115    radv_describe_layout_transition(cmd_buffer, &barrier);  in radv_init_fmask()
8117    return radv_clear_fmask(cmd_buffer, image, range, value);  in radv_init_fmask()
8121 radv_init_dcc(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,  in radv_init_dcc()  argument
8129    radv_describe_layout_transition(cmd_buffer, &barrier);  in radv_init_dcc()
8131    flush_bits |= radv_clear_dcc(cmd_buffer, image, range, value);  in radv_init_dcc()
8133    if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX8) {  in radv_init_dcc()
8152          flush_bits |= radv_fill_buffer(cmd_buffer, image, image->bo,  in radv_init_dcc()
8165 radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,  in radv_init_color_image_metadata()  argument
8176    cmd_buffer->state.flush_bits |=  in radv_init_color_image_metadata()
8177       radv_src_access_flush(cmd_buffer, VK_ACCESS_2_COLOR_ATTACHMENT_WRITE_BIT_KHR, image);  in radv_init_color_image_metadata()
8182       if (cmd_buffer->device->physical_device->rad_info.chip_class == GFX9) {  in radv_init_color_image_metadata()
8186               radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel, dst_layout,  in radv_init_color_image_metadata()
8199       flush_bits |= radv_init_cmask(cmd_buffer, image, range, value);  in radv_init_color_image_metadata()
8203       flush_bits |= radv_init_fmask(cmd_buffer, image, range);  in radv_init_color_image_metadata()
8209       if (radv_layout_dcc_compressed(cmd_buffer->device, image, range->baseMipLevel,  in radv_init_color_image_metadata()
8214       flush_bits |= radv_init_dcc(cmd_buffer, image, range, value);  in radv_init_color_image_metadata()
8218       radv_update_fce_metadata(cmd_buffer, image, range, false);  in radv_init_color_image_metadata()
8221       radv_set_color_clear_metadata(cmd_buffer, image, range, color_values);  in radv_init_color_image_metadata()
8224    cmd_buffer->state.flush_bits |= flush_bits;  in radv_init_color_image_metadata()
8228 radv_retile_transition(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,  in radv_retile_transition()  argument
8234       radv_retile_dcc(cmd_buffer, image);  in radv_retile_transition()
8248 radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,  in radv_handle_color_image_transition()  argument
8261       radv_init_color_image_metadata(cmd_buffer, image, src_layout, src_render_loop, dst_layout,  in radv_handle_color_image_transition()
8265          radv_retile_transition(cmd_buffer, image, src_layout, dst_layout, dst_queue_mask);  in radv_handle_color_image_transition()
8271          cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, image, range, 0xffffffffu);  in radv_handle_color_image_transition()
8272       } else if (radv_layout_dcc_compressed(cmd_buffer->device, image, range->baseMipLevel,  in radv_handle_color_image_transition()
8274                  !radv_layout_dcc_compressed(cmd_buffer->device, image, range->baseMipLevel,  in radv_handle_color_image_transition()
8276          radv_decompress_dcc(cmd_buffer, image, range);  in radv_handle_color_image_transition()
8278       } else if (radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel,  in radv_handle_color_image_transition()
8280                  !radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel,  in radv_handle_color_image_transition()
8282          radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);  in radv_handle_color_image_transition()
8287          radv_retile_transition(cmd_buffer, image, src_layout, dst_layout, dst_queue_mask);  in radv_handle_color_image_transition()
8289       if (radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel,  in radv_handle_color_image_transition()
8291           !radv_layout_can_fast_clear(cmd_buffer->device, image, range->baseMipLevel,  in radv_handle_color_image_transition()
8293          radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);  in radv_handle_color_image_transition()
8301        radv_layout_fmask_compressed(cmd_buffer->device, image, src_layout, src_queue_mask) &&  in radv_handle_color_image_transition()
8302        !radv_layout_fmask_compressed(cmd_buffer->device, image, dst_layout, dst_queue_mask)) {  in radv_handle_color_image_transition()
8304           !radv_image_use_dcc_image_stores(cmd_buffer->device, image) && !dcc_decompressed) {  in radv_handle_color_image_transition()
8310          radv_decompress_dcc(cmd_buffer, image, range);  in radv_handle_color_image_transition()
8315          radv_fast_clear_flush_image_inplace(cmd_buffer, image, range);  in radv_handle_color_image_transition()
8320       radv_describe_layout_transition(cmd_buffer, &barrier);  in radv_handle_color_image_transition()
8322       radv_expand_fmask_image_inplace(cmd_buffer, image, range);  in radv_handle_color_image_transition()
8327 radv_handle_image_transition(struct radv_cmd_buffer *cmd_buffer, struct radv_image *image,  in radv_handle_image_transition()  argument
8333 …enum radv_queue_family src_qf = vk_queue_to_radv(cmd_buffer->device->physical_device, src_family_i…  in radv_handle_image_transition()
8334 …enum radv_queue_family dst_qf = vk_queue_to_radv(cmd_buffer->device->physical_device, dst_family_i…  in radv_handle_image_transition()
8340       assert(src_qf == cmd_buffer->qf ||  in radv_handle_image_transition()
8341              dst_qf == cmd_buffer->qf);  in radv_handle_image_transition()
8346       if (cmd_buffer->qf == RADV_QUEUE_TRANSFER)  in radv_handle_image_transition()
8349       if (cmd_buffer->qf == RADV_QUEUE_COMPUTE &&  in radv_handle_image_transition()
8355       radv_image_queue_family_mask(image, src_qf, cmd_buffer->qf);  in radv_handle_image_transition()
8357       radv_image_queue_family_mask(image, dst_qf, cmd_buffer->qf);  in radv_handle_image_transition()
8363       radv_handle_depth_image_transition(cmd_buffer, image, src_layout, src_render_loop, dst_layout,  in radv_handle_image_transition()
8367       radv_handle_color_image_transition(cmd_buffer, image, src_layout, src_render_loop, dst_layout,  in radv_handle_image_transition()
8373 radv_barrier(struct radv_cmd_buffer *cmd_buffer, const VkDependencyInfoKHR *dep_info,  in radv_barrier()  argument
8381    if (cmd_buffer->state.subpass)  in radv_barrier()
8382       radv_mark_noncoherent_rb(cmd_buffer);  in radv_barrier()
8384    radv_describe_barrier_start(cmd_buffer, reason);  in radv_barrier()
8389          radv_src_access_flush(cmd_buffer, dep_info->pMemoryBarriers[i].srcAccessMask, NULL);  in radv_barrier()
8392          radv_dst_access_flush(cmd_buffer, dep_info->pMemoryBarriers[i].dstAccessMask, NULL);  in radv_barrier()
8398          radv_src_access_flush(cmd_buffer, dep_info->pBufferMemoryBarriers[i].srcAccessMask, NULL);  in radv_barrier()
8401          radv_dst_access_flush(cmd_buffer, dep_info->pBufferMemoryBarriers[i].dstAccessMask, NULL);  in radv_barrier()
8409          radv_src_access_flush(cmd_buffer, dep_info->pImageMemoryBarriers[i].srcAccessMask, image);  in radv_barrier()
8412          radv_dst_access_flush(cmd_buffer, dep_info->pImageMemoryBarriers[i].dstAccessMask, image);  in radv_barrier()
8427       radv_stage_flush(cmd_buffer, src_stage_mask);  in radv_barrier()
8428    cmd_buffer->state.flush_bits |= src_flush_bits;  in radv_barrier()
8447          cmd_buffer, image, dep_info->pImageMemoryBarriers[i].oldLayout,  in radv_barrier()
8462       si_cp_dma_wait_for_idle(cmd_buffer);  in radv_barrier()
8464    cmd_buffer->state.flush_bits |= dst_flush_bits;  in radv_barrier()
8466    radv_describe_barrier_end(cmd_buffer);  in radv_barrier()
8473    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdPipelineBarrier2KHR()
8475    radv_barrier(cmd_buffer, pDependencyInfo, RGP_BARRIER_EXTERNAL_CMD_PIPELINE_BARRIER);  in radv_CmdPipelineBarrier2KHR()
8479 write_event(struct radv_cmd_buffer *cmd_buffer, struct radv_event *event,  in write_event()  argument
8482    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in write_event()
8485    si_emit_cache_flush(cmd_buffer);  in write_event()
8487    radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);  in write_event()
8489    ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 28);  in write_event()
8524       si_cp_dma_wait_for_idle(cmd_buffer);  in write_event()
8554       si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.chip_class,  in write_event()
8555                                  radv_cmd_buffer_uses_mec(cmd_buffer), event_type, 0,  in write_event()
8557                                  cmd_buffer->gfx9_eop_bug_va);  in write_event()
8560    assert(cmd_buffer->cs->cdw <= cdw_max);  in write_event()
8567    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdSetEvent2KHR()
8578    write_event(cmd_buffer, event, src_stage_mask, 1);  in radv_CmdSetEvent2KHR()
8585    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdResetEvent2KHR()
8588    write_event(cmd_buffer, event, stageMask, 0);  in radv_CmdResetEvent2KHR()
8595    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdWaitEvents2KHR()
8596    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_CmdWaitEvents2KHR()
8602       radv_cs_add_buffer(cmd_buffer->device->ws, cs, event->bo);  in radv_CmdWaitEvents2KHR()
8604       ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cs, 7);  in radv_CmdWaitEvents2KHR()
8607       assert(cmd_buffer->cs->cdw <= cdw_max);  in radv_CmdWaitEvents2KHR()
8610    radv_barrier(cmd_buffer, pDependencyInfos, RGP_BARRIER_EXTERNAL_CMD_WAIT_EVENTS);  in radv_CmdWaitEvents2KHR()
8625    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdBeginConditionalRenderingEXT()
8627    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_CmdBeginConditionalRenderingEXT()
8643    si_emit_cache_flush(cmd_buffer);  in radv_CmdBeginConditionalRenderingEXT()
8645    if (cmd_buffer->qf == RADV_QUEUE_GENERAL &&  in radv_CmdBeginConditionalRenderingEXT()
8646        !cmd_buffer->device->physical_device->rad_info.has_32bit_predication) {  in radv_CmdBeginConditionalRenderingEXT()
8676       radv_cmd_buffer_upload_data(cmd_buffer, 8, &pred_value, &pred_offset);  in radv_CmdBeginConditionalRenderingEXT()
8678       pred_va = radv_buffer_get_va(cmd_buffer->upload.upload_bo) + pred_offset;  in radv_CmdBeginConditionalRenderingEXT()
8696    si_emit_set_predication_state(cmd_buffer, draw_visible, pred_op, va);  in radv_CmdBeginConditionalRenderingEXT()
8697    cmd_buffer->state.predicating = true;  in radv_CmdBeginConditionalRenderingEXT()
8700    cmd_buffer->state.predication_type = draw_visible;  in radv_CmdBeginConditionalRenderingEXT()
8701    cmd_buffer->state.predication_op = pred_op;  in radv_CmdBeginConditionalRenderingEXT()
8702    cmd_buffer->state.predication_va = va;  in radv_CmdBeginConditionalRenderingEXT()
8708    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdEndConditionalRenderingEXT()
8711    si_emit_set_predication_state(cmd_buffer, false, 0, 0);  in radv_CmdEndConditionalRenderingEXT()
8712    cmd_buffer->state.predicating = false;  in radv_CmdEndConditionalRenderingEXT()
8715    cmd_buffer->state.predication_type = -1;  in radv_CmdEndConditionalRenderingEXT()
8716    cmd_buffer->state.predication_op = 0;  in radv_CmdEndConditionalRenderingEXT()
8717    cmd_buffer->state.predication_va = 0;  in radv_CmdEndConditionalRenderingEXT()
8726    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdBindTransformFeedbackBuffersEXT()
8727    struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;  in radv_CmdBindTransformFeedbackBuffersEXT()
8743       radv_cs_add_buffer(cmd_buffer->device->ws, cmd_buffer->cs, sb[idx].buffer->bo);  in radv_CmdBindTransformFeedbackBuffersEXT()
8748    cmd_buffer->state.streamout.enabled_mask |= enabled_mask;  in radv_CmdBindTransformFeedbackBuffersEXT()
8750    cmd_buffer->state.dirty |= RADV_CMD_DIRTY_STREAMOUT_BUFFER;  in radv_CmdBindTransformFeedbackBuffersEXT()
8754 radv_emit_streamout_enable(struct radv_cmd_buffer *cmd_buffer)  in radv_emit_streamout_enable()  argument
8756    struct radv_streamout_state *so = &cmd_buffer->state.streamout;  in radv_emit_streamout_enable()
8757    struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;  in radv_emit_streamout_enable()
8759    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_emit_streamout_enable()
8768    cmd_buffer->state.context_roll_without_scissor_emitted = true;  in radv_emit_streamout_enable()
8772 radv_set_streamout_enable(struct radv_cmd_buffer *cmd_buffer, bool enable)  in radv_set_streamout_enable()  argument
8774    struct radv_streamout_state *so = &cmd_buffer->state.streamout;  in radv_set_streamout_enable()
8783    if (!cmd_buffer->device->physical_device->use_ngg_streamout &&  in radv_set_streamout_enable()
8786       radv_emit_streamout_enable(cmd_buffer);  in radv_set_streamout_enable()
8788    if (cmd_buffer->device->physical_device->use_ngg_streamout) {  in radv_set_streamout_enable()
8789       cmd_buffer->gds_needed = true;  in radv_set_streamout_enable()
8790       cmd_buffer->gds_oa_needed = true;  in radv_set_streamout_enable()
8795 radv_flush_vgt_streamout(struct radv_cmd_buffer *cmd_buffer)  in radv_flush_vgt_streamout()  argument
8797    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_flush_vgt_streamout()
8801    if (cmd_buffer->device->physical_device->rad_info.chip_class >= GFX7) {  in radv_flush_vgt_streamout()
8823 radv_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer, uint32_t firstCounterBuffer,  in radv_emit_streamout_begin()  argument
8828    struct radv_streamout_binding *sb = cmd_buffer->streamout_bindings;  in radv_emit_streamout_begin()
8829    struct radv_streamout_state *so = &cmd_buffer->state.streamout;  in radv_emit_streamout_begin()
8830    struct radv_pipeline *pipeline = cmd_buffer->state.pipeline;  in radv_emit_streamout_begin()
8832    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_emit_streamout_begin()
8834    radv_flush_vgt_streamout(cmd_buffer);  in radv_emit_streamout_begin()
8851       cmd_buffer->state.context_roll_without_scissor_emitted = true;  in radv_emit_streamout_begin()
8873          radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);  in radv_emit_streamout_begin()
8886    radv_set_streamout_enable(cmd_buffer, true);  in radv_emit_streamout_begin()
8890 gfx10_emit_streamout_begin(struct radv_cmd_buffer *cmd_buffer, uint32_t firstCounterBuffer,  in gfx10_emit_streamout_begin()  argument
8894    struct radv_streamout_state *so = &cmd_buffer->state.streamout;  in gfx10_emit_streamout_begin()
8896    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in gfx10_emit_streamout_begin()
8898    assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);  in gfx10_emit_streamout_begin()
8906    cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_VS_PARTIAL_FLUSH;  in gfx10_emit_streamout_begin()
8907    si_emit_cache_flush(cmd_buffer);  in gfx10_emit_streamout_begin()
8929          radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);  in gfx10_emit_streamout_begin()
8942    radv_set_streamout_enable(cmd_buffer, true);  in gfx10_emit_streamout_begin()
8950    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdBeginTransformFeedbackEXT()
8952    if (cmd_buffer->device->physical_device->use_ngg_streamout) {  in radv_CmdBeginTransformFeedbackEXT()
8953       gfx10_emit_streamout_begin(cmd_buffer, firstCounterBuffer, counterBufferCount,  in radv_CmdBeginTransformFeedbackEXT()
8956       radv_emit_streamout_begin(cmd_buffer, firstCounterBuffer, counterBufferCount, pCounterBuffers,  in radv_CmdBeginTransformFeedbackEXT()
8962 radv_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer, uint32_t firstCounterBuffer,  in radv_emit_streamout_end()  argument
8966    struct radv_streamout_state *so = &cmd_buffer->state.streamout;  in radv_emit_streamout_end()
8967    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_emit_streamout_end()
8969    radv_flush_vgt_streamout(cmd_buffer);  in radv_emit_streamout_end()
8998          radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);  in radv_emit_streamout_end()
9008       cmd_buffer->state.context_roll_without_scissor_emitted = true;  in radv_emit_streamout_end()
9011    radv_set_streamout_enable(cmd_buffer, false);  in radv_emit_streamout_end()
9015 gfx10_emit_streamout_end(struct radv_cmd_buffer *cmd_buffer, uint32_t firstCounterBuffer,  in gfx10_emit_streamout_end()  argument
9019    struct radv_streamout_state *so = &cmd_buffer->state.streamout;  in gfx10_emit_streamout_end()
9020    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in gfx10_emit_streamout_end()
9022    assert(cmd_buffer->device->physical_device->rad_info.chip_class >= GFX10);  in gfx10_emit_streamout_end()
9042          si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.chip_class,  in gfx10_emit_streamout_end()
9043                                     radv_cmd_buffer_uses_mec(cmd_buffer), V_028A90_PS_DONE, 0,  in gfx10_emit_streamout_end()
9046          radv_cs_add_buffer(cmd_buffer->device->ws, cs, buffer->bo);  in gfx10_emit_streamout_end()
9050    radv_set_streamout_enable(cmd_buffer, false);  in gfx10_emit_streamout_end()
9058    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdEndTransformFeedbackEXT()
9060    if (cmd_buffer->device->physical_device->use_ngg_streamout) {  in radv_CmdEndTransformFeedbackEXT()
9061       gfx10_emit_streamout_end(cmd_buffer, firstCounterBuffer, counterBufferCount, pCounterBuffers,  in radv_CmdEndTransformFeedbackEXT()
9064       radv_emit_streamout_end(cmd_buffer, firstCounterBuffer, counterBufferCount, pCounterBuffers,  in radv_CmdEndTransformFeedbackEXT()
9075    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdDrawIndirectByteCountEXT()
9088    if (!radv_before_draw(cmd_buffer, &info, 1))  in radv_CmdDrawIndirectByteCountEXT()
9091    radv_emit_direct_draw_packets(cmd_buffer, &info, 1, &minfo, S_0287F0_USE_OPAQUE(1), 0);  in radv_CmdDrawIndirectByteCountEXT()
9092    radv_after_draw(cmd_buffer);  in radv_CmdDrawIndirectByteCountEXT()
9100    RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);  in radv_CmdWriteBufferMarker2AMD()
9102    struct radeon_cmdbuf *cs = cmd_buffer->cs;  in radv_CmdWriteBufferMarker2AMD()
9105    si_emit_cache_flush(cmd_buffer);  in radv_CmdWriteBufferMarker2AMD()
9107    ASSERTED unsigned cdw_max = radeon_check_space(cmd_buffer->device->ws, cmd_buffer->cs, 12);  in radv_CmdWriteBufferMarker2AMD()
9118       si_cs_emit_write_event_eop(cs, cmd_buffer->device->physical_device->rad_info.chip_class,  in radv_CmdWriteBufferMarker2AMD()
9119                                  radv_cmd_buffer_uses_mec(cmd_buffer), V_028A90_BOTTOM_OF_PIPE_TS,  in radv_CmdWriteBufferMarker2AMD()
9121                                  cmd_buffer->gfx9_eop_bug_va);  in radv_CmdWriteBufferMarker2AMD()
9124    assert(cmd_buffer->cs->cdw <= cdw_max);  in radv_CmdWriteBufferMarker2AMD()