Lines Matching refs:enc
70 static void radeon_enc_op_balance(struct radeon_encoder *enc) in radeon_enc_op_balance() argument
76 static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc) in radeon_enc_slice_header_hevc() argument
84 RADEON_ENC_BEGIN(enc->cmd.slice_header); in radeon_enc_slice_header_hevc()
85 radeon_enc_reset(enc); in radeon_enc_slice_header_hevc()
86 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_slice_header_hevc()
88 cdw_start = enc->cs.current.cdw; in radeon_enc_slice_header_hevc()
89 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header_hevc()
90 radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6); in radeon_enc_slice_header_hevc()
91 radeon_enc_code_fixed_bits(enc, 0x0, 6); in radeon_enc_slice_header_hevc()
92 radeon_enc_code_fixed_bits(enc, 0x1, 3); in radeon_enc_slice_header_hevc()
94 radeon_enc_flush_headers(enc); in radeon_enc_slice_header_hevc()
96 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header_hevc()
97 bits_copied = enc->bits_output; in radeon_enc_slice_header_hevc()
103 if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23)) in radeon_enc_slice_header_hevc()
104 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header_hevc()
106 radeon_enc_code_ue(enc, 0x0); in radeon_enc_slice_header_hevc()
108 radeon_enc_flush_headers(enc); in radeon_enc_slice_header_hevc()
110 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header_hevc()
111 bits_copied = enc->bits_output; in radeon_enc_slice_header_hevc()
120 switch (enc->enc_pic.picture_type) { in radeon_enc_slice_header_hevc()
123 radeon_enc_code_ue(enc, 0x2); in radeon_enc_slice_header_hevc()
127 radeon_enc_code_ue(enc, 0x1); in radeon_enc_slice_header_hevc()
130 radeon_enc_code_ue(enc, 0x0); in radeon_enc_slice_header_hevc()
133 radeon_enc_code_ue(enc, 0x1); in radeon_enc_slice_header_hevc()
136 if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) { in radeon_enc_slice_header_hevc()
137 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, enc->enc_pic.log2_max_poc); in radeon_enc_slice_header_hevc()
138 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) in radeon_enc_slice_header_hevc()
139 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_slice_header_hevc()
141 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header_hevc()
142 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header_hevc()
143 radeon_enc_code_ue(enc, 0x0); in radeon_enc_slice_header_hevc()
144 radeon_enc_code_ue(enc, 0x0); in radeon_enc_slice_header_hevc()
148 if (enc->enc_pic.sample_adaptive_offset_enabled_flag) { in radeon_enc_slice_header_hevc()
149 radeon_enc_flush_headers(enc); in radeon_enc_slice_header_hevc()
151 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header_hevc()
152 bits_copied = enc->bits_output; in radeon_enc_slice_header_hevc()
159 if ((enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) || in radeon_enc_slice_header_hevc()
160 (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)) { in radeon_enc_slice_header_hevc()
161 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header_hevc()
162 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1); in radeon_enc_slice_header_hevc()
163 radeon_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand); in radeon_enc_slice_header_hevc()
166 radeon_enc_flush_headers(enc); in radeon_enc_slice_header_hevc()
168 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header_hevc()
169 bits_copied = enc->bits_output; in radeon_enc_slice_header_hevc()
175 if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) && in radeon_enc_slice_header_hevc()
176 (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled || in radeon_enc_slice_header_hevc()
177 enc->enc_pic.sample_adaptive_offset_enabled_flag)) { in radeon_enc_slice_header_hevc()
178 if (enc->enc_pic.sample_adaptive_offset_enabled_flag) { in radeon_enc_slice_header_hevc()
179 radeon_enc_flush_headers(enc); in radeon_enc_slice_header_hevc()
181 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header_hevc()
182 bits_copied = enc->bits_output; in radeon_enc_slice_header_hevc()
189 … radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1); in radeon_enc_slice_header_hevc()
192 radeon_enc_flush_headers(enc); in radeon_enc_slice_header_hevc()
194 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header_hevc()
195 bits_copied = enc->bits_output; in radeon_enc_slice_header_hevc()
199 cdw_filled = enc->cs.current.cdw - cdw_start; in radeon_enc_slice_header_hevc()
211 static void radeon_enc_loop_filter_hevc(struct radeon_encoder *enc) in radeon_enc_loop_filter_hevc() argument
213 RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc); in radeon_enc_loop_filter_hevc()
214 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled); in radeon_enc_loop_filter_hevc()
215 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled); in radeon_enc_loop_filter_hevc()
216 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_enc_loop_filter_hevc()
217 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2); in radeon_enc_loop_filter_hevc()
218 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset); in radeon_enc_loop_filter_hevc()
219 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset); in radeon_enc_loop_filter_hevc()
220 RADEON_ENC_CS(!enc->enc_pic.sample_adaptive_offset_enabled_flag); in radeon_enc_loop_filter_hevc()
224 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc) in radeon_enc_nalu_sps_hevc() argument
226 RADEON_ENC_BEGIN(enc->cmd.nalu); in radeon_enc_nalu_sps_hevc()
228 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_enc_nalu_sps_hevc()
231 radeon_enc_reset(enc); in radeon_enc_nalu_sps_hevc()
232 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_nalu_sps_hevc()
233 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); in radeon_enc_nalu_sps_hevc()
234 radeon_enc_code_fixed_bits(enc, 0x4201, 16); in radeon_enc_nalu_sps_hevc()
235 radeon_enc_byte_align(enc); in radeon_enc_nalu_sps_hevc()
236 radeon_enc_set_emulation_prevention(enc, true); in radeon_enc_nalu_sps_hevc()
237 radeon_enc_code_fixed_bits(enc, 0x0, 4); in radeon_enc_nalu_sps_hevc()
238 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3); in radeon_enc_nalu_sps_hevc()
239 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps_hevc()
240 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_sps_hevc()
241 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1); in radeon_enc_nalu_sps_hevc()
242 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5); in radeon_enc_nalu_sps_hevc()
244 if (enc->enc_pic.general_profile_idc == 2) in radeon_enc_nalu_sps_hevc()
245 radeon_enc_code_fixed_bits(enc, 0x20000000, 32); in radeon_enc_nalu_sps_hevc()
247 radeon_enc_code_fixed_bits(enc, 0x60000000, 32); in radeon_enc_nalu_sps_hevc()
249 radeon_enc_code_fixed_bits(enc, 0xb0000000, 32); in radeon_enc_nalu_sps_hevc()
250 radeon_enc_code_fixed_bits(enc, 0x0, 16); in radeon_enc_nalu_sps_hevc()
251 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8); in radeon_enc_nalu_sps_hevc()
253 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++) in radeon_enc_nalu_sps_hevc()
254 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_sps_hevc()
256 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) { in radeon_enc_nalu_sps_hevc()
257 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++) in radeon_enc_nalu_sps_hevc()
258 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_sps_hevc()
261 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps_hevc()
262 radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc); in radeon_enc_nalu_sps_hevc()
263 radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width); in radeon_enc_nalu_sps_hevc()
264 radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height); in radeon_enc_nalu_sps_hevc()
266 if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right != 0) || in radeon_enc_nalu_sps_hevc()
267 (enc->enc_pic.crop_top != 0) || (enc->enc_pic.crop_bottom != 0)) { in radeon_enc_nalu_sps_hevc()
268 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps_hevc()
269 radeon_enc_code_ue(enc, enc->enc_pic.crop_left); in radeon_enc_nalu_sps_hevc()
270 radeon_enc_code_ue(enc, enc->enc_pic.crop_right); in radeon_enc_nalu_sps_hevc()
271 radeon_enc_code_ue(enc, enc->enc_pic.crop_top); in radeon_enc_nalu_sps_hevc()
272 radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom); in radeon_enc_nalu_sps_hevc()
273 } else if (enc->enc_pic.session_init.padding_width != 0 || in radeon_enc_nalu_sps_hevc()
274 enc->enc_pic.session_init.padding_height != 0) { in radeon_enc_nalu_sps_hevc()
275 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps_hevc()
276 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_width / 2); in radeon_enc_nalu_sps_hevc()
277 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_width / 2); in radeon_enc_nalu_sps_hevc()
278 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_height / 2); in radeon_enc_nalu_sps_hevc()
279 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_height / 2); in radeon_enc_nalu_sps_hevc()
281 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
283 radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8); in radeon_enc_nalu_sps_hevc()
284 radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8); in radeon_enc_nalu_sps_hevc()
285 radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4); in radeon_enc_nalu_sps_hevc()
286 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
287 radeon_enc_code_ue(enc, 1); in radeon_enc_nalu_sps_hevc()
288 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps_hevc()
289 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps_hevc()
290 radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3); in radeon_enc_nalu_sps_hevc()
292 radeon_enc_code_ue(enc, in radeon_enc_nalu_sps_hevc()
293 6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3)); in radeon_enc_nalu_sps_hevc()
294 radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2); in radeon_enc_nalu_sps_hevc()
295 radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size); in radeon_enc_nalu_sps_hevc()
296 radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter); in radeon_enc_nalu_sps_hevc()
297 radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra); in radeon_enc_nalu_sps_hevc()
299 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
300 radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1); in radeon_enc_nalu_sps_hevc()
301 radeon_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1); in radeon_enc_nalu_sps_hevc()
302 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1); in radeon_enc_nalu_sps_hevc()
304 radeon_enc_code_ue(enc, 1); in radeon_enc_nalu_sps_hevc()
305 radeon_enc_code_ue(enc, 1); in radeon_enc_nalu_sps_hevc()
306 radeon_enc_code_ue(enc, 0); in radeon_enc_nalu_sps_hevc()
307 radeon_enc_code_ue(enc, 0); in radeon_enc_nalu_sps_hevc()
308 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps_hevc()
310 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
312 radeon_enc_code_fixed_bits(enc, 0, 1); in radeon_enc_nalu_sps_hevc()
313 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1); in radeon_enc_nalu_sps_hevc()
315 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
317 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
319 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps_hevc()
321 radeon_enc_byte_align(enc); in radeon_enc_nalu_sps_hevc()
322 radeon_enc_flush_headers(enc); in radeon_enc_nalu_sps_hevc()
323 *size_in_bytes = (enc->bits_output + 7) / 8; in radeon_enc_nalu_sps_hevc()
327 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc) in radeon_enc_nalu_pps_hevc() argument
329 RADEON_ENC_BEGIN(enc->cmd.nalu); in radeon_enc_nalu_pps_hevc()
331 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_enc_nalu_pps_hevc()
332 radeon_enc_reset(enc); in radeon_enc_nalu_pps_hevc()
333 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_nalu_pps_hevc()
334 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); in radeon_enc_nalu_pps_hevc()
335 radeon_enc_code_fixed_bits(enc, 0x4401, 16); in radeon_enc_nalu_pps_hevc()
336 radeon_enc_byte_align(enc); in radeon_enc_nalu_pps_hevc()
337 radeon_enc_set_emulation_prevention(enc, true); in radeon_enc_nalu_pps_hevc()
338 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps_hevc()
339 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps_hevc()
340 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
341 radeon_enc_code_fixed_bits(enc, 0x0, 4); in radeon_enc_nalu_pps_hevc()
342 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
343 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
344 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps_hevc()
345 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps_hevc()
346 radeon_enc_code_se(enc, 0x0); in radeon_enc_nalu_pps_hevc()
347 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1); in radeon_enc_nalu_pps_hevc()
348 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
349 if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE) in radeon_enc_nalu_pps_hevc()
350 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
352 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
353 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps_hevc()
355 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset); in radeon_enc_nalu_pps_hevc()
356 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset); in radeon_enc_nalu_pps_hevc()
357 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
358 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_pps_hevc()
359 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
360 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
361 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
362 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1); in radeon_enc_nalu_pps_hevc()
363 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
364 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
365 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1); in radeon_enc_nalu_pps_hevc()
367 if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) { in radeon_enc_nalu_pps_hevc()
368 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_enc_nalu_pps_hevc()
369 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2); in radeon_enc_nalu_pps_hevc()
372 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
373 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
374 radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2); in radeon_enc_nalu_pps_hevc()
375 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_pps_hevc()
377 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
379 radeon_enc_byte_align(enc); in radeon_enc_nalu_pps_hevc()
380 radeon_enc_flush_headers(enc); in radeon_enc_nalu_pps_hevc()
381 *size_in_bytes = (enc->bits_output + 7) / 8; in radeon_enc_nalu_pps_hevc()
385 static void radeon_enc_session_init(struct radeon_encoder *enc) in radeon_enc_session_init() argument
387 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264; in radeon_enc_session_init()
388 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16); in radeon_enc_session_init()
389 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16); in radeon_enc_session_init()
390 …enc->enc_pic.session_init.padding_width = enc->enc_pic.session_init.aligned_picture_width - enc->b… in radeon_enc_session_init()
391 …enc->enc_pic.session_init.padding_height = enc->enc_pic.session_init.aligned_picture_height - enc-… in radeon_enc_session_init()
392 enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE; in radeon_enc_session_init()
393 enc->enc_pic.session_init.pre_encode_chroma_enabled = FALSE; in radeon_enc_session_init()
395 RADEON_ENC_BEGIN(enc->cmd.session_init); in radeon_enc_session_init()
396 RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard); in radeon_enc_session_init()
397 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width); in radeon_enc_session_init()
398 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height); in radeon_enc_session_init()
399 RADEON_ENC_CS(enc->enc_pic.session_init.padding_width); in radeon_enc_session_init()
400 RADEON_ENC_CS(enc->enc_pic.session_init.padding_height); in radeon_enc_session_init()
401 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode); in radeon_enc_session_init()
402 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled); in radeon_enc_session_init()
406 static void radeon_enc_efc_config(struct radeon_encoder *enc) in radeon_enc_efc_config() argument
408 if (enc->efc == NULL) { in radeon_enc_efc_config()
409 enc->efc = CALLOC_STRUCT(rvid_buffer); in radeon_enc_efc_config()
411 if (!si_vid_create_buffer(enc->screen, enc->efc, buffer_size, PIPE_USAGE_DYNAMIC)) { in radeon_enc_efc_config()
413 FREE(enc->efc); in radeon_enc_efc_config()
417 …uint32_t *ptr = enc->ws->buffer_map(enc->ws, enc->efc->res->buf, &enc->cs, PIPE_MAP_WRITE | RADEON… in radeon_enc_efc_config()
419 enc->ws->buffer_unmap(enc->ws, enc->efc->res->buf); in radeon_enc_efc_config()
422 enc->enc_pic.efc_params.coef_buffer_size = 46817; in radeon_enc_efc_config()
423 enc->enc_pic.efc_params.cm_program_register_data_size = 1728; in radeon_enc_efc_config()
425 assert(enc->efc); in radeon_enc_efc_config()
427 RADEON_ENC_BEGIN(enc->cmd.efc_params); in radeon_enc_efc_config()
428 RADEON_ENC_WRITE(enc->efc->res->buf, enc->efc->res->domains, 0x0); in radeon_enc_efc_config()
429 RADEON_ENC_CS(enc->enc_pic.efc_params.coef_buffer_size); in radeon_enc_efc_config()
430 RADEON_ENC_CS(enc->enc_pic.efc_params.cm_program_register_data_size); in radeon_enc_efc_config()
434 static void radeon_enc_input_format(struct radeon_encoder *enc) in radeon_enc_input_format() argument
436 RADEON_ENC_BEGIN(enc->cmd.input_format); in radeon_enc_input_format()
437 RADEON_ENC_CS(enc->enc_pic.input_format.input_color_volume); in radeon_enc_input_format()
438 RADEON_ENC_CS(enc->enc_pic.input_format.input_color_space); in radeon_enc_input_format()
439 RADEON_ENC_CS(enc->enc_pic.input_format.input_color_range); in radeon_enc_input_format()
440 RADEON_ENC_CS(enc->enc_pic.input_format.input_chroma_subsampling); in radeon_enc_input_format()
441 RADEON_ENC_CS(enc->enc_pic.input_format.input_chroma_location); in radeon_enc_input_format()
442 RADEON_ENC_CS(enc->enc_pic.input_format.input_color_bit_depth); in radeon_enc_input_format()
443 RADEON_ENC_CS(enc->enc_pic.input_format.input_color_packing_format); in radeon_enc_input_format()
447 static void radeon_enc_output_format(struct radeon_encoder *enc) in radeon_enc_output_format() argument
449 RADEON_ENC_BEGIN(enc->cmd.output_format); in radeon_enc_output_format()
450 RADEON_ENC_CS(enc->enc_pic.output_format.output_color_volume); in radeon_enc_output_format()
451 RADEON_ENC_CS(enc->enc_pic.output_format.output_color_range); in radeon_enc_output_format()
452 RADEON_ENC_CS(enc->enc_pic.output_format.output_chroma_location); in radeon_enc_output_format()
453 RADEON_ENC_CS(enc->enc_pic.output_format.output_color_bit_depth); in radeon_enc_output_format()
457 static void encode(struct radeon_encoder *enc) in encode() argument
459 enc->before_encode(enc); in encode()
460 enc->session_info(enc); in encode()
461 enc->total_task_size = 0; in encode()
462 enc->task_info(enc, enc->need_feedback); in encode()
463 enc->efc_params(enc); in encode()
464 enc->encode_headers(enc); in encode()
465 enc->ctx(enc); in encode()
466 enc->bitstream(enc); in encode()
467 enc->feedback(enc); in encode()
468 enc->intra_refresh(enc); in encode()
469 enc->input_format(enc); in encode()
470 enc->output_format(enc); in encode()
472 enc->op_preset(enc); in encode()
473 enc->op_enc(enc); in encode()
474 *enc->p_task_size = (enc->total_task_size); in encode()
477 void radeon_enc_2_0_init(struct radeon_encoder *enc) in radeon_enc_2_0_init() argument
479 radeon_enc_1_2_init(enc); in radeon_enc_2_0_init()
480 enc->encode = encode; in radeon_enc_2_0_init()
481 enc->input_format = radeon_enc_input_format; in radeon_enc_2_0_init()
482 enc->output_format = radeon_enc_output_format; in radeon_enc_2_0_init()
483 enc->efc_params = radeon_enc_efc_config; in radeon_enc_2_0_init()
485 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) { in radeon_enc_2_0_init()
486 enc->session_init = radeon_enc_session_init; in radeon_enc_2_0_init()
488 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) { in radeon_enc_2_0_init()
489 enc->deblocking_filter = radeon_enc_loop_filter_hevc; in radeon_enc_2_0_init()
490 enc->nalu_sps = radeon_enc_nalu_sps_hevc; in radeon_enc_2_0_init()
491 enc->nalu_pps = radeon_enc_nalu_pps_hevc; in radeon_enc_2_0_init()
492 enc->slice_header = radeon_enc_slice_header_hevc; in radeon_enc_2_0_init()
493 enc->op_preset = radeon_enc_op_balance; in radeon_enc_2_0_init()
496 enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO; in radeon_enc_2_0_init()
497 enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO; in radeon_enc_2_0_init()
498 enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT; in radeon_enc_2_0_init()
499 enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL; in radeon_enc_2_0_init()
500 enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT; in radeon_enc_2_0_init()
501 enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT; in radeon_enc_2_0_init()
502 enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT; in radeon_enc_2_0_init()
503 enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE; in radeon_enc_2_0_init()
504 enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS; in radeon_enc_2_0_init()
505 enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU; in radeon_enc_2_0_init()
506 enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER; in radeon_enc_2_0_init()
507 enc->cmd.input_format = RENCODE_IB_PARAM_INPUT_FORMAT; in radeon_enc_2_0_init()
508 enc->cmd.output_format = RENCODE_IB_PARAM_OUTPUT_FORMAT; in radeon_enc_2_0_init()
509 enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS; in radeon_enc_2_0_init()
510 enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH; in radeon_enc_2_0_init()
511 enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER; in radeon_enc_2_0_init()
512 enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER; in radeon_enc_2_0_init()
513 enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER; in radeon_enc_2_0_init()
514 enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL; in radeon_enc_2_0_init()
515 enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC; in radeon_enc_2_0_init()
516 enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_LOOP_FILTER; in radeon_enc_2_0_init()
517 enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL; in radeon_enc_2_0_init()
518 enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC; in radeon_enc_2_0_init()
519 enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS; in radeon_enc_2_0_init()
520 enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER; in radeon_enc_2_0_init()
521 enc->cmd.efc_params = RENCODE_IB_PARAM_EFC_CONFIG; in radeon_enc_2_0_init()
523 enc->enc_pic.session_info.interface_version = in radeon_enc_2_0_init()