Lines Matching refs:enc
65 static void radeon_enc_session_info(struct radeon_encoder *enc) in radeon_enc_session_info() argument
67 RADEON_ENC_BEGIN(enc->cmd.session_info); in radeon_enc_session_info()
68 RADEON_ENC_CS(enc->enc_pic.session_info.interface_version); in radeon_enc_session_info()
69 RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0); in radeon_enc_session_info()
74 static void radeon_enc_task_info(struct radeon_encoder *enc, bool need_feedback) in radeon_enc_task_info() argument
76 enc->enc_pic.task_info.task_id++; in radeon_enc_task_info()
79 enc->enc_pic.task_info.allowed_max_num_feedbacks = 1; in radeon_enc_task_info()
81 enc->enc_pic.task_info.allowed_max_num_feedbacks = 0; in radeon_enc_task_info()
83 RADEON_ENC_BEGIN(enc->cmd.task_info); in radeon_enc_task_info()
84 enc->p_task_size = &enc->cs->current.buf[enc->cs->current.cdw++]; in radeon_enc_task_info()
85 RADEON_ENC_CS(enc->enc_pic.task_info.task_id); in radeon_enc_task_info()
86 RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks); in radeon_enc_task_info()
90 static void radeon_enc_session_init(struct radeon_encoder *enc) in radeon_enc_session_init() argument
92 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264; in radeon_enc_session_init()
93 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16); in radeon_enc_session_init()
94 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16); in radeon_enc_session_init()
95 enc->enc_pic.session_init.padding_width = in radeon_enc_session_init()
96 enc->enc_pic.session_init.aligned_picture_width - enc->base.width; in radeon_enc_session_init()
97 enc->enc_pic.session_init.padding_height = in radeon_enc_session_init()
98 enc->enc_pic.session_init.aligned_picture_height - enc->base.height; in radeon_enc_session_init()
99 enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE; in radeon_enc_session_init()
100 enc->enc_pic.session_init.pre_encode_chroma_enabled = false; in radeon_enc_session_init()
102 RADEON_ENC_BEGIN(enc->cmd.session_init); in radeon_enc_session_init()
103 RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard); in radeon_enc_session_init()
104 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width); in radeon_enc_session_init()
105 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height); in radeon_enc_session_init()
106 RADEON_ENC_CS(enc->enc_pic.session_init.padding_width); in radeon_enc_session_init()
107 RADEON_ENC_CS(enc->enc_pic.session_init.padding_height); in radeon_enc_session_init()
108 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode); in radeon_enc_session_init()
109 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled); in radeon_enc_session_init()
113 static void radeon_enc_session_init_hevc(struct radeon_encoder *enc) in radeon_enc_session_init_hevc() argument
115 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC; in radeon_enc_session_init_hevc()
116 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64); in radeon_enc_session_init_hevc()
117 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16); in radeon_enc_session_init_hevc()
118 enc->enc_pic.session_init.padding_width = in radeon_enc_session_init_hevc()
119 enc->enc_pic.session_init.aligned_picture_width - enc->base.width; in radeon_enc_session_init_hevc()
120 enc->enc_pic.session_init.padding_height = in radeon_enc_session_init_hevc()
121 enc->enc_pic.session_init.aligned_picture_height - enc->base.height; in radeon_enc_session_init_hevc()
122 enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE; in radeon_enc_session_init_hevc()
123 enc->enc_pic.session_init.pre_encode_chroma_enabled = false; in radeon_enc_session_init_hevc()
125 RADEON_ENC_BEGIN(enc->cmd.session_init); in radeon_enc_session_init_hevc()
126 RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard); in radeon_enc_session_init_hevc()
127 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width); in radeon_enc_session_init_hevc()
128 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height); in radeon_enc_session_init_hevc()
129 RADEON_ENC_CS(enc->enc_pic.session_init.padding_width); in radeon_enc_session_init_hevc()
130 RADEON_ENC_CS(enc->enc_pic.session_init.padding_height); in radeon_enc_session_init_hevc()
131 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode); in radeon_enc_session_init_hevc()
132 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled); in radeon_enc_session_init_hevc()
136 static void radeon_enc_layer_control(struct radeon_encoder *enc) in radeon_enc_layer_control() argument
138 enc->enc_pic.layer_ctrl.max_num_temporal_layers = 1; in radeon_enc_layer_control()
139 enc->enc_pic.layer_ctrl.num_temporal_layers = 1; in radeon_enc_layer_control()
141 RADEON_ENC_BEGIN(enc->cmd.layer_control); in radeon_enc_layer_control()
142 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers); in radeon_enc_layer_control()
143 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers); in radeon_enc_layer_control()
147 static void radeon_enc_layer_select(struct radeon_encoder *enc) in radeon_enc_layer_select() argument
149 enc->enc_pic.layer_sel.temporal_layer_index = 0; in radeon_enc_layer_select()
151 RADEON_ENC_BEGIN(enc->cmd.layer_select); in radeon_enc_layer_select()
152 RADEON_ENC_CS(enc->enc_pic.layer_sel.temporal_layer_index); in radeon_enc_layer_select()
156 static void radeon_enc_slice_control(struct radeon_encoder *enc) in radeon_enc_slice_control() argument
158 enc->enc_pic.slice_ctrl.slice_control_mode = RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS; in radeon_enc_slice_control()
159 enc->enc_pic.slice_ctrl.num_mbs_per_slice = in radeon_enc_slice_control()
160 align(enc->base.width, 16) / 16 * align(enc->base.height, 16) / 16; in radeon_enc_slice_control()
162 RADEON_ENC_BEGIN(enc->cmd.slice_control_h264); in radeon_enc_slice_control()
163 RADEON_ENC_CS(enc->enc_pic.slice_ctrl.slice_control_mode); in radeon_enc_slice_control()
164 RADEON_ENC_CS(enc->enc_pic.slice_ctrl.num_mbs_per_slice); in radeon_enc_slice_control()
168 static void radeon_enc_slice_control_hevc(struct radeon_encoder *enc) in radeon_enc_slice_control_hevc() argument
170 enc->enc_pic.hevc_slice_ctrl.slice_control_mode = RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS; in radeon_enc_slice_control_hevc()
171 enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice = in radeon_enc_slice_control_hevc()
172 align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64; in radeon_enc_slice_control_hevc()
173 enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment = in radeon_enc_slice_control_hevc()
174 enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice; in radeon_enc_slice_control_hevc()
176 RADEON_ENC_BEGIN(enc->cmd.slice_control_hevc); in radeon_enc_slice_control_hevc()
177 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode); in radeon_enc_slice_control_hevc()
178 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice); in radeon_enc_slice_control_hevc()
179 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment); in radeon_enc_slice_control_hevc()
183 static void radeon_enc_spec_misc(struct radeon_encoder *enc) in radeon_enc_spec_misc() argument
185 enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0; in radeon_enc_spec_misc()
186 enc->enc_pic.spec_misc.cabac_enable = 0; in radeon_enc_spec_misc()
187 enc->enc_pic.spec_misc.cabac_init_idc = 0; in radeon_enc_spec_misc()
188 enc->enc_pic.spec_misc.half_pel_enabled = 1; in radeon_enc_spec_misc()
189 enc->enc_pic.spec_misc.quarter_pel_enabled = 1; in radeon_enc_spec_misc()
190 enc->enc_pic.spec_misc.profile_idc = u_get_h264_profile_idc(enc->base.profile); in radeon_enc_spec_misc()
191 enc->enc_pic.spec_misc.level_idc = enc->base.level; in radeon_enc_spec_misc()
193 RADEON_ENC_BEGIN(enc->cmd.spec_misc_h264); in radeon_enc_spec_misc()
194 RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag); in radeon_enc_spec_misc()
195 RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable); in radeon_enc_spec_misc()
196 RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc); in radeon_enc_spec_misc()
197 RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled); in radeon_enc_spec_misc()
198 RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled); in radeon_enc_spec_misc()
199 RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc); in radeon_enc_spec_misc()
200 RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc); in radeon_enc_spec_misc()
204 static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc) in radeon_enc_spec_misc_hevc() argument
206 RADEON_ENC_BEGIN(enc->cmd.spec_misc_hevc); in radeon_enc_spec_misc_hevc()
207 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3); in radeon_enc_spec_misc_hevc()
208 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled); in radeon_enc_spec_misc_hevc()
209 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled); in radeon_enc_spec_misc_hevc()
210 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag); in radeon_enc_spec_misc_hevc()
211 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag); in radeon_enc_spec_misc_hevc()
212 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled); in radeon_enc_spec_misc_hevc()
213 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled); in radeon_enc_spec_misc_hevc()
217 static void radeon_enc_rc_session_init(struct radeon_encoder *enc) in radeon_enc_rc_session_init() argument
219 RADEON_ENC_BEGIN(enc->cmd.rc_session_init); in radeon_enc_rc_session_init()
220 RADEON_ENC_CS(enc->enc_pic.rc_session_init.rate_control_method); in radeon_enc_rc_session_init()
221 RADEON_ENC_CS(enc->enc_pic.rc_session_init.vbv_buffer_level); in radeon_enc_rc_session_init()
225 static void radeon_enc_rc_layer_init(struct radeon_encoder *enc) in radeon_enc_rc_layer_init() argument
227 RADEON_ENC_BEGIN(enc->cmd.rc_layer_init); in radeon_enc_rc_layer_init()
228 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.target_bit_rate); in radeon_enc_rc_layer_init()
229 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bit_rate); in radeon_enc_rc_layer_init()
230 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_num); in radeon_enc_rc_layer_init()
231 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.frame_rate_den); in radeon_enc_rc_layer_init()
232 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.vbv_buffer_size); in radeon_enc_rc_layer_init()
233 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.avg_target_bits_per_picture); in radeon_enc_rc_layer_init()
234 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_integer); in radeon_enc_rc_layer_init()
235 RADEON_ENC_CS(enc->enc_pic.rc_layer_init.peak_bits_per_picture_fractional); in radeon_enc_rc_layer_init()
239 static void radeon_enc_deblocking_filter_h264(struct radeon_encoder *enc) in radeon_enc_deblocking_filter_h264() argument
241 enc->enc_pic.h264_deblock.disable_deblocking_filter_idc = 0; in radeon_enc_deblocking_filter_h264()
242 enc->enc_pic.h264_deblock.alpha_c0_offset_div2 = 0; in radeon_enc_deblocking_filter_h264()
243 enc->enc_pic.h264_deblock.beta_offset_div2 = 0; in radeon_enc_deblocking_filter_h264()
244 enc->enc_pic.h264_deblock.cb_qp_offset = 0; in radeon_enc_deblocking_filter_h264()
245 enc->enc_pic.h264_deblock.cr_qp_offset = 0; in radeon_enc_deblocking_filter_h264()
247 RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_h264); in radeon_enc_deblocking_filter_h264()
248 RADEON_ENC_CS(enc->enc_pic.h264_deblock.disable_deblocking_filter_idc); in radeon_enc_deblocking_filter_h264()
249 RADEON_ENC_CS(enc->enc_pic.h264_deblock.alpha_c0_offset_div2); in radeon_enc_deblocking_filter_h264()
250 RADEON_ENC_CS(enc->enc_pic.h264_deblock.beta_offset_div2); in radeon_enc_deblocking_filter_h264()
251 RADEON_ENC_CS(enc->enc_pic.h264_deblock.cb_qp_offset); in radeon_enc_deblocking_filter_h264()
252 RADEON_ENC_CS(enc->enc_pic.h264_deblock.cr_qp_offset); in radeon_enc_deblocking_filter_h264()
256 static void radeon_enc_deblocking_filter_hevc(struct radeon_encoder *enc) in radeon_enc_deblocking_filter_hevc() argument
258 RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc); in radeon_enc_deblocking_filter_hevc()
259 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled); in radeon_enc_deblocking_filter_hevc()
260 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled); in radeon_enc_deblocking_filter_hevc()
261 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_enc_deblocking_filter_hevc()
262 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2); in radeon_enc_deblocking_filter_hevc()
263 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset); in radeon_enc_deblocking_filter_hevc()
264 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset); in radeon_enc_deblocking_filter_hevc()
268 static void radeon_enc_quality_params(struct radeon_encoder *enc) in radeon_enc_quality_params() argument
270 enc->enc_pic.quality_params.vbaq_mode = 0; in radeon_enc_quality_params()
271 enc->enc_pic.quality_params.scene_change_sensitivity = 0; in radeon_enc_quality_params()
272 enc->enc_pic.quality_params.scene_change_min_idr_interval = 0; in radeon_enc_quality_params()
274 RADEON_ENC_BEGIN(enc->cmd.quality_params); in radeon_enc_quality_params()
275 RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode); in radeon_enc_quality_params()
276 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity); in radeon_enc_quality_params()
277 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval); in radeon_enc_quality_params()
281 static void radeon_enc_nalu_sps(struct radeon_encoder *enc) in radeon_enc_nalu_sps() argument
283 RADEON_ENC_BEGIN(enc->cmd.nalu); in radeon_enc_nalu_sps()
285 uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++]; in radeon_enc_nalu_sps()
286 radeon_enc_reset(enc); in radeon_enc_nalu_sps()
287 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_nalu_sps()
288 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); in radeon_enc_nalu_sps()
289 radeon_enc_code_fixed_bits(enc, 0x67, 8); in radeon_enc_nalu_sps()
290 radeon_enc_byte_align(enc); in radeon_enc_nalu_sps()
291 radeon_enc_set_emulation_prevention(enc, true); in radeon_enc_nalu_sps()
292 radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.profile_idc, 8); in radeon_enc_nalu_sps()
293 radeon_enc_code_fixed_bits(enc, 0x44, 8); // hardcode to constrained baseline in radeon_enc_nalu_sps()
294 radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.level_idc, 8); in radeon_enc_nalu_sps()
295 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps()
297 if (enc->enc_pic.spec_misc.profile_idc == 100 || enc->enc_pic.spec_misc.profile_idc == 110 || in radeon_enc_nalu_sps()
298 enc->enc_pic.spec_misc.profile_idc == 122 || enc->enc_pic.spec_misc.profile_idc == 244 || in radeon_enc_nalu_sps()
299 enc->enc_pic.spec_misc.profile_idc == 44 || enc->enc_pic.spec_misc.profile_idc == 83 || in radeon_enc_nalu_sps()
300 enc->enc_pic.spec_misc.profile_idc == 86 || enc->enc_pic.spec_misc.profile_idc == 118 || in radeon_enc_nalu_sps()
301 enc->enc_pic.spec_misc.profile_idc == 128 || enc->enc_pic.spec_misc.profile_idc == 138) { in radeon_enc_nalu_sps()
302 radeon_enc_code_ue(enc, 0x1); in radeon_enc_nalu_sps()
303 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps()
304 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps()
305 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_sps()
308 radeon_enc_code_ue(enc, 1); in radeon_enc_nalu_sps()
309 radeon_enc_code_ue(enc, enc->enc_pic.pic_order_cnt_type); in radeon_enc_nalu_sps()
311 if (enc->enc_pic.pic_order_cnt_type == 0) in radeon_enc_nalu_sps()
312 radeon_enc_code_ue(enc, 1); in radeon_enc_nalu_sps()
314 radeon_enc_code_ue(enc, (enc->base.max_references + 1)); in radeon_enc_nalu_sps()
315 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0, in radeon_enc_nalu_sps()
317 radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_width / 16 - 1)); in radeon_enc_nalu_sps()
318 radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_height / 16 - 1)); in radeon_enc_nalu_sps()
320 radeon_enc_code_fixed_bits(enc, progressive_only ? 0x1 : 0x0, 1); in radeon_enc_nalu_sps()
323 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps()
325 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps()
327 if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right != 0) || in radeon_enc_nalu_sps()
328 (enc->enc_pic.crop_top != 0) || (enc->enc_pic.crop_bottom != 0)) { in radeon_enc_nalu_sps()
329 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps()
330 radeon_enc_code_ue(enc, enc->enc_pic.crop_left); in radeon_enc_nalu_sps()
331 radeon_enc_code_ue(enc, enc->enc_pic.crop_right); in radeon_enc_nalu_sps()
332 radeon_enc_code_ue(enc, enc->enc_pic.crop_top); in radeon_enc_nalu_sps()
333 radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom); in radeon_enc_nalu_sps()
335 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps()
337 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps()
338 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps()
339 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps()
340 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps()
341 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps()
342 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps()
343 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps()
344 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps()
345 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps()
346 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps()
347 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps()
348 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps()
349 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps()
350 radeon_enc_code_ue(enc, 16); in radeon_enc_nalu_sps()
351 radeon_enc_code_ue(enc, 16); in radeon_enc_nalu_sps()
352 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps()
353 radeon_enc_code_ue(enc, (enc->base.max_references + 1)); in radeon_enc_nalu_sps()
355 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps()
357 radeon_enc_byte_align(enc); in radeon_enc_nalu_sps()
358 radeon_enc_flush_headers(enc); in radeon_enc_nalu_sps()
359 *size_in_bytes = (enc->bits_output + 7) / 8; in radeon_enc_nalu_sps()
363 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc) in radeon_enc_nalu_sps_hevc() argument
365 RADEON_ENC_BEGIN(enc->cmd.nalu); in radeon_enc_nalu_sps_hevc()
367 uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++]; in radeon_enc_nalu_sps_hevc()
370 radeon_enc_reset(enc); in radeon_enc_nalu_sps_hevc()
371 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_nalu_sps_hevc()
372 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); in radeon_enc_nalu_sps_hevc()
373 radeon_enc_code_fixed_bits(enc, 0x4201, 16); in radeon_enc_nalu_sps_hevc()
374 radeon_enc_byte_align(enc); in radeon_enc_nalu_sps_hevc()
375 radeon_enc_set_emulation_prevention(enc, true); in radeon_enc_nalu_sps_hevc()
376 radeon_enc_code_fixed_bits(enc, 0x0, 4); in radeon_enc_nalu_sps_hevc()
377 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3); in radeon_enc_nalu_sps_hevc()
378 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps_hevc()
379 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_sps_hevc()
380 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1); in radeon_enc_nalu_sps_hevc()
381 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5); in radeon_enc_nalu_sps_hevc()
382 radeon_enc_code_fixed_bits(enc, 0x60000000, 32); in radeon_enc_nalu_sps_hevc()
383 radeon_enc_code_fixed_bits(enc, 0xb0000000, 32); in radeon_enc_nalu_sps_hevc()
384 radeon_enc_code_fixed_bits(enc, 0x0, 16); in radeon_enc_nalu_sps_hevc()
385 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8); in radeon_enc_nalu_sps_hevc()
387 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++) in radeon_enc_nalu_sps_hevc()
388 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_sps_hevc()
390 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) { in radeon_enc_nalu_sps_hevc()
391 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++) in radeon_enc_nalu_sps_hevc()
392 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_sps_hevc()
395 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps_hevc()
396 radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc); in radeon_enc_nalu_sps_hevc()
397 radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width); in radeon_enc_nalu_sps_hevc()
398 radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height); in radeon_enc_nalu_sps_hevc()
399 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
400 radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8); in radeon_enc_nalu_sps_hevc()
401 radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8); in radeon_enc_nalu_sps_hevc()
402 radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4); in radeon_enc_nalu_sps_hevc()
403 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
404 radeon_enc_code_ue(enc, 1); in radeon_enc_nalu_sps_hevc()
405 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps_hevc()
406 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps_hevc()
407 radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3); in radeon_enc_nalu_sps_hevc()
409 radeon_enc_code_ue(enc, in radeon_enc_nalu_sps_hevc()
410 6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3)); in radeon_enc_nalu_sps_hevc()
411 radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2); in radeon_enc_nalu_sps_hevc()
412 radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size); in radeon_enc_nalu_sps_hevc()
413 radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter); in radeon_enc_nalu_sps_hevc()
414 radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra); in radeon_enc_nalu_sps_hevc()
416 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
417 radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1); in radeon_enc_nalu_sps_hevc()
418 radeon_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1); in radeon_enc_nalu_sps_hevc()
419 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1); in radeon_enc_nalu_sps_hevc()
421 radeon_enc_code_ue(enc, 1); in radeon_enc_nalu_sps_hevc()
422 radeon_enc_code_ue(enc, 1); in radeon_enc_nalu_sps_hevc()
423 radeon_enc_code_ue(enc, 0); in radeon_enc_nalu_sps_hevc()
424 radeon_enc_code_ue(enc, 0); in radeon_enc_nalu_sps_hevc()
425 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps_hevc()
427 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
429 radeon_enc_code_fixed_bits(enc, 0, 1); in radeon_enc_nalu_sps_hevc()
430 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1); in radeon_enc_nalu_sps_hevc()
432 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
434 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
436 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps_hevc()
438 radeon_enc_byte_align(enc); in radeon_enc_nalu_sps_hevc()
439 radeon_enc_flush_headers(enc); in radeon_enc_nalu_sps_hevc()
440 *size_in_bytes = (enc->bits_output + 7) / 8; in radeon_enc_nalu_sps_hevc()
444 static void radeon_enc_nalu_pps(struct radeon_encoder *enc) in radeon_enc_nalu_pps() argument
446 RADEON_ENC_BEGIN(enc->cmd.nalu); in radeon_enc_nalu_pps()
448 uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++]; in radeon_enc_nalu_pps()
449 radeon_enc_reset(enc); in radeon_enc_nalu_pps()
450 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_nalu_pps()
451 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); in radeon_enc_nalu_pps()
452 radeon_enc_code_fixed_bits(enc, 0x68, 8); in radeon_enc_nalu_pps()
453 radeon_enc_byte_align(enc); in radeon_enc_nalu_pps()
454 radeon_enc_set_emulation_prevention(enc, true); in radeon_enc_nalu_pps()
455 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps()
456 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps()
457 radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.cabac_enable ? 0x1 : 0x0), 1); in radeon_enc_nalu_pps()
458 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps()
459 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps()
460 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps()
461 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps()
462 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps()
463 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_pps()
464 radeon_enc_code_se(enc, 0x0); in radeon_enc_nalu_pps()
465 radeon_enc_code_se(enc, 0x0); in radeon_enc_nalu_pps()
466 radeon_enc_code_se(enc, 0x0); in radeon_enc_nalu_pps()
467 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps()
468 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps()
469 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps()
471 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps()
473 radeon_enc_byte_align(enc); in radeon_enc_nalu_pps()
474 radeon_enc_flush_headers(enc); in radeon_enc_nalu_pps()
475 *size_in_bytes = (enc->bits_output + 7) / 8; in radeon_enc_nalu_pps()
479 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc) in radeon_enc_nalu_pps_hevc() argument
481 RADEON_ENC_BEGIN(enc->cmd.nalu); in radeon_enc_nalu_pps_hevc()
483 uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++]; in radeon_enc_nalu_pps_hevc()
484 radeon_enc_reset(enc); in radeon_enc_nalu_pps_hevc()
485 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_nalu_pps_hevc()
486 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); in radeon_enc_nalu_pps_hevc()
487 radeon_enc_code_fixed_bits(enc, 0x4401, 16); in radeon_enc_nalu_pps_hevc()
488 radeon_enc_byte_align(enc); in radeon_enc_nalu_pps_hevc()
489 radeon_enc_set_emulation_prevention(enc, true); in radeon_enc_nalu_pps_hevc()
490 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps_hevc()
491 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps_hevc()
492 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
493 radeon_enc_code_fixed_bits(enc, 0x0, 4); in radeon_enc_nalu_pps_hevc()
494 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
495 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
496 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps_hevc()
497 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps_hevc()
498 radeon_enc_code_se(enc, 0x0); in radeon_enc_nalu_pps_hevc()
499 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1); in radeon_enc_nalu_pps_hevc()
500 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
501 if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE) in radeon_enc_nalu_pps_hevc()
502 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
504 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
505 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps_hevc()
507 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset); in radeon_enc_nalu_pps_hevc()
508 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset); in radeon_enc_nalu_pps_hevc()
509 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
510 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_pps_hevc()
511 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
512 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
513 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
514 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1); in radeon_enc_nalu_pps_hevc()
515 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
516 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
517 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1); in radeon_enc_nalu_pps_hevc()
519 if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) { in radeon_enc_nalu_pps_hevc()
520 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_enc_nalu_pps_hevc()
521 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2); in radeon_enc_nalu_pps_hevc()
524 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
525 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
526 radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2); in radeon_enc_nalu_pps_hevc()
527 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_pps_hevc()
529 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
531 radeon_enc_byte_align(enc); in radeon_enc_nalu_pps_hevc()
532 radeon_enc_flush_headers(enc); in radeon_enc_nalu_pps_hevc()
533 *size_in_bytes = (enc->bits_output + 7) / 8; in radeon_enc_nalu_pps_hevc()
537 static void radeon_enc_nalu_vps(struct radeon_encoder *enc) in radeon_enc_nalu_vps() argument
539 RADEON_ENC_BEGIN(enc->cmd.nalu); in radeon_enc_nalu_vps()
541 uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++]; in radeon_enc_nalu_vps()
544 radeon_enc_reset(enc); in radeon_enc_nalu_vps()
545 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_nalu_vps()
546 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); in radeon_enc_nalu_vps()
547 radeon_enc_code_fixed_bits(enc, 0x4001, 16); in radeon_enc_nalu_vps()
548 radeon_enc_byte_align(enc); in radeon_enc_nalu_vps()
549 radeon_enc_set_emulation_prevention(enc, true); in radeon_enc_nalu_vps()
551 radeon_enc_code_fixed_bits(enc, 0x0, 4); in radeon_enc_nalu_vps()
552 radeon_enc_code_fixed_bits(enc, 0x3, 2); in radeon_enc_nalu_vps()
553 radeon_enc_code_fixed_bits(enc, 0x0, 6); in radeon_enc_nalu_vps()
554 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3); in radeon_enc_nalu_vps()
555 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_vps()
556 radeon_enc_code_fixed_bits(enc, 0xffff, 16); in radeon_enc_nalu_vps()
557 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_vps()
558 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1); in radeon_enc_nalu_vps()
559 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5); in radeon_enc_nalu_vps()
560 radeon_enc_code_fixed_bits(enc, 0x60000000, 32); in radeon_enc_nalu_vps()
561 radeon_enc_code_fixed_bits(enc, 0xb0000000, 32); in radeon_enc_nalu_vps()
562 radeon_enc_code_fixed_bits(enc, 0x0, 16); in radeon_enc_nalu_vps()
563 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8); in radeon_enc_nalu_vps()
565 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++) in radeon_enc_nalu_vps()
566 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_vps()
568 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) { in radeon_enc_nalu_vps()
569 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++) in radeon_enc_nalu_vps()
570 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_vps()
573 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_vps()
574 radeon_enc_code_ue(enc, 0x1); in radeon_enc_nalu_vps()
575 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_vps()
576 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_vps()
578 radeon_enc_code_fixed_bits(enc, 0x0, 6); in radeon_enc_nalu_vps()
579 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_vps()
580 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_vps()
581 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_vps()
583 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_vps()
585 radeon_enc_byte_align(enc); in radeon_enc_nalu_vps()
586 radeon_enc_flush_headers(enc); in radeon_enc_nalu_vps()
587 *size_in_bytes = (enc->bits_output + 7) / 8; in radeon_enc_nalu_vps()
591 static void radeon_enc_nalu_aud_hevc(struct radeon_encoder *enc) in radeon_enc_nalu_aud_hevc() argument
593 RADEON_ENC_BEGIN(enc->cmd.nalu); in radeon_enc_nalu_aud_hevc()
595 uint32_t *size_in_bytes = &enc->cs->current.buf[enc->cs->current.cdw++]; in radeon_enc_nalu_aud_hevc()
596 radeon_enc_reset(enc); in radeon_enc_nalu_aud_hevc()
597 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_nalu_aud_hevc()
598 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); in radeon_enc_nalu_aud_hevc()
599 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_aud_hevc()
600 radeon_enc_code_fixed_bits(enc, 35, 6); in radeon_enc_nalu_aud_hevc()
601 radeon_enc_code_fixed_bits(enc, 0x0, 6); in radeon_enc_nalu_aud_hevc()
602 radeon_enc_code_fixed_bits(enc, 0x1, 3); in radeon_enc_nalu_aud_hevc()
603 radeon_enc_byte_align(enc); in radeon_enc_nalu_aud_hevc()
604 radeon_enc_set_emulation_prevention(enc, true); in radeon_enc_nalu_aud_hevc()
605 switch (enc->enc_pic.picture_type) { in radeon_enc_nalu_aud_hevc()
608 radeon_enc_code_fixed_bits(enc, 0x00, 3); in radeon_enc_nalu_aud_hevc()
611 radeon_enc_code_fixed_bits(enc, 0x01, 3); in radeon_enc_nalu_aud_hevc()
614 radeon_enc_code_fixed_bits(enc, 0x02, 3); in radeon_enc_nalu_aud_hevc()
617 radeon_enc_code_fixed_bits(enc, 0x02, 3); in radeon_enc_nalu_aud_hevc()
620 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_aud_hevc()
622 radeon_enc_byte_align(enc); in radeon_enc_nalu_aud_hevc()
623 radeon_enc_flush_headers(enc); in radeon_enc_nalu_aud_hevc()
624 *size_in_bytes = (enc->bits_output + 7) / 8; in radeon_enc_nalu_aud_hevc()
628 static void radeon_enc_slice_header(struct radeon_encoder *enc) in radeon_enc_slice_header() argument
635 RADEON_ENC_BEGIN(enc->cmd.slice_header); in radeon_enc_slice_header()
636 radeon_enc_reset(enc); in radeon_enc_slice_header()
637 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_slice_header()
639 if (enc->enc_pic.is_idr) in radeon_enc_slice_header()
640 radeon_enc_code_fixed_bits(enc, 0x65, 8); in radeon_enc_slice_header()
641 else if (enc->enc_pic.not_referenced) in radeon_enc_slice_header()
642 radeon_enc_code_fixed_bits(enc, 0x01, 8); in radeon_enc_slice_header()
644 radeon_enc_code_fixed_bits(enc, 0x41, 8); in radeon_enc_slice_header()
646 radeon_enc_flush_headers(enc); in radeon_enc_slice_header()
649 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header()
650 bits_copied = enc->bits_output; in radeon_enc_slice_header()
656 switch (enc->enc_pic.picture_type) { in radeon_enc_slice_header()
659 radeon_enc_code_fixed_bits(enc, 0x08, 7); in radeon_enc_slice_header()
663 radeon_enc_code_fixed_bits(enc, 0x06, 5); in radeon_enc_slice_header()
666 radeon_enc_code_fixed_bits(enc, 0x07, 5); in radeon_enc_slice_header()
669 radeon_enc_code_fixed_bits(enc, 0x08, 7); in radeon_enc_slice_header()
672 radeon_enc_code_ue(enc, 0x0); in radeon_enc_slice_header()
673 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % 32, 5); in radeon_enc_slice_header()
675 if (enc->enc_pic.h264_enc_params.input_picture_structure != in radeon_enc_slice_header()
677 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_slice_header()
678 radeon_enc_code_fixed_bits(enc, in radeon_enc_slice_header()
679 enc->enc_pic.h264_enc_params.input_picture_structure == in radeon_enc_slice_header()
686 if (enc->enc_pic.is_idr) in radeon_enc_slice_header()
687 radeon_enc_code_ue(enc, enc->enc_pic.is_even_frame); in radeon_enc_slice_header()
689 enc->enc_pic.is_even_frame = !enc->enc_pic.is_even_frame; in radeon_enc_slice_header()
691 if (enc->enc_pic.pic_order_cnt_type == 0) in radeon_enc_slice_header()
692 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt % 32, 5); in radeon_enc_slice_header()
694 if (enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) { in radeon_enc_slice_header()
695 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header()
697 if (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 > 1) { in radeon_enc_slice_header()
698 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_slice_header()
699 radeon_enc_code_ue(enc, 0x0); in radeon_enc_slice_header()
700 radeon_enc_code_ue(enc, (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 - 1)); in radeon_enc_slice_header()
701 radeon_enc_code_ue(enc, 0x3); in radeon_enc_slice_header()
703 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header()
706 if (enc->enc_pic.is_idr) { in radeon_enc_slice_header()
707 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header()
708 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header()
710 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header()
712 if ((enc->enc_pic.picture_type != PIPE_H264_ENC_PICTURE_TYPE_IDR) && in radeon_enc_slice_header()
713 (enc->enc_pic.spec_misc.cabac_enable)) in radeon_enc_slice_header()
714 radeon_enc_code_ue(enc, enc->enc_pic.spec_misc.cabac_init_idc); in radeon_enc_slice_header()
716 radeon_enc_flush_headers(enc); in radeon_enc_slice_header()
719 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header()
720 bits_copied = enc->bits_output; in radeon_enc_slice_header()
726 radeon_enc_code_ue(enc, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc ? 1 : 0); in radeon_enc_slice_header()
728 if (!enc->enc_pic.h264_deblock.disable_deblocking_filter_idc) { in radeon_enc_slice_header()
729 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.alpha_c0_offset_div2); in radeon_enc_slice_header()
730 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2); in radeon_enc_slice_header()
733 radeon_enc_flush_headers(enc); in radeon_enc_slice_header()
736 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header()
737 bits_copied = enc->bits_output; in radeon_enc_slice_header()
753 static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc) in radeon_enc_slice_header_hevc() argument
760 RADEON_ENC_BEGIN(enc->cmd.slice_header); in radeon_enc_slice_header_hevc()
761 radeon_enc_reset(enc); in radeon_enc_slice_header_hevc()
762 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_slice_header_hevc()
764 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header_hevc()
765 radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6); in radeon_enc_slice_header_hevc()
766 radeon_enc_code_fixed_bits(enc, 0x0, 6); in radeon_enc_slice_header_hevc()
767 radeon_enc_code_fixed_bits(enc, 0x1, 3); in radeon_enc_slice_header_hevc()
769 radeon_enc_flush_headers(enc); in radeon_enc_slice_header_hevc()
772 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header_hevc()
773 bits_copied = enc->bits_output; in radeon_enc_slice_header_hevc()
779 if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23)) in radeon_enc_slice_header_hevc()
780 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header_hevc()
782 radeon_enc_code_ue(enc, 0x0); in radeon_enc_slice_header_hevc()
784 radeon_enc_flush_headers(enc); in radeon_enc_slice_header_hevc()
787 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header_hevc()
788 bits_copied = enc->bits_output; in radeon_enc_slice_header_hevc()
797 switch (enc->enc_pic.picture_type) { in radeon_enc_slice_header_hevc()
800 radeon_enc_code_ue(enc, 0x2); in radeon_enc_slice_header_hevc()
804 radeon_enc_code_ue(enc, 0x1); in radeon_enc_slice_header_hevc()
807 radeon_enc_code_ue(enc, 0x0); in radeon_enc_slice_header_hevc()
810 radeon_enc_code_ue(enc, 0x1); in radeon_enc_slice_header_hevc()
813 if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) { in radeon_enc_slice_header_hevc()
814 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, enc->enc_pic.log2_max_poc); in radeon_enc_slice_header_hevc()
815 if (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P) in radeon_enc_slice_header_hevc()
816 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_slice_header_hevc()
818 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header_hevc()
819 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header_hevc()
820 radeon_enc_code_ue(enc, 0x0); in radeon_enc_slice_header_hevc()
821 radeon_enc_code_ue(enc, 0x0); in radeon_enc_slice_header_hevc()
825 if ((enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_P) || in radeon_enc_slice_header_hevc()
826 (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_B)) { in radeon_enc_slice_header_hevc()
827 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header_hevc()
828 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1); in radeon_enc_slice_header_hevc()
829 radeon_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand); in radeon_enc_slice_header_hevc()
832 radeon_enc_flush_headers(enc); in radeon_enc_slice_header_hevc()
835 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header_hevc()
836 bits_copied = enc->bits_output; in radeon_enc_slice_header_hevc()
842 if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) && in radeon_enc_slice_header_hevc()
843 (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled)) { in radeon_enc_slice_header_hevc()
844 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, in radeon_enc_slice_header_hevc()
847 radeon_enc_flush_headers(enc); in radeon_enc_slice_header_hevc()
850 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header_hevc()
851 bits_copied = enc->bits_output; in radeon_enc_slice_header_hevc()
868 static void radeon_enc_ctx(struct radeon_encoder *enc) in radeon_enc_ctx() argument
870 enc->enc_pic.ctx_buf.swizzle_mode = 0; in radeon_enc_ctx()
871 enc->enc_pic.ctx_buf.rec_luma_pitch = align(enc->base.width, enc->alignment); in radeon_enc_ctx()
872 enc->enc_pic.ctx_buf.rec_chroma_pitch = align(enc->base.width, enc->alignment); in radeon_enc_ctx()
873 enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2; in radeon_enc_ctx()
875 RADEON_ENC_BEGIN(enc->cmd.ctx); in radeon_enc_ctx()
876 RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0); in radeon_enc_ctx()
877 RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode); in radeon_enc_ctx()
878 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch); in radeon_enc_ctx()
879 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch); in radeon_enc_ctx()
880 RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures); in radeon_enc_ctx()
884 RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16)); in radeon_enc_ctx()
886 RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 3 / 2); in radeon_enc_ctx()
888 RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 5 / 2); in radeon_enc_ctx()
896 static void radeon_enc_bitstream(struct radeon_encoder *enc) in radeon_enc_bitstream() argument
898 enc->enc_pic.bit_buf.mode = RENCODE_REC_SWIZZLE_MODE_LINEAR; in radeon_enc_bitstream()
899 enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size; in radeon_enc_bitstream()
900 enc->enc_pic.bit_buf.video_bitstream_data_offset = 0; in radeon_enc_bitstream()
902 RADEON_ENC_BEGIN(enc->cmd.bitstream); in radeon_enc_bitstream()
903 RADEON_ENC_CS(enc->enc_pic.bit_buf.mode); in radeon_enc_bitstream()
904 RADEON_ENC_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0); in radeon_enc_bitstream()
905 RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_buffer_size); in radeon_enc_bitstream()
906 RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_data_offset); in radeon_enc_bitstream()
910 static void radeon_enc_feedback(struct radeon_encoder *enc) in radeon_enc_feedback() argument
912 enc->enc_pic.fb_buf.mode = RENCODE_FEEDBACK_BUFFER_MODE_LINEAR; in radeon_enc_feedback()
913 enc->enc_pic.fb_buf.feedback_buffer_size = 16; in radeon_enc_feedback()
914 enc->enc_pic.fb_buf.feedback_data_size = 40; in radeon_enc_feedback()
916 RADEON_ENC_BEGIN(enc->cmd.feedback); in radeon_enc_feedback()
917 RADEON_ENC_CS(enc->enc_pic.fb_buf.mode); in radeon_enc_feedback()
918 RADEON_ENC_WRITE(enc->fb->res->buf, enc->fb->res->domains, 0x0); in radeon_enc_feedback()
919 RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_buffer_size); in radeon_enc_feedback()
920 RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_data_size); in radeon_enc_feedback()
924 static void radeon_enc_intra_refresh(struct radeon_encoder *enc) in radeon_enc_intra_refresh() argument
926 enc->enc_pic.intra_ref.intra_refresh_mode = RENCODE_INTRA_REFRESH_MODE_NONE; in radeon_enc_intra_refresh()
927 enc->enc_pic.intra_ref.offset = 0; in radeon_enc_intra_refresh()
928 enc->enc_pic.intra_ref.region_size = 0; in radeon_enc_intra_refresh()
930 RADEON_ENC_BEGIN(enc->cmd.intra_refresh); in radeon_enc_intra_refresh()
931 RADEON_ENC_CS(enc->enc_pic.intra_ref.intra_refresh_mode); in radeon_enc_intra_refresh()
932 RADEON_ENC_CS(enc->enc_pic.intra_ref.offset); in radeon_enc_intra_refresh()
933 RADEON_ENC_CS(enc->enc_pic.intra_ref.region_size); in radeon_enc_intra_refresh()
937 static void radeon_enc_rc_per_pic(struct radeon_encoder *enc) in radeon_enc_rc_per_pic() argument
939 RADEON_ENC_BEGIN(enc->cmd.rc_per_pic); in radeon_enc_rc_per_pic()
940 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp); in radeon_enc_rc_per_pic()
941 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_app); in radeon_enc_rc_per_pic()
942 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_app); in radeon_enc_rc_per_pic()
943 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size); in radeon_enc_rc_per_pic()
944 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data); in radeon_enc_rc_per_pic()
945 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable); in radeon_enc_rc_per_pic()
946 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd); in radeon_enc_rc_per_pic()
950 static void radeon_enc_encode_params(struct radeon_encoder *enc) in radeon_enc_encode_params() argument
952 switch (enc->enc_pic.picture_type) { in radeon_enc_encode_params()
955 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I; in radeon_enc_encode_params()
958 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P; in radeon_enc_encode_params()
961 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP; in radeon_enc_encode_params()
964 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B; in radeon_enc_encode_params()
967 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I; in radeon_enc_encode_params()
970 enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size; in radeon_enc_encode_params()
971 enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch; in radeon_enc_encode_params()
972 enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch; in radeon_enc_encode_params()
973 enc->enc_pic.enc_params.input_pic_swizzle_mode = RENCODE_INPUT_SWIZZLE_MODE_LINEAR; in radeon_enc_encode_params()
975 if (enc->enc_pic.picture_type == PIPE_H264_ENC_PICTURE_TYPE_IDR) in radeon_enc_encode_params()
976 enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF; in radeon_enc_encode_params()
978 enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2; in radeon_enc_encode_params()
980 enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2; in radeon_enc_encode_params()
982 RADEON_ENC_BEGIN(enc->cmd.enc_params); in radeon_enc_encode_params()
983 RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type); in radeon_enc_encode_params()
984 RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size); in radeon_enc_encode_params()
985 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset); in radeon_enc_encode_params()
986 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset); in radeon_enc_encode_params()
987 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch); in radeon_enc_encode_params()
988 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch); in radeon_enc_encode_params()
989 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode); in radeon_enc_encode_params()
990 RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index); in radeon_enc_encode_params()
991 RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index); in radeon_enc_encode_params()
995 static void radeon_enc_encode_params_hevc(struct radeon_encoder *enc) in radeon_enc_encode_params_hevc() argument
997 switch (enc->enc_pic.picture_type) { in radeon_enc_encode_params_hevc()
1000 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I; in radeon_enc_encode_params_hevc()
1003 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P; in radeon_enc_encode_params_hevc()
1006 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP; in radeon_enc_encode_params_hevc()
1009 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B; in radeon_enc_encode_params_hevc()
1012 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I; in radeon_enc_encode_params_hevc()
1015 enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size; in radeon_enc_encode_params_hevc()
1016 enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch; in radeon_enc_encode_params_hevc()
1017 enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch; in radeon_enc_encode_params_hevc()
1018 enc->enc_pic.enc_params.input_pic_swizzle_mode = RENCODE_INPUT_SWIZZLE_MODE_LINEAR; in radeon_enc_encode_params_hevc()
1020 if (enc->enc_pic.enc_params.pic_type == RENCODE_PICTURE_TYPE_I) in radeon_enc_encode_params_hevc()
1021 enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF; in radeon_enc_encode_params_hevc()
1023 enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2; in radeon_enc_encode_params_hevc()
1025 enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2; in radeon_enc_encode_params_hevc()
1027 RADEON_ENC_BEGIN(enc->cmd.enc_params); in radeon_enc_encode_params_hevc()
1028 RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type); in radeon_enc_encode_params_hevc()
1029 RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size); in radeon_enc_encode_params_hevc()
1030 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset); in radeon_enc_encode_params_hevc()
1031 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset); in radeon_enc_encode_params_hevc()
1032 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch); in radeon_enc_encode_params_hevc()
1033 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch); in radeon_enc_encode_params_hevc()
1034 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode); in radeon_enc_encode_params_hevc()
1035 RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index); in radeon_enc_encode_params_hevc()
1036 RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index); in radeon_enc_encode_params_hevc()
1040 static void radeon_enc_encode_params_h264(struct radeon_encoder *enc) in radeon_enc_encode_params_h264() argument
1042 enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME; in radeon_enc_encode_params_h264()
1043 enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE; in radeon_enc_encode_params_h264()
1044 enc->enc_pic.h264_enc_params.reference_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME; in radeon_enc_encode_params_h264()
1045 enc->enc_pic.h264_enc_params.reference_picture1_index = 0xFFFFFFFF; in radeon_enc_encode_params_h264()
1047 RADEON_ENC_BEGIN(enc->cmd.enc_params_h264); in radeon_enc_encode_params_h264()
1048 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure); in radeon_enc_encode_params_h264()
1049 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode); in radeon_enc_encode_params_h264()
1050 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture_structure); in radeon_enc_encode_params_h264()
1051 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture1_index); in radeon_enc_encode_params_h264()
1055 static void radeon_enc_op_init(struct radeon_encoder *enc) in radeon_enc_op_init() argument
1061 static void radeon_enc_op_close(struct radeon_encoder *enc) in radeon_enc_op_close() argument
1067 static void radeon_enc_op_enc(struct radeon_encoder *enc) in radeon_enc_op_enc() argument
1073 static void radeon_enc_op_init_rc(struct radeon_encoder *enc) in radeon_enc_op_init_rc() argument
1079 static void radeon_enc_op_init_rc_vbv(struct radeon_encoder *enc) in radeon_enc_op_init_rc_vbv() argument
1085 static void radeon_enc_op_speed(struct radeon_encoder *enc) in radeon_enc_op_speed() argument
1091 static void begin(struct radeon_encoder *enc) in begin() argument
1093 enc->session_info(enc); in begin()
1094 enc->total_task_size = 0; in begin()
1095 enc->task_info(enc, enc->need_feedback); in begin()
1096 enc->op_init(enc); in begin()
1098 enc->session_init(enc); in begin()
1099 enc->slice_control(enc); in begin()
1100 enc->spec_misc(enc); in begin()
1101 enc->deblocking_filter(enc); in begin()
1103 enc->layer_control(enc); in begin()
1104 enc->rc_session_init(enc); in begin()
1105 enc->quality_params(enc); in begin()
1106 enc->layer_select(enc); in begin()
1107 enc->rc_layer_init(enc); in begin()
1108 enc->layer_select(enc); in begin()
1109 enc->rc_per_pic(enc); in begin()
1110 enc->op_init_rc(enc); in begin()
1111 enc->op_init_rc_vbv(enc); in begin()
1112 *enc->p_task_size = (enc->total_task_size); in begin()
1115 static void radeon_enc_headers_h264(struct radeon_encoder *enc) in radeon_enc_headers_h264() argument
1117 if (enc->enc_pic.is_idr) { in radeon_enc_headers_h264()
1118 enc->nalu_sps(enc); in radeon_enc_headers_h264()
1119 enc->nalu_pps(enc); in radeon_enc_headers_h264()
1121 enc->slice_header(enc); in radeon_enc_headers_h264()
1122 enc->encode_params(enc); in radeon_enc_headers_h264()
1123 enc->encode_params_codec_spec(enc); in radeon_enc_headers_h264()
1126 static void radeon_enc_headers_hevc(struct radeon_encoder *enc) in radeon_enc_headers_hevc() argument
1128 enc->nalu_aud(enc); in radeon_enc_headers_hevc()
1129 if (enc->enc_pic.is_idr) { in radeon_enc_headers_hevc()
1130 enc->nalu_vps(enc); in radeon_enc_headers_hevc()
1131 enc->nalu_pps(enc); in radeon_enc_headers_hevc()
1132 enc->nalu_sps(enc); in radeon_enc_headers_hevc()
1134 enc->slice_header(enc); in radeon_enc_headers_hevc()
1135 enc->encode_params(enc); in radeon_enc_headers_hevc()
1138 static void encode(struct radeon_encoder *enc) in encode() argument
1140 enc->session_info(enc); in encode()
1141 enc->total_task_size = 0; in encode()
1142 enc->task_info(enc, enc->need_feedback); in encode()
1144 enc->encode_headers(enc); in encode()
1145 enc->ctx(enc); in encode()
1146 enc->bitstream(enc); in encode()
1147 enc->feedback(enc); in encode()
1148 enc->intra_refresh(enc); in encode()
1150 enc->op_speed(enc); in encode()
1151 enc->op_enc(enc); in encode()
1152 *enc->p_task_size = (enc->total_task_size); in encode()
1155 static void destroy(struct radeon_encoder *enc) in destroy() argument
1157 enc->session_info(enc); in destroy()
1158 enc->total_task_size = 0; in destroy()
1159 enc->task_info(enc, enc->need_feedback); in destroy()
1160 enc->op_close(enc); in destroy()
1161 *enc->p_task_size = (enc->total_task_size); in destroy()
1164 void radeon_enc_1_2_init(struct radeon_encoder *enc) in radeon_enc_1_2_init() argument
1166 enc->begin = begin; in radeon_enc_1_2_init()
1167 enc->encode = encode; in radeon_enc_1_2_init()
1168 enc->destroy = destroy; in radeon_enc_1_2_init()
1169 enc->session_info = radeon_enc_session_info; in radeon_enc_1_2_init()
1170 enc->task_info = radeon_enc_task_info; in radeon_enc_1_2_init()
1171 enc->layer_control = radeon_enc_layer_control; in radeon_enc_1_2_init()
1172 enc->layer_select = radeon_enc_layer_select; in radeon_enc_1_2_init()
1173 enc->rc_session_init = radeon_enc_rc_session_init; in radeon_enc_1_2_init()
1174 enc->rc_layer_init = radeon_enc_rc_layer_init; in radeon_enc_1_2_init()
1175 enc->quality_params = radeon_enc_quality_params; in radeon_enc_1_2_init()
1176 enc->ctx = radeon_enc_ctx; in radeon_enc_1_2_init()
1177 enc->bitstream = radeon_enc_bitstream; in radeon_enc_1_2_init()
1178 enc->feedback = radeon_enc_feedback; in radeon_enc_1_2_init()
1179 enc->intra_refresh = radeon_enc_intra_refresh; in radeon_enc_1_2_init()
1180 enc->rc_per_pic = radeon_enc_rc_per_pic; in radeon_enc_1_2_init()
1181 enc->encode_params = radeon_enc_encode_params; in radeon_enc_1_2_init()
1182 enc->op_init = radeon_enc_op_init; in radeon_enc_1_2_init()
1183 enc->op_close = radeon_enc_op_close; in radeon_enc_1_2_init()
1184 enc->op_enc = radeon_enc_op_enc; in radeon_enc_1_2_init()
1185 enc->op_init_rc = radeon_enc_op_init_rc; in radeon_enc_1_2_init()
1186 enc->op_init_rc_vbv = radeon_enc_op_init_rc_vbv; in radeon_enc_1_2_init()
1187 enc->op_speed = radeon_enc_op_speed; in radeon_enc_1_2_init()
1189 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) { in radeon_enc_1_2_init()
1190 enc->session_init = radeon_enc_session_init; in radeon_enc_1_2_init()
1191 enc->slice_control = radeon_enc_slice_control; in radeon_enc_1_2_init()
1192 enc->spec_misc = radeon_enc_spec_misc; in radeon_enc_1_2_init()
1193 enc->deblocking_filter = radeon_enc_deblocking_filter_h264; in radeon_enc_1_2_init()
1194 enc->nalu_sps = radeon_enc_nalu_sps; in radeon_enc_1_2_init()
1195 enc->nalu_pps = radeon_enc_nalu_pps; in radeon_enc_1_2_init()
1196 enc->slice_header = radeon_enc_slice_header; in radeon_enc_1_2_init()
1197 enc->encode_params = radeon_enc_encode_params; in radeon_enc_1_2_init()
1198 enc->encode_params_codec_spec = radeon_enc_encode_params_h264; in radeon_enc_1_2_init()
1199 enc->encode_headers = radeon_enc_headers_h264; in radeon_enc_1_2_init()
1200 } else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) { in radeon_enc_1_2_init()
1201 enc->session_init = radeon_enc_session_init_hevc; in radeon_enc_1_2_init()
1202 enc->slice_control = radeon_enc_slice_control_hevc; in radeon_enc_1_2_init()
1203 enc->spec_misc = radeon_enc_spec_misc_hevc; in radeon_enc_1_2_init()
1204 enc->deblocking_filter = radeon_enc_deblocking_filter_hevc; in radeon_enc_1_2_init()
1205 enc->nalu_sps = radeon_enc_nalu_sps_hevc; in radeon_enc_1_2_init()
1206 enc->nalu_pps = radeon_enc_nalu_pps_hevc; in radeon_enc_1_2_init()
1207 enc->nalu_vps = radeon_enc_nalu_vps; in radeon_enc_1_2_init()
1208 enc->nalu_aud = radeon_enc_nalu_aud_hevc; in radeon_enc_1_2_init()
1209 enc->slice_header = radeon_enc_slice_header_hevc; in radeon_enc_1_2_init()
1210 enc->encode_params = radeon_enc_encode_params_hevc; in radeon_enc_1_2_init()
1211 enc->encode_headers = radeon_enc_headers_hevc; in radeon_enc_1_2_init()
1214 enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO; in radeon_enc_1_2_init()
1215 enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO; in radeon_enc_1_2_init()
1216 enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT; in radeon_enc_1_2_init()
1217 enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL; in radeon_enc_1_2_init()
1218 enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT; in radeon_enc_1_2_init()
1219 enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT; in radeon_enc_1_2_init()
1220 enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT; in radeon_enc_1_2_init()
1221 enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE; in radeon_enc_1_2_init()
1222 enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS; in radeon_enc_1_2_init()
1223 enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU; in radeon_enc_1_2_init()
1224 enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER; in radeon_enc_1_2_init()
1225 enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS; in radeon_enc_1_2_init()
1226 enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH; in radeon_enc_1_2_init()
1227 enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER; in radeon_enc_1_2_init()
1228 enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER; in radeon_enc_1_2_init()
1229 enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER; in radeon_enc_1_2_init()
1230 enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL; in radeon_enc_1_2_init()
1231 enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC; in radeon_enc_1_2_init()
1232 enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER; in radeon_enc_1_2_init()
1233 enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL; in radeon_enc_1_2_init()
1234 enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC; in radeon_enc_1_2_init()
1235 enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS; in radeon_enc_1_2_init()
1236 enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER; in radeon_enc_1_2_init()
1238 enc->enc_pic.session_info.interface_version = in radeon_enc_1_2_init()