Lines Matching refs:ins
89 mir_pack_mod(midgard_instruction *ins, unsigned i, bool scalar) in mir_pack_mod() argument
91 bool integer = midgard_is_integer_op(ins->op); in mir_pack_mod()
92 unsigned base_size = max_bitsize_for_alu(ins); in mir_pack_mod()
93 unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]); in mir_pack_mod()
97 mir_get_imod(ins->src_shift[i], ins->src_types[i], half, scalar) : in mir_pack_mod()
98 ((ins->src_abs[i] << 0) | in mir_pack_mod()
99 ((ins->src_neg[i] << 1))); in mir_pack_mod()
134 vector_to_scalar_alu(midgard_vector_alu v, midgard_instruction *ins) in vector_to_scalar_alu() argument
136 bool is_full = nir_alu_type_get_type_size(ins->dest_type) == 32; in vector_to_scalar_alu()
138 bool half_0 = nir_alu_type_get_type_size(ins->src_types[0]) == 16; in vector_to_scalar_alu()
139 bool half_1 = nir_alu_type_get_type_size(ins->src_types[1]) == 16; in vector_to_scalar_alu()
140 unsigned comp = component_from_mask(ins->mask); in vector_to_scalar_alu()
143 mir_pack_scalar_source(mir_pack_mod(ins, 0, true), !half_0, ins->swizzle[0][comp]), in vector_to_scalar_alu()
144 mir_pack_scalar_source(mir_pack_mod(ins, 1, true), !half_1, ins->swizzle[1][comp]) in vector_to_scalar_alu()
167 if (ins->has_inline_constant) { in vector_to_scalar_alu()
169 int lower_11 = ins->inline_constant & ((1 << 12) - 1); in vector_to_scalar_alu()
209 mir_pack_mask_alu(midgard_instruction *ins, midgard_vector_alu *alu) in mir_pack_mask_alu() argument
211 unsigned effective = ins->mask; in mir_pack_mask_alu()
217 unsigned inst_size = max_bitsize_for_alu(ins); in mir_pack_mask_alu()
218 signed upper_shift = mir_upper_override(ins, inst_size); in mir_pack_mask_alu()
331 mir_pack_vector_srcs(midgard_instruction *ins, midgard_vector_alu *alu) in mir_pack_vector_srcs() argument
333 bool channeled = GET_CHANNEL_COUNT(alu_opcode_props[ins->op].props); in mir_pack_vector_srcs()
335 unsigned base_size = max_bitsize_for_alu(ins); in mir_pack_vector_srcs()
338 if (ins->has_inline_constant && (i == 1)) in mir_pack_vector_srcs()
341 if (ins->src[i] == ~0) in mir_pack_vector_srcs()
344 unsigned sz = nir_alu_type_get_type_size(ins->src_types[i]); in mir_pack_vector_srcs()
348 unsigned swizzle = mir_pack_swizzle(ins->mask, ins->swizzle[i], in mir_pack_vector_srcs()
353 .mod = mir_pack_mod(ins, i, false), in mir_pack_vector_srcs()
368 mir_pack_swizzle_ldst(midgard_instruction *ins) in mir_pack_swizzle_ldst() argument
372 unsigned v = ins->swizzle[0][c]; in mir_pack_swizzle_ldst()
377 ins->load_store.swizzle |= v << (2 * c); in mir_pack_swizzle_ldst()
384 mir_pack_swizzle_tex(midgard_instruction *ins) in mir_pack_swizzle_tex() argument
390 unsigned v = ins->swizzle[i][c]; in mir_pack_swizzle_tex()
399 ins->texture.swizzle = packed; in mir_pack_swizzle_tex()
401 ins->texture.in_reg_swizzle = packed; in mir_pack_swizzle_tex()
426 midgard_instruction *ins = bundle->instructions[i]; in mir_can_run_ooo() local
428 mir_foreach_src(ins, s) { in mir_can_run_ooo()
429 if (ins->src[s] == dependency) in mir_can_run_ooo()
439 mir_pack_tex_ooo(midgard_block *block, midgard_bundle *bundle, midgard_instruction *ins) in mir_pack_tex_ooo() argument
444 if (!mir_can_run_ooo(block, bundle + count + 1, ins->dest)) in mir_pack_tex_ooo()
448 ins->texture.out_of_order = count; in mir_pack_tex_ooo()
459 midgard_pack_common_store_mask(midgard_instruction *ins) { in midgard_pack_common_store_mask() argument
460 unsigned comp_sz = nir_alu_type_get_type_size(ins->dest_type); in midgard_pack_common_store_mask()
461 unsigned mask = ins->mask; in midgard_pack_common_store_mask()
465 switch (ins->op) { in midgard_pack_common_store_mask()
484 if (ins->op == midgard_op_st_128) in midgard_pack_common_store_mask()
486 else if (ins->op == midgard_op_st_64) in midgard_pack_common_store_mask()
514 mir_pack_ldst_mask(midgard_instruction *ins) in mir_pack_ldst_mask() argument
516 unsigned sz = nir_alu_type_get_type_size(ins->dest_type); in mir_pack_ldst_mask()
517 unsigned packed = ins->mask; in mir_pack_ldst_mask()
519 if (OP_IS_COMMON_STORE(ins->op)) { in mir_pack_ldst_mask()
520 packed = midgard_pack_common_store_mask(ins); in mir_pack_ldst_mask()
523 packed = ((ins->mask & 0x2) ? (0x8 | 0x4) : 0) | in mir_pack_ldst_mask()
524 ((ins->mask & 0x1) ? (0x2 | 0x1) : 0); in mir_pack_ldst_mask()
530 bool u = (ins->mask & (1 << (2*i + 0))) != 0; in mir_pack_ldst_mask()
531 ASSERTED bool v = (ins->mask & (1 << (2*i + 1))) != 0; in mir_pack_ldst_mask()
541 ins->load_store.mask = packed; in mir_pack_ldst_mask()
545 mir_lower_inverts(midgard_instruction *ins) in mir_lower_inverts() argument
548 ins->src_invert[0], in mir_lower_inverts()
549 ins->src_invert[1], in mir_lower_inverts()
550 ins->src_invert[2] in mir_lower_inverts()
553 switch (ins->op) { in mir_lower_inverts()
559 ins->op = midgard_alu_op_inor; in mir_lower_inverts()
561 ins->op = midgard_alu_op_iandnot; in mir_lower_inverts()
569 ins->op = midgard_alu_op_inand; in mir_lower_inverts()
571 ins->op = midgard_alu_op_iornot; in mir_lower_inverts()
580 ins->op = midgard_alu_op_inxor; in mir_lower_inverts()
592 mir_lower_roundmode(midgard_instruction *ins) in mir_lower_roundmode() argument
594 if (alu_opcode_props[ins->op].props & MIDGARD_ROUNDS) { in mir_lower_roundmode()
595 assert(ins->roundmode <= 0x3); in mir_lower_roundmode()
596 ins->op += ins->roundmode; in mir_lower_roundmode()
601 load_store_from_instr(midgard_instruction *ins) in load_store_from_instr() argument
603 midgard_load_store_word ldst = ins->load_store; in load_store_from_instr()
604 ldst.op = ins->op; in load_store_from_instr()
607 ldst.reg = SSA_REG_FROM_FIXED(ins->src[0]) & 1; in load_store_from_instr()
609 ldst.reg = SSA_REG_FROM_FIXED(ins->dest); in load_store_from_instr()
615 if (OP_IS_ATOMIC(ins->op)) { in load_store_from_instr()
617 ldst.swizzle |= ins->swizzle[3][0] & 3; in load_store_from_instr()
618 ldst.swizzle |= (SSA_REG_FROM_FIXED(ins->src[3]) & 1 ? 1 : 0) << 2; in load_store_from_instr()
621 if (ins->src[1] != ~0) { in load_store_from_instr()
622 ldst.arg_reg = SSA_REG_FROM_FIXED(ins->src[1]) - REGISTER_LDST_BASE; in load_store_from_instr()
623 unsigned sz = nir_alu_type_get_type_size(ins->src_types[1]); in load_store_from_instr()
624 ldst.arg_comp = midgard_ldst_comp(ldst.arg_reg, ins->swizzle[1][0], sz); in load_store_from_instr()
627 if (ins->src[2] != ~0) { in load_store_from_instr()
628 ldst.index_reg = SSA_REG_FROM_FIXED(ins->src[2]) - REGISTER_LDST_BASE; in load_store_from_instr()
629 unsigned sz = nir_alu_type_get_type_size(ins->src_types[2]); in load_store_from_instr()
630 ldst.index_comp = midgard_ldst_comp(ldst.index_reg, ins->swizzle[2][0], sz); in load_store_from_instr()
637 texture_word_from_instr(midgard_instruction *ins) in texture_word_from_instr() argument
639 midgard_texture_word tex = ins->texture; in texture_word_from_instr()
640 tex.op = ins->op; in texture_word_from_instr()
642 unsigned src1 = ins->src[1] == ~0 ? REGISTER_UNUSED : SSA_REG_FROM_FIXED(ins->src[1]); in texture_word_from_instr()
645 unsigned dest = ins->dest == ~0 ? REGISTER_UNUSED : SSA_REG_FROM_FIXED(ins->dest); in texture_word_from_instr()
648 if (ins->src[2] != ~0) { in texture_word_from_instr()
650 .select = SSA_REG_FROM_FIXED(ins->src[2]) & 1, in texture_word_from_instr()
652 .component = ins->swizzle[2][0] in texture_word_from_instr()
659 if (ins->src[3] != ~0) { in texture_word_from_instr()
660 unsigned x = ins->swizzle[3][0]; in texture_word_from_instr()
667 unsigned offset_reg = SSA_REG_FROM_FIXED(ins->src[3]); in texture_word_from_instr()
681 vector_alu_from_instr(midgard_instruction *ins) in vector_alu_from_instr() argument
684 .op = ins->op, in vector_alu_from_instr()
685 .outmod = ins->outmod, in vector_alu_from_instr()
686 .reg_mode = reg_mode_for_bitsize(max_bitsize_for_alu(ins)) in vector_alu_from_instr()
689 if (ins->has_inline_constant) { in vector_alu_from_instr()
693 int lower_11 = ins->inline_constant & ((1 << 12) - 1); in vector_alu_from_instr()
735 emit_branch(midgard_instruction *ins, in emit_branch() argument
742 bool is_compact = ins->unit == ALU_ENAB_BR_COMPACT; in emit_branch()
743 bool is_conditional = ins->branch.conditional; in emit_branch()
744 bool is_inverted = ins->branch.invert_conditional; in emit_branch()
745 bool is_discard = ins->branch.target_type == TARGET_DISCARD; in emit_branch()
746 bool is_tilebuf_wait = ins->branch.target_type == TARGET_TILEBUF_WAIT; in emit_branch()
748 bool is_writeout = ins->writeout; in emit_branch()
751 int target_number = ins->branch.target_block; in emit_branch()
856 midgard_instruction *ins = bundle->instructions[i]; in emit_alu_bundle() local
859 if (ins->compact_branch) continue; in emit_alu_bundle()
862 if (ins->has_inline_constant) in emit_alu_bundle()
863 src2_reg = ins->inline_constant >> 11; in emit_alu_bundle()
864 else if (ins->src[1] != ~0) in emit_alu_bundle()
865 src2_reg = SSA_REG_FROM_FIXED(ins->src[1]); in emit_alu_bundle()
870 .src1_reg = (ins->src[0] == ~0 ? in emit_alu_bundle()
872 SSA_REG_FROM_FIXED(ins->src[0])), in emit_alu_bundle()
874 .src2_imm = ins->has_inline_constant, in emit_alu_bundle()
875 .out_reg = (ins->dest == ~0 ? in emit_alu_bundle()
877 SSA_REG_FROM_FIXED(ins->dest)), in emit_alu_bundle()
885 midgard_instruction *ins = bundle->instructions[i]; in emit_alu_bundle() local
887 if (!ins->compact_branch) { in emit_alu_bundle()
888 mir_lower_inverts(ins); in emit_alu_bundle()
889 mir_lower_roundmode(ins); in emit_alu_bundle()
892 if (midgard_is_branch_unit(ins->unit)) { in emit_alu_bundle()
893 emit_branch(ins, ctx, block, bundle, emission); in emit_alu_bundle()
894 } else if (ins->unit & UNITS_ANY_VECTOR) { in emit_alu_bundle()
895 midgard_vector_alu source = vector_alu_from_instr(ins); in emit_alu_bundle()
896 mir_pack_mask_alu(ins, &source); in emit_alu_bundle()
897 mir_pack_vector_srcs(ins, &source); in emit_alu_bundle()
901 … midgard_scalar_alu source = vector_to_scalar_alu(vector_alu_from_instr(ins), ins); in emit_alu_bundle()
924 mir_ldst_pack_offset(midgard_instruction *ins, int offset) in mir_ldst_pack_offset() argument
927 assert(!OP_IS_REG2REG_LDST(ins->op) || in mir_ldst_pack_offset()
928 ins->op == midgard_op_lea || in mir_ldst_pack_offset()
929 ins->op == midgard_op_lea_image); in mir_ldst_pack_offset()
931 if (OP_IS_UBO_READ(ins->op)) in mir_ldst_pack_offset()
932 ins->load_store.signed_offset |= PACK_LDST_UBO_OFS(offset); in mir_ldst_pack_offset()
933 else if (OP_IS_IMAGE(ins->op)) in mir_ldst_pack_offset()
934 ins->load_store.signed_offset |= PACK_LDST_ATTRIB_OFS(offset); in mir_ldst_pack_offset()
935 else if (OP_IS_SPECIAL(ins->op)) in mir_ldst_pack_offset()
936 ins->load_store.signed_offset |= PACK_LDST_SELECTOR_OFS(offset); in mir_ldst_pack_offset()
938 ins->load_store.signed_offset |= PACK_LDST_MEM_OFS(offset); in mir_ldst_pack_offset()
987 midgard_instruction *ins = bundle->instructions[i]; in emit_binary_bundle() local
988 mir_pack_ldst_mask(ins); in emit_binary_bundle()
991 if (!OP_IS_ATOMIC(ins->op)) in emit_binary_bundle()
992 mir_pack_swizzle_ldst(ins); in emit_binary_bundle()
995 unsigned offset = ins->constants.u32[0]; in emit_binary_bundle()
997 mir_ldst_pack_offset(ins, offset); in emit_binary_bundle()
1029 midgard_instruction *ins = bundle->instructions[0]; in emit_binary_bundle() local
1031 ins->texture.type = bundle->tag; in emit_binary_bundle()
1032 ins->texture.next_type = next_tag; in emit_binary_bundle()
1035 if (ins->op == midgard_tex_op_barrier) { in emit_binary_bundle()
1036 ins->texture.cont = ins->texture.last = 1; in emit_binary_bundle()
1037 ins->texture.op = ins->op; in emit_binary_bundle()
1038 util_dynarray_append(emission, midgard_texture_word, ins->texture); in emit_binary_bundle()
1042 signed override = mir_upper_override(ins, 32); in emit_binary_bundle()
1044 ins->texture.mask = override > 0 ? in emit_binary_bundle()
1045 ins->mask >> override : in emit_binary_bundle()
1046 ins->mask; in emit_binary_bundle()
1048 mir_pack_swizzle_tex(ins); in emit_binary_bundle()
1051 mir_pack_tex_ooo(block, bundle, ins); in emit_binary_bundle()
1053 unsigned osz = nir_alu_type_get_type_size(ins->dest_type); in emit_binary_bundle()
1054 unsigned isz = nir_alu_type_get_type_size(ins->src_types[1]); in emit_binary_bundle()
1059 ins->texture.out_full = (osz == 32); in emit_binary_bundle()
1060 ins->texture.out_upper = override > 0; in emit_binary_bundle()
1061 ins->texture.in_reg_full = (isz == 32); in emit_binary_bundle()
1062 ins->texture.sampler_type = midgard_sampler_type(ins->dest_type); in emit_binary_bundle()
1063 ins->texture.outmod = ins->outmod; in emit_binary_bundle()
1065 if (mir_op_computes_derivatives(ctx->stage, ins->op)) { in emit_binary_bundle()
1066 ins->texture.cont = !ins->helper_terminate; in emit_binary_bundle()
1067 ins->texture.last = ins->helper_terminate || ins->helper_execute; in emit_binary_bundle()
1069 ins->texture.cont = ins->texture.last = 1; in emit_binary_bundle()
1072 midgard_texture_word texture = texture_word_from_instr(ins); in emit_binary_bundle()