Lines Matching refs:enc
66 static void radeon_enc_session_info(struct radeon_encoder *enc) in radeon_enc_session_info() argument
68 RADEON_ENC_BEGIN(enc->cmd.session_info); in radeon_enc_session_info()
69 RADEON_ENC_CS(enc->enc_pic.session_info.interface_version); in radeon_enc_session_info()
70 RADEON_ENC_READWRITE(enc->si->res->buf, enc->si->res->domains, 0x0); in radeon_enc_session_info()
75 static void radeon_enc_task_info(struct radeon_encoder *enc, bool need_feedback) in radeon_enc_task_info() argument
77 enc->enc_pic.task_info.task_id++; in radeon_enc_task_info()
80 enc->enc_pic.task_info.allowed_max_num_feedbacks = 1; in radeon_enc_task_info()
82 enc->enc_pic.task_info.allowed_max_num_feedbacks = 0; in radeon_enc_task_info()
84 RADEON_ENC_BEGIN(enc->cmd.task_info); in radeon_enc_task_info()
85 enc->p_task_size = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_enc_task_info()
86 RADEON_ENC_CS(enc->enc_pic.task_info.task_id); in radeon_enc_task_info()
87 RADEON_ENC_CS(enc->enc_pic.task_info.allowed_max_num_feedbacks); in radeon_enc_task_info()
91 static void radeon_enc_session_init(struct radeon_encoder *enc) in radeon_enc_session_init() argument
93 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_H264; in radeon_enc_session_init()
94 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 16); in radeon_enc_session_init()
95 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16); in radeon_enc_session_init()
96 enc->enc_pic.session_init.padding_width = in radeon_enc_session_init()
97 enc->enc_pic.session_init.aligned_picture_width - enc->base.width; in radeon_enc_session_init()
98 enc->enc_pic.session_init.padding_height = in radeon_enc_session_init()
99 enc->enc_pic.session_init.aligned_picture_height - enc->base.height; in radeon_enc_session_init()
100 enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE; in radeon_enc_session_init()
101 enc->enc_pic.session_init.pre_encode_chroma_enabled = false; in radeon_enc_session_init()
103 RADEON_ENC_BEGIN(enc->cmd.session_init); in radeon_enc_session_init()
104 RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard); in radeon_enc_session_init()
105 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width); in radeon_enc_session_init()
106 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height); in radeon_enc_session_init()
107 RADEON_ENC_CS(enc->enc_pic.session_init.padding_width); in radeon_enc_session_init()
108 RADEON_ENC_CS(enc->enc_pic.session_init.padding_height); in radeon_enc_session_init()
109 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode); in radeon_enc_session_init()
110 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled); in radeon_enc_session_init()
114 static void radeon_enc_session_init_hevc(struct radeon_encoder *enc) in radeon_enc_session_init_hevc() argument
116 enc->enc_pic.session_init.encode_standard = RENCODE_ENCODE_STANDARD_HEVC; in radeon_enc_session_init_hevc()
117 enc->enc_pic.session_init.aligned_picture_width = align(enc->base.width, 64); in radeon_enc_session_init_hevc()
118 enc->enc_pic.session_init.aligned_picture_height = align(enc->base.height, 16); in radeon_enc_session_init_hevc()
119 enc->enc_pic.session_init.padding_width = in radeon_enc_session_init_hevc()
120 enc->enc_pic.session_init.aligned_picture_width - enc->base.width; in radeon_enc_session_init_hevc()
121 enc->enc_pic.session_init.padding_height = in radeon_enc_session_init_hevc()
122 enc->enc_pic.session_init.aligned_picture_height - enc->base.height; in radeon_enc_session_init_hevc()
123 enc->enc_pic.session_init.pre_encode_mode = RENCODE_PREENCODE_MODE_NONE; in radeon_enc_session_init_hevc()
124 enc->enc_pic.session_init.pre_encode_chroma_enabled = false; in radeon_enc_session_init_hevc()
126 RADEON_ENC_BEGIN(enc->cmd.session_init); in radeon_enc_session_init_hevc()
127 RADEON_ENC_CS(enc->enc_pic.session_init.encode_standard); in radeon_enc_session_init_hevc()
128 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_width); in radeon_enc_session_init_hevc()
129 RADEON_ENC_CS(enc->enc_pic.session_init.aligned_picture_height); in radeon_enc_session_init_hevc()
130 RADEON_ENC_CS(enc->enc_pic.session_init.padding_width); in radeon_enc_session_init_hevc()
131 RADEON_ENC_CS(enc->enc_pic.session_init.padding_height); in radeon_enc_session_init_hevc()
132 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_mode); in radeon_enc_session_init_hevc()
133 RADEON_ENC_CS(enc->enc_pic.session_init.pre_encode_chroma_enabled); in radeon_enc_session_init_hevc()
137 static void radeon_enc_layer_control(struct radeon_encoder *enc) in radeon_enc_layer_control() argument
139 enc->enc_pic.layer_ctrl.max_num_temporal_layers = enc->enc_pic.num_temporal_layers; in radeon_enc_layer_control()
140 enc->enc_pic.layer_ctrl.num_temporal_layers = enc->enc_pic.num_temporal_layers; in radeon_enc_layer_control()
142 RADEON_ENC_BEGIN(enc->cmd.layer_control); in radeon_enc_layer_control()
143 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.max_num_temporal_layers); in radeon_enc_layer_control()
144 RADEON_ENC_CS(enc->enc_pic.layer_ctrl.num_temporal_layers); in radeon_enc_layer_control()
148 static void radeon_enc_layer_select(struct radeon_encoder *enc) in radeon_enc_layer_select() argument
150 enc->enc_pic.layer_sel.temporal_layer_index = enc->enc_pic.temporal_id; in radeon_enc_layer_select()
152 RADEON_ENC_BEGIN(enc->cmd.layer_select); in radeon_enc_layer_select()
153 RADEON_ENC_CS(enc->enc_pic.layer_sel.temporal_layer_index); in radeon_enc_layer_select()
157 static void radeon_enc_slice_control(struct radeon_encoder *enc) in radeon_enc_slice_control() argument
159 enc->enc_pic.slice_ctrl.slice_control_mode = RENCODE_H264_SLICE_CONTROL_MODE_FIXED_MBS; in radeon_enc_slice_control()
160 enc->enc_pic.slice_ctrl.num_mbs_per_slice = in radeon_enc_slice_control()
161 align(enc->base.width, 16) / 16 * align(enc->base.height, 16) / 16; in radeon_enc_slice_control()
163 RADEON_ENC_BEGIN(enc->cmd.slice_control_h264); in radeon_enc_slice_control()
164 RADEON_ENC_CS(enc->enc_pic.slice_ctrl.slice_control_mode); in radeon_enc_slice_control()
165 RADEON_ENC_CS(enc->enc_pic.slice_ctrl.num_mbs_per_slice); in radeon_enc_slice_control()
169 static void radeon_enc_slice_control_hevc(struct radeon_encoder *enc) in radeon_enc_slice_control_hevc() argument
171 enc->enc_pic.hevc_slice_ctrl.slice_control_mode = RENCODE_HEVC_SLICE_CONTROL_MODE_FIXED_CTBS; in radeon_enc_slice_control_hevc()
172 enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice = in radeon_enc_slice_control_hevc()
173 align(enc->base.width, 64) / 64 * align(enc->base.height, 64) / 64; in radeon_enc_slice_control_hevc()
174 enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment = in radeon_enc_slice_control_hevc()
175 enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice; in radeon_enc_slice_control_hevc()
177 RADEON_ENC_BEGIN(enc->cmd.slice_control_hevc); in radeon_enc_slice_control_hevc()
178 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.slice_control_mode); in radeon_enc_slice_control_hevc()
179 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice); in radeon_enc_slice_control_hevc()
180 RADEON_ENC_CS(enc->enc_pic.hevc_slice_ctrl.fixed_ctbs_per_slice.num_ctbs_per_slice_segment); in radeon_enc_slice_control_hevc()
184 static void radeon_enc_spec_misc(struct radeon_encoder *enc) in radeon_enc_spec_misc() argument
186 enc->enc_pic.spec_misc.constrained_intra_pred_flag = 0; in radeon_enc_spec_misc()
187 enc->enc_pic.spec_misc.cabac_enable = 0; in radeon_enc_spec_misc()
188 enc->enc_pic.spec_misc.cabac_init_idc = 0; in radeon_enc_spec_misc()
189 enc->enc_pic.spec_misc.half_pel_enabled = 1; in radeon_enc_spec_misc()
190 enc->enc_pic.spec_misc.quarter_pel_enabled = 1; in radeon_enc_spec_misc()
191 enc->enc_pic.spec_misc.profile_idc = u_get_h264_profile_idc(enc->base.profile); in radeon_enc_spec_misc()
192 enc->enc_pic.spec_misc.level_idc = enc->base.level; in radeon_enc_spec_misc()
194 RADEON_ENC_BEGIN(enc->cmd.spec_misc_h264); in radeon_enc_spec_misc()
195 RADEON_ENC_CS(enc->enc_pic.spec_misc.constrained_intra_pred_flag); in radeon_enc_spec_misc()
196 RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_enable); in radeon_enc_spec_misc()
197 RADEON_ENC_CS(enc->enc_pic.spec_misc.cabac_init_idc); in radeon_enc_spec_misc()
198 RADEON_ENC_CS(enc->enc_pic.spec_misc.half_pel_enabled); in radeon_enc_spec_misc()
199 RADEON_ENC_CS(enc->enc_pic.spec_misc.quarter_pel_enabled); in radeon_enc_spec_misc()
200 RADEON_ENC_CS(enc->enc_pic.spec_misc.profile_idc); in radeon_enc_spec_misc()
201 RADEON_ENC_CS(enc->enc_pic.spec_misc.level_idc); in radeon_enc_spec_misc()
205 static void radeon_enc_spec_misc_hevc(struct radeon_encoder *enc) in radeon_enc_spec_misc_hevc() argument
207 RADEON_ENC_BEGIN(enc->cmd.spec_misc_hevc); in radeon_enc_spec_misc_hevc()
208 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3); in radeon_enc_spec_misc_hevc()
209 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.amp_disabled); in radeon_enc_spec_misc_hevc()
210 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled); in radeon_enc_spec_misc_hevc()
211 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag); in radeon_enc_spec_misc_hevc()
212 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.cabac_init_flag); in radeon_enc_spec_misc_hevc()
213 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.half_pel_enabled); in radeon_enc_spec_misc_hevc()
214 RADEON_ENC_CS(enc->enc_pic.hevc_spec_misc.quarter_pel_enabled); in radeon_enc_spec_misc_hevc()
218 static void radeon_enc_rc_session_init(struct radeon_encoder *enc) in radeon_enc_rc_session_init() argument
220 RADEON_ENC_BEGIN(enc->cmd.rc_session_init); in radeon_enc_rc_session_init()
221 RADEON_ENC_CS(enc->enc_pic.rc_session_init.rate_control_method); in radeon_enc_rc_session_init()
222 RADEON_ENC_CS(enc->enc_pic.rc_session_init.vbv_buffer_level); in radeon_enc_rc_session_init()
226 static void radeon_enc_rc_layer_init(struct radeon_encoder *enc) in radeon_enc_rc_layer_init() argument
228 unsigned int i = enc->enc_pic.temporal_id; in radeon_enc_rc_layer_init()
229 RADEON_ENC_BEGIN(enc->cmd.rc_layer_init); in radeon_enc_rc_layer_init()
230 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].target_bit_rate); in radeon_enc_rc_layer_init()
231 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].peak_bit_rate); in radeon_enc_rc_layer_init()
232 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].frame_rate_num); in radeon_enc_rc_layer_init()
233 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].frame_rate_den); in radeon_enc_rc_layer_init()
234 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].vbv_buffer_size); in radeon_enc_rc_layer_init()
235 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].avg_target_bits_per_picture); in radeon_enc_rc_layer_init()
236 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_integer); in radeon_enc_rc_layer_init()
237 RADEON_ENC_CS(enc->enc_pic.rc_layer_init[i].peak_bits_per_picture_fractional); in radeon_enc_rc_layer_init()
241 static void radeon_enc_deblocking_filter_h264(struct radeon_encoder *enc) in radeon_enc_deblocking_filter_h264() argument
243 enc->enc_pic.h264_deblock.disable_deblocking_filter_idc = 0; in radeon_enc_deblocking_filter_h264()
244 enc->enc_pic.h264_deblock.alpha_c0_offset_div2 = 0; in radeon_enc_deblocking_filter_h264()
245 enc->enc_pic.h264_deblock.beta_offset_div2 = 0; in radeon_enc_deblocking_filter_h264()
246 enc->enc_pic.h264_deblock.cb_qp_offset = 0; in radeon_enc_deblocking_filter_h264()
247 enc->enc_pic.h264_deblock.cr_qp_offset = 0; in radeon_enc_deblocking_filter_h264()
249 RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_h264); in radeon_enc_deblocking_filter_h264()
250 RADEON_ENC_CS(enc->enc_pic.h264_deblock.disable_deblocking_filter_idc); in radeon_enc_deblocking_filter_h264()
251 RADEON_ENC_CS(enc->enc_pic.h264_deblock.alpha_c0_offset_div2); in radeon_enc_deblocking_filter_h264()
252 RADEON_ENC_CS(enc->enc_pic.h264_deblock.beta_offset_div2); in radeon_enc_deblocking_filter_h264()
253 RADEON_ENC_CS(enc->enc_pic.h264_deblock.cb_qp_offset); in radeon_enc_deblocking_filter_h264()
254 RADEON_ENC_CS(enc->enc_pic.h264_deblock.cr_qp_offset); in radeon_enc_deblocking_filter_h264()
258 static void radeon_enc_deblocking_filter_hevc(struct radeon_encoder *enc) in radeon_enc_deblocking_filter_hevc() argument
260 RADEON_ENC_BEGIN(enc->cmd.deblocking_filter_hevc); in radeon_enc_deblocking_filter_hevc()
261 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled); in radeon_enc_deblocking_filter_hevc()
262 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.deblocking_filter_disabled); in radeon_enc_deblocking_filter_hevc()
263 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_enc_deblocking_filter_hevc()
264 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.tc_offset_div2); in radeon_enc_deblocking_filter_hevc()
265 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cb_qp_offset); in radeon_enc_deblocking_filter_hevc()
266 RADEON_ENC_CS(enc->enc_pic.hevc_deblock.cr_qp_offset); in radeon_enc_deblocking_filter_hevc()
270 static void radeon_enc_quality_params(struct radeon_encoder *enc) in radeon_enc_quality_params() argument
272 enc->enc_pic.quality_params.vbaq_mode = 0; in radeon_enc_quality_params()
273 enc->enc_pic.quality_params.scene_change_sensitivity = 0; in radeon_enc_quality_params()
274 enc->enc_pic.quality_params.scene_change_min_idr_interval = 0; in radeon_enc_quality_params()
276 RADEON_ENC_BEGIN(enc->cmd.quality_params); in radeon_enc_quality_params()
277 RADEON_ENC_CS(enc->enc_pic.quality_params.vbaq_mode); in radeon_enc_quality_params()
278 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_sensitivity); in radeon_enc_quality_params()
279 RADEON_ENC_CS(enc->enc_pic.quality_params.scene_change_min_idr_interval); in radeon_enc_quality_params()
283 static void radeon_enc_nalu_sps(struct radeon_encoder *enc) in radeon_enc_nalu_sps() argument
285 RADEON_ENC_BEGIN(enc->cmd.nalu); in radeon_enc_nalu_sps()
287 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_enc_nalu_sps()
288 radeon_enc_reset(enc); in radeon_enc_nalu_sps()
289 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_nalu_sps()
290 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); in radeon_enc_nalu_sps()
291 radeon_enc_code_fixed_bits(enc, 0x67, 8); in radeon_enc_nalu_sps()
292 radeon_enc_byte_align(enc); in radeon_enc_nalu_sps()
293 radeon_enc_set_emulation_prevention(enc, true); in radeon_enc_nalu_sps()
294 radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.profile_idc, 8); in radeon_enc_nalu_sps()
295 radeon_enc_code_fixed_bits(enc, 0x44, 8); // hardcode to constrained baseline in radeon_enc_nalu_sps()
296 radeon_enc_code_fixed_bits(enc, enc->enc_pic.spec_misc.level_idc, 8); in radeon_enc_nalu_sps()
297 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps()
299 if (enc->enc_pic.spec_misc.profile_idc == 100 || enc->enc_pic.spec_misc.profile_idc == 110 || in radeon_enc_nalu_sps()
300 enc->enc_pic.spec_misc.profile_idc == 122 || enc->enc_pic.spec_misc.profile_idc == 244 || in radeon_enc_nalu_sps()
301 enc->enc_pic.spec_misc.profile_idc == 44 || enc->enc_pic.spec_misc.profile_idc == 83 || in radeon_enc_nalu_sps()
302 enc->enc_pic.spec_misc.profile_idc == 86 || enc->enc_pic.spec_misc.profile_idc == 118 || in radeon_enc_nalu_sps()
303 enc->enc_pic.spec_misc.profile_idc == 128 || enc->enc_pic.spec_misc.profile_idc == 138) { in radeon_enc_nalu_sps()
304 radeon_enc_code_ue(enc, 0x1); in radeon_enc_nalu_sps()
305 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps()
306 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps()
307 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_sps()
310 radeon_enc_code_ue(enc, 1); in radeon_enc_nalu_sps()
311 radeon_enc_code_ue(enc, enc->enc_pic.pic_order_cnt_type); in radeon_enc_nalu_sps()
313 if (enc->enc_pic.pic_order_cnt_type == 0) in radeon_enc_nalu_sps()
314 radeon_enc_code_ue(enc, 1); in radeon_enc_nalu_sps()
316 radeon_enc_code_ue(enc, (enc->base.max_references + 1)); in radeon_enc_nalu_sps()
317 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers > 1 ? 0x1 : 0x0, in radeon_enc_nalu_sps()
319 radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_width / 16 - 1)); in radeon_enc_nalu_sps()
320 radeon_enc_code_ue(enc, (enc->enc_pic.session_init.aligned_picture_height / 16 - 1)); in radeon_enc_nalu_sps()
322 radeon_enc_code_fixed_bits(enc, progressive_only ? 0x1 : 0x0, 1); in radeon_enc_nalu_sps()
325 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps()
327 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps()
329 if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right != 0) || in radeon_enc_nalu_sps()
330 (enc->enc_pic.crop_top != 0) || (enc->enc_pic.crop_bottom != 0)) { in radeon_enc_nalu_sps()
331 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps()
332 radeon_enc_code_ue(enc, enc->enc_pic.crop_left); in radeon_enc_nalu_sps()
333 radeon_enc_code_ue(enc, enc->enc_pic.crop_right); in radeon_enc_nalu_sps()
334 radeon_enc_code_ue(enc, enc->enc_pic.crop_top); in radeon_enc_nalu_sps()
335 radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom); in radeon_enc_nalu_sps()
337 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps()
339 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps()
340 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps()
341 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps()
342 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps()
343 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps()
344 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps()
345 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps()
346 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps()
347 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps()
348 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps()
349 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps()
350 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps()
351 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps()
352 radeon_enc_code_ue(enc, 16); in radeon_enc_nalu_sps()
353 radeon_enc_code_ue(enc, 16); in radeon_enc_nalu_sps()
354 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps()
355 radeon_enc_code_ue(enc, (enc->base.max_references + 1)); in radeon_enc_nalu_sps()
357 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps()
359 radeon_enc_byte_align(enc); in radeon_enc_nalu_sps()
360 radeon_enc_flush_headers(enc); in radeon_enc_nalu_sps()
361 *size_in_bytes = (enc->bits_output + 7) / 8; in radeon_enc_nalu_sps()
365 static void radeon_enc_nalu_sps_hevc(struct radeon_encoder *enc) in radeon_enc_nalu_sps_hevc() argument
367 RADEON_ENC_BEGIN(enc->cmd.nalu); in radeon_enc_nalu_sps_hevc()
369 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_enc_nalu_sps_hevc()
372 radeon_enc_reset(enc); in radeon_enc_nalu_sps_hevc()
373 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_nalu_sps_hevc()
374 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); in radeon_enc_nalu_sps_hevc()
375 radeon_enc_code_fixed_bits(enc, 0x4201, 16); in radeon_enc_nalu_sps_hevc()
376 radeon_enc_byte_align(enc); in radeon_enc_nalu_sps_hevc()
377 radeon_enc_set_emulation_prevention(enc, true); in radeon_enc_nalu_sps_hevc()
378 radeon_enc_code_fixed_bits(enc, 0x0, 4); in radeon_enc_nalu_sps_hevc()
379 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3); in radeon_enc_nalu_sps_hevc()
380 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps_hevc()
381 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_sps_hevc()
382 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1); in radeon_enc_nalu_sps_hevc()
383 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5); in radeon_enc_nalu_sps_hevc()
384 radeon_enc_code_fixed_bits(enc, 0x60000000, 32); in radeon_enc_nalu_sps_hevc()
385 radeon_enc_code_fixed_bits(enc, 0xb0000000, 32); in radeon_enc_nalu_sps_hevc()
386 radeon_enc_code_fixed_bits(enc, 0x0, 16); in radeon_enc_nalu_sps_hevc()
387 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8); in radeon_enc_nalu_sps_hevc()
389 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++) in radeon_enc_nalu_sps_hevc()
390 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_sps_hevc()
392 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) { in radeon_enc_nalu_sps_hevc()
393 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++) in radeon_enc_nalu_sps_hevc()
394 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_sps_hevc()
397 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps_hevc()
398 radeon_enc_code_ue(enc, enc->enc_pic.chroma_format_idc); in radeon_enc_nalu_sps_hevc()
399 radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_width); in radeon_enc_nalu_sps_hevc()
400 radeon_enc_code_ue(enc, enc->enc_pic.session_init.aligned_picture_height); in radeon_enc_nalu_sps_hevc()
402 if ((enc->enc_pic.crop_left != 0) || (enc->enc_pic.crop_right != 0) || in radeon_enc_nalu_sps_hevc()
403 (enc->enc_pic.crop_top != 0) || (enc->enc_pic.crop_bottom != 0)) { in radeon_enc_nalu_sps_hevc()
404 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps_hevc()
405 radeon_enc_code_ue(enc, enc->enc_pic.crop_left); in radeon_enc_nalu_sps_hevc()
406 radeon_enc_code_ue(enc, enc->enc_pic.crop_right); in radeon_enc_nalu_sps_hevc()
407 radeon_enc_code_ue(enc, enc->enc_pic.crop_top); in radeon_enc_nalu_sps_hevc()
408 radeon_enc_code_ue(enc, enc->enc_pic.crop_bottom); in radeon_enc_nalu_sps_hevc()
409 } else if (enc->enc_pic.session_init.padding_width != 0 || in radeon_enc_nalu_sps_hevc()
410 enc->enc_pic.session_init.padding_height != 0) { in radeon_enc_nalu_sps_hevc()
411 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps_hevc()
412 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_width / 2); in radeon_enc_nalu_sps_hevc()
413 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_width / 2); in radeon_enc_nalu_sps_hevc()
414 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_height / 2); in radeon_enc_nalu_sps_hevc()
415 radeon_enc_code_ue(enc, enc->enc_pic.session_init.padding_height / 2); in radeon_enc_nalu_sps_hevc()
417 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
419 radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_luma_minus8); in radeon_enc_nalu_sps_hevc()
420 radeon_enc_code_ue(enc, enc->enc_pic.bit_depth_chroma_minus8); in radeon_enc_nalu_sps_hevc()
421 radeon_enc_code_ue(enc, enc->enc_pic.log2_max_poc - 4); in radeon_enc_nalu_sps_hevc()
422 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
423 radeon_enc_code_ue(enc, 1); in radeon_enc_nalu_sps_hevc()
424 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps_hevc()
425 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_sps_hevc()
426 radeon_enc_code_ue(enc, enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3); in radeon_enc_nalu_sps_hevc()
428 radeon_enc_code_ue(enc, in radeon_enc_nalu_sps_hevc()
429 6 - (enc->enc_pic.hevc_spec_misc.log2_min_luma_coding_block_size_minus3 + 3)); in radeon_enc_nalu_sps_hevc()
430 radeon_enc_code_ue(enc, enc->enc_pic.log2_min_transform_block_size_minus2); in radeon_enc_nalu_sps_hevc()
431 radeon_enc_code_ue(enc, enc->enc_pic.log2_diff_max_min_transform_block_size); in radeon_enc_nalu_sps_hevc()
432 radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_inter); in radeon_enc_nalu_sps_hevc()
433 radeon_enc_code_ue(enc, enc->enc_pic.max_transform_hierarchy_depth_intra); in radeon_enc_nalu_sps_hevc()
435 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
436 radeon_enc_code_fixed_bits(enc, !enc->enc_pic.hevc_spec_misc.amp_disabled, 1); in radeon_enc_nalu_sps_hevc()
437 radeon_enc_code_fixed_bits(enc, enc->enc_pic.sample_adaptive_offset_enabled_flag, 1); in radeon_enc_nalu_sps_hevc()
438 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pcm_enabled_flag, 1); in radeon_enc_nalu_sps_hevc()
440 radeon_enc_code_ue(enc, 1); in radeon_enc_nalu_sps_hevc()
441 radeon_enc_code_ue(enc, 1); in radeon_enc_nalu_sps_hevc()
442 radeon_enc_code_ue(enc, 0); in radeon_enc_nalu_sps_hevc()
443 radeon_enc_code_ue(enc, 0); in radeon_enc_nalu_sps_hevc()
444 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps_hevc()
446 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
448 radeon_enc_code_fixed_bits(enc, 0, 1); in radeon_enc_nalu_sps_hevc()
449 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.strong_intra_smoothing_enabled, 1); in radeon_enc_nalu_sps_hevc()
451 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
453 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sps_hevc()
455 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sps_hevc()
457 radeon_enc_byte_align(enc); in radeon_enc_nalu_sps_hevc()
458 radeon_enc_flush_headers(enc); in radeon_enc_nalu_sps_hevc()
459 *size_in_bytes = (enc->bits_output + 7) / 8; in radeon_enc_nalu_sps_hevc()
463 static void radeon_enc_nalu_prefix(struct radeon_encoder *enc) in radeon_enc_nalu_prefix() argument
465 uint nalRefIdc = enc->enc_pic.is_idr ? 3 : 0; in radeon_enc_nalu_prefix()
468 table_info = rvcn_temporal_layer_pattern_tables[enc->enc_pic.layer_ctrl.num_temporal_layers]; in radeon_enc_nalu_prefix()
470 if (enc->enc_pic.pic_order_cnt == 0) in radeon_enc_nalu_prefix()
471 enc->enc_pic.temporal_layer_pattern_index = 0; in radeon_enc_nalu_prefix()
472 else if(enc->enc_pic.temporal_layer_pattern_index == (table_info.pattern_size - 1)) in radeon_enc_nalu_prefix()
473 enc->enc_pic.temporal_layer_pattern_index = 1; in radeon_enc_nalu_prefix()
475 enc->enc_pic.temporal_layer_pattern_index++; in radeon_enc_nalu_prefix()
478 table_info.pattern_table[enc->enc_pic.temporal_layer_pattern_index]; in radeon_enc_nalu_prefix()
480 RADEON_ENC_BEGIN(enc->cmd.nalu); in radeon_enc_nalu_prefix()
482 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_enc_nalu_prefix()
483 radeon_enc_reset(enc); in radeon_enc_nalu_prefix()
484 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_nalu_prefix()
485 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); in radeon_enc_nalu_prefix()
486 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_prefix()
487 radeon_enc_code_fixed_bits(enc, nalRefIdc, 2); in radeon_enc_nalu_prefix()
488 radeon_enc_code_fixed_bits(enc, 14, 5); in radeon_enc_nalu_prefix()
489 radeon_enc_byte_align(enc); in radeon_enc_nalu_prefix()
490 radeon_enc_set_emulation_prevention(enc, true); in radeon_enc_nalu_prefix()
491 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_prefix()
492 radeon_enc_code_fixed_bits(enc, enc->enc_pic.is_idr ? 0x1 : 0x0, 1); in radeon_enc_nalu_prefix()
493 radeon_enc_code_fixed_bits(enc, 0x0, 6); in radeon_enc_nalu_prefix()
494 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_prefix()
495 radeon_enc_code_fixed_bits(enc, 0x0, 3); in radeon_enc_nalu_prefix()
496 radeon_enc_code_fixed_bits(enc, 0x0, 4); in radeon_enc_nalu_prefix()
497 radeon_enc_code_fixed_bits(enc, pattern.temporal_id, 3); in radeon_enc_nalu_prefix()
498 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_prefix()
499 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_prefix()
500 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_prefix()
501 radeon_enc_code_fixed_bits(enc, 0x3, 2); in radeon_enc_nalu_prefix()
505 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_prefix()
506 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_prefix()
507 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_prefix()
508 radeon_enc_byte_align(enc); in radeon_enc_nalu_prefix()
511 radeon_enc_flush_headers(enc); in radeon_enc_nalu_prefix()
512 *size_in_bytes = (enc->bits_output + 7) / 8; in radeon_enc_nalu_prefix()
516 static void radeon_enc_nalu_sei(struct radeon_encoder *enc) in radeon_enc_nalu_sei() argument
521 table_info = rvcn_temporal_layer_pattern_tables[enc->enc_pic.layer_ctrl.num_temporal_layers - 1]; in radeon_enc_nalu_sei()
524 RADEON_ENC_BEGIN(enc->cmd.nalu); in radeon_enc_nalu_sei()
526 unsigned *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_enc_nalu_sei()
527 radeon_enc_reset(enc); in radeon_enc_nalu_sei()
528 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_nalu_sei()
530 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); in radeon_enc_nalu_sei()
531 radeon_enc_code_fixed_bits(enc, 0x6, 8); in radeon_enc_nalu_sei()
532 radeon_enc_byte_align(enc); in radeon_enc_nalu_sei()
534 radeon_enc_set_emulation_prevention(enc, true); in radeon_enc_nalu_sei()
537 unsigned position = enc->cs.current.cdw; in radeon_enc_nalu_sei()
538 unsigned shifter = enc->shifter; in radeon_enc_nalu_sei()
539 unsigned bits_in_shifter = enc->bits_in_shifter; in radeon_enc_nalu_sei()
540 unsigned num_zeros = enc->num_zeros; in radeon_enc_nalu_sei()
541 unsigned byte_index = enc->byte_index; in radeon_enc_nalu_sei()
542 unsigned bits_output = enc->bits_output; in radeon_enc_nalu_sei()
543 bool emulation_prevention = enc->emulation_prevention; in radeon_enc_nalu_sei()
546 radeon_enc_code_fixed_bits(enc, 24, 8); in radeon_enc_nalu_sei()
547 radeon_enc_code_fixed_bits(enc, 0, 8); in radeon_enc_nalu_sei()
549 unsigned svc_start_offset = enc->bits_size; in radeon_enc_nalu_sei()
551 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sei()
552 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sei()
553 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sei()
554 radeon_enc_code_ue(enc, number_of_layers - 1); in radeon_enc_nalu_sei()
559 radeon_enc_code_ue(enc, i); in radeon_enc_nalu_sei()
560 radeon_enc_code_fixed_bits(enc, 0x0, 6); in radeon_enc_nalu_sei()
561 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sei()
562 radeon_enc_code_fixed_bits(enc, 0x0, 3); in radeon_enc_nalu_sei()
563 radeon_enc_code_fixed_bits(enc, 0x0, 4); in radeon_enc_nalu_sei()
564 radeon_enc_code_fixed_bits(enc, pattern.temporal_id, 3); in radeon_enc_nalu_sei()
565 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sei()
566 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sei()
567 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sei()
568 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sei()
569 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sei()
570 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sei()
571 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sei()
572 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sei()
573 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sei()
574 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sei()
575 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sei()
576 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sei()
577 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_sei()
578 radeon_enc_code_ue(enc, 0); in radeon_enc_nalu_sei()
579 radeon_enc_code_ue(enc, 0); in radeon_enc_nalu_sei()
581 unsigned svc_size = ((enc->bits_size - svc_start_offset) + 7) / 8; in radeon_enc_nalu_sei()
582 unsigned aligned = (32 - enc->bits_in_shifter) % 8; in radeon_enc_nalu_sei()
584 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sei()
585 radeon_enc_byte_align(enc); in radeon_enc_nalu_sei()
587 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_sei()
588 radeon_enc_byte_align(enc); in radeon_enc_nalu_sei()
591 unsigned position2 = enc->cs.current.cdw; in radeon_enc_nalu_sei()
592 unsigned shifter2 = enc->shifter; in radeon_enc_nalu_sei()
593 unsigned bits_in_shifter2 = enc->bits_in_shifter; in radeon_enc_nalu_sei()
594 unsigned num_zeros2 = enc->num_zeros; in radeon_enc_nalu_sei()
595 unsigned byte_index2 = enc->byte_index; in radeon_enc_nalu_sei()
596 unsigned bits_output2 = enc->bits_output; in radeon_enc_nalu_sei()
597 bool emulation_prevention2 = enc->emulation_prevention; in radeon_enc_nalu_sei()
599 enc->cs.current.cdw = position; in radeon_enc_nalu_sei()
600 enc->shifter = shifter; in radeon_enc_nalu_sei()
601 enc->bits_in_shifter = bits_in_shifter; in radeon_enc_nalu_sei()
602 enc->num_zeros = num_zeros; in radeon_enc_nalu_sei()
603 enc->byte_index = byte_index; in radeon_enc_nalu_sei()
604 enc->bits_output = bits_output; in radeon_enc_nalu_sei()
605 enc->emulation_prevention = emulation_prevention; in radeon_enc_nalu_sei()
607 radeon_enc_output_one_byte(enc, 24); in radeon_enc_nalu_sei()
608 radeon_enc_output_one_byte(enc, svc_size); in radeon_enc_nalu_sei()
611 enc->cs.current.cdw = position2; in radeon_enc_nalu_sei()
612 enc->shifter = shifter2; in radeon_enc_nalu_sei()
613 enc->bits_in_shifter = bits_in_shifter2; in radeon_enc_nalu_sei()
614 enc->num_zeros = num_zeros2; in radeon_enc_nalu_sei()
615 enc->byte_index = byte_index2; in radeon_enc_nalu_sei()
616 enc->bits_output = bits_output2; in radeon_enc_nalu_sei()
617 enc->emulation_prevention = emulation_prevention2; in radeon_enc_nalu_sei()
619 radeon_enc_flush_headers(enc); in radeon_enc_nalu_sei()
621 *size_in_bytes = (enc->bits_output + 7) / 8; in radeon_enc_nalu_sei()
625 static void radeon_enc_nalu_pps(struct radeon_encoder *enc) in radeon_enc_nalu_pps() argument
627 RADEON_ENC_BEGIN(enc->cmd.nalu); in radeon_enc_nalu_pps()
629 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_enc_nalu_pps()
630 radeon_enc_reset(enc); in radeon_enc_nalu_pps()
631 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_nalu_pps()
632 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); in radeon_enc_nalu_pps()
633 radeon_enc_code_fixed_bits(enc, 0x68, 8); in radeon_enc_nalu_pps()
634 radeon_enc_byte_align(enc); in radeon_enc_nalu_pps()
635 radeon_enc_set_emulation_prevention(enc, true); in radeon_enc_nalu_pps()
636 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps()
637 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps()
638 radeon_enc_code_fixed_bits(enc, (enc->enc_pic.spec_misc.cabac_enable ? 0x1 : 0x0), 1); in radeon_enc_nalu_pps()
639 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps()
640 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps()
641 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps()
642 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps()
643 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps()
644 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_pps()
645 radeon_enc_code_se(enc, 0x0); in radeon_enc_nalu_pps()
646 radeon_enc_code_se(enc, 0x0); in radeon_enc_nalu_pps()
647 radeon_enc_code_se(enc, 0x0); in radeon_enc_nalu_pps()
648 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps()
649 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps()
650 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps()
652 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps()
654 radeon_enc_byte_align(enc); in radeon_enc_nalu_pps()
655 radeon_enc_flush_headers(enc); in radeon_enc_nalu_pps()
656 *size_in_bytes = (enc->bits_output + 7) / 8; in radeon_enc_nalu_pps()
660 static void radeon_enc_nalu_pps_hevc(struct radeon_encoder *enc) in radeon_enc_nalu_pps_hevc() argument
662 RADEON_ENC_BEGIN(enc->cmd.nalu); in radeon_enc_nalu_pps_hevc()
664 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_enc_nalu_pps_hevc()
665 radeon_enc_reset(enc); in radeon_enc_nalu_pps_hevc()
666 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_nalu_pps_hevc()
667 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); in radeon_enc_nalu_pps_hevc()
668 radeon_enc_code_fixed_bits(enc, 0x4401, 16); in radeon_enc_nalu_pps_hevc()
669 radeon_enc_byte_align(enc); in radeon_enc_nalu_pps_hevc()
670 radeon_enc_set_emulation_prevention(enc, true); in radeon_enc_nalu_pps_hevc()
671 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps_hevc()
672 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps_hevc()
673 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
674 radeon_enc_code_fixed_bits(enc, 0x0, 4); in radeon_enc_nalu_pps_hevc()
675 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
676 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
677 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps_hevc()
678 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps_hevc()
679 radeon_enc_code_se(enc, 0x0); in radeon_enc_nalu_pps_hevc()
680 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.constrained_intra_pred_flag, 1); in radeon_enc_nalu_pps_hevc()
681 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
682 if (enc->enc_pic.rc_session_init.rate_control_method == RENCODE_RATE_CONTROL_METHOD_NONE) in radeon_enc_nalu_pps_hevc()
683 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
685 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
686 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_pps_hevc()
688 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cb_qp_offset); in radeon_enc_nalu_pps_hevc()
689 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.cr_qp_offset); in radeon_enc_nalu_pps_hevc()
690 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
691 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_pps_hevc()
692 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
693 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
694 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
695 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, 1); in radeon_enc_nalu_pps_hevc()
696 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
697 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
698 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.deblocking_filter_disabled, 1); in radeon_enc_nalu_pps_hevc()
700 if (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled) { in radeon_enc_nalu_pps_hevc()
701 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.beta_offset_div2); in radeon_enc_nalu_pps_hevc()
702 radeon_enc_code_se(enc, enc->enc_pic.hevc_deblock.tc_offset_div2); in radeon_enc_nalu_pps_hevc()
705 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
706 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_pps_hevc()
707 radeon_enc_code_ue(enc, enc->enc_pic.log2_parallel_merge_level_minus2); in radeon_enc_nalu_pps_hevc()
708 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_pps_hevc()
710 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_pps_hevc()
712 radeon_enc_byte_align(enc); in radeon_enc_nalu_pps_hevc()
713 radeon_enc_flush_headers(enc); in radeon_enc_nalu_pps_hevc()
714 *size_in_bytes = (enc->bits_output + 7) / 8; in radeon_enc_nalu_pps_hevc()
718 static void radeon_enc_nalu_vps(struct radeon_encoder *enc) in radeon_enc_nalu_vps() argument
720 RADEON_ENC_BEGIN(enc->cmd.nalu); in radeon_enc_nalu_vps()
722 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_enc_nalu_vps()
725 radeon_enc_reset(enc); in radeon_enc_nalu_vps()
726 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_nalu_vps()
727 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); in radeon_enc_nalu_vps()
728 radeon_enc_code_fixed_bits(enc, 0x4001, 16); in radeon_enc_nalu_vps()
729 radeon_enc_byte_align(enc); in radeon_enc_nalu_vps()
730 radeon_enc_set_emulation_prevention(enc, true); in radeon_enc_nalu_vps()
732 radeon_enc_code_fixed_bits(enc, 0x0, 4); in radeon_enc_nalu_vps()
733 radeon_enc_code_fixed_bits(enc, 0x3, 2); in radeon_enc_nalu_vps()
734 radeon_enc_code_fixed_bits(enc, 0x0, 6); in radeon_enc_nalu_vps()
735 radeon_enc_code_fixed_bits(enc, enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1, 3); in radeon_enc_nalu_vps()
736 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_vps()
737 radeon_enc_code_fixed_bits(enc, 0xffff, 16); in radeon_enc_nalu_vps()
738 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_vps()
739 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_tier_flag, 1); in radeon_enc_nalu_vps()
740 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_profile_idc, 5); in radeon_enc_nalu_vps()
741 radeon_enc_code_fixed_bits(enc, 0x60000000, 32); in radeon_enc_nalu_vps()
742 radeon_enc_code_fixed_bits(enc, 0xb0000000, 32); in radeon_enc_nalu_vps()
743 radeon_enc_code_fixed_bits(enc, 0x0, 16); in radeon_enc_nalu_vps()
744 radeon_enc_code_fixed_bits(enc, enc->enc_pic.general_level_idc, 8); in radeon_enc_nalu_vps()
746 for (i = 0; i < (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i++) in radeon_enc_nalu_vps()
747 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_vps()
749 if ((enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1) > 0) { in radeon_enc_nalu_vps()
750 for (i = (enc->enc_pic.layer_ctrl.max_num_temporal_layers - 1); i < 8; i++) in radeon_enc_nalu_vps()
751 radeon_enc_code_fixed_bits(enc, 0x0, 2); in radeon_enc_nalu_vps()
754 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_vps()
755 radeon_enc_code_ue(enc, 0x1); in radeon_enc_nalu_vps()
756 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_vps()
757 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_vps()
759 radeon_enc_code_fixed_bits(enc, 0x0, 6); in radeon_enc_nalu_vps()
760 radeon_enc_code_ue(enc, 0x0); in radeon_enc_nalu_vps()
761 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_vps()
762 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_vps()
764 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_vps()
766 radeon_enc_byte_align(enc); in radeon_enc_nalu_vps()
767 radeon_enc_flush_headers(enc); in radeon_enc_nalu_vps()
768 *size_in_bytes = (enc->bits_output + 7) / 8; in radeon_enc_nalu_vps()
772 static void radeon_enc_nalu_aud_hevc(struct radeon_encoder *enc) in radeon_enc_nalu_aud_hevc() argument
774 RADEON_ENC_BEGIN(enc->cmd.nalu); in radeon_enc_nalu_aud_hevc()
776 uint32_t *size_in_bytes = &enc->cs.current.buf[enc->cs.current.cdw++]; in radeon_enc_nalu_aud_hevc()
777 radeon_enc_reset(enc); in radeon_enc_nalu_aud_hevc()
778 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_nalu_aud_hevc()
779 radeon_enc_code_fixed_bits(enc, 0x00000001, 32); in radeon_enc_nalu_aud_hevc()
780 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_nalu_aud_hevc()
781 radeon_enc_code_fixed_bits(enc, 35, 6); in radeon_enc_nalu_aud_hevc()
782 radeon_enc_code_fixed_bits(enc, 0x0, 6); in radeon_enc_nalu_aud_hevc()
783 radeon_enc_code_fixed_bits(enc, 0x1, 3); in radeon_enc_nalu_aud_hevc()
784 radeon_enc_byte_align(enc); in radeon_enc_nalu_aud_hevc()
785 radeon_enc_set_emulation_prevention(enc, true); in radeon_enc_nalu_aud_hevc()
786 switch (enc->enc_pic.picture_type) { in radeon_enc_nalu_aud_hevc()
789 radeon_enc_code_fixed_bits(enc, 0x00, 3); in radeon_enc_nalu_aud_hevc()
792 radeon_enc_code_fixed_bits(enc, 0x01, 3); in radeon_enc_nalu_aud_hevc()
795 radeon_enc_code_fixed_bits(enc, 0x02, 3); in radeon_enc_nalu_aud_hevc()
798 radeon_enc_code_fixed_bits(enc, 0x02, 3); in radeon_enc_nalu_aud_hevc()
801 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_nalu_aud_hevc()
803 radeon_enc_byte_align(enc); in radeon_enc_nalu_aud_hevc()
804 radeon_enc_flush_headers(enc); in radeon_enc_nalu_aud_hevc()
805 *size_in_bytes = (enc->bits_output + 7) / 8; in radeon_enc_nalu_aud_hevc()
809 static void radeon_enc_slice_header(struct radeon_encoder *enc) in radeon_enc_slice_header() argument
817 RADEON_ENC_BEGIN(enc->cmd.slice_header); in radeon_enc_slice_header()
818 radeon_enc_reset(enc); in radeon_enc_slice_header()
819 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_slice_header()
821 cdw_start = enc->cs.current.cdw; in radeon_enc_slice_header()
822 if (enc->enc_pic.is_idr) in radeon_enc_slice_header()
823 radeon_enc_code_fixed_bits(enc, 0x65, 8); in radeon_enc_slice_header()
824 else if (enc->enc_pic.not_referenced) in radeon_enc_slice_header()
825 radeon_enc_code_fixed_bits(enc, 0x01, 8); in radeon_enc_slice_header()
827 radeon_enc_code_fixed_bits(enc, 0x41, 8); in radeon_enc_slice_header()
829 radeon_enc_flush_headers(enc); in radeon_enc_slice_header()
831 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header()
832 bits_copied = enc->bits_output; in radeon_enc_slice_header()
838 switch (enc->enc_pic.picture_type) { in radeon_enc_slice_header()
841 radeon_enc_code_fixed_bits(enc, 0x08, 7); in radeon_enc_slice_header()
845 radeon_enc_code_fixed_bits(enc, 0x06, 5); in radeon_enc_slice_header()
848 radeon_enc_code_fixed_bits(enc, 0x07, 5); in radeon_enc_slice_header()
851 radeon_enc_code_fixed_bits(enc, 0x08, 7); in radeon_enc_slice_header()
854 radeon_enc_code_ue(enc, 0x0); in radeon_enc_slice_header()
855 radeon_enc_code_fixed_bits(enc, enc->enc_pic.frame_num % 32, 5); in radeon_enc_slice_header()
857 if (enc->enc_pic.h264_enc_params.input_picture_structure != in radeon_enc_slice_header()
859 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_slice_header()
860 radeon_enc_code_fixed_bits(enc, in radeon_enc_slice_header()
861 enc->enc_pic.h264_enc_params.input_picture_structure == in radeon_enc_slice_header()
868 if (enc->enc_pic.is_idr) in radeon_enc_slice_header()
869 radeon_enc_code_ue(enc, enc->enc_pic.is_even_frame); in radeon_enc_slice_header()
871 enc->enc_pic.is_even_frame = !enc->enc_pic.is_even_frame; in radeon_enc_slice_header()
873 if (enc->enc_pic.pic_order_cnt_type == 0) in radeon_enc_slice_header()
874 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt % 32, 5); in radeon_enc_slice_header()
876 if (enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_IDR) { in radeon_enc_slice_header()
877 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header()
879 if (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 > 1) { in radeon_enc_slice_header()
880 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_slice_header()
881 radeon_enc_code_ue(enc, 0x0); in radeon_enc_slice_header()
882 radeon_enc_code_ue(enc, (enc->enc_pic.frame_num - enc->enc_pic.ref_idx_l0 - 1)); in radeon_enc_slice_header()
883 radeon_enc_code_ue(enc, 0x3); in radeon_enc_slice_header()
885 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header()
888 if (enc->enc_pic.is_idr) { in radeon_enc_slice_header()
889 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header()
890 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header()
892 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header()
894 if ((enc->enc_pic.picture_type != PIPE_H2645_ENC_PICTURE_TYPE_IDR) && in radeon_enc_slice_header()
895 (enc->enc_pic.spec_misc.cabac_enable)) in radeon_enc_slice_header()
896 radeon_enc_code_ue(enc, enc->enc_pic.spec_misc.cabac_init_idc); in radeon_enc_slice_header()
898 radeon_enc_flush_headers(enc); in radeon_enc_slice_header()
900 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header()
901 bits_copied = enc->bits_output; in radeon_enc_slice_header()
907 radeon_enc_code_ue(enc, enc->enc_pic.h264_deblock.disable_deblocking_filter_idc ? 1 : 0); in radeon_enc_slice_header()
909 if (!enc->enc_pic.h264_deblock.disable_deblocking_filter_idc) { in radeon_enc_slice_header()
910 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.alpha_c0_offset_div2); in radeon_enc_slice_header()
911 radeon_enc_code_se(enc, enc->enc_pic.h264_deblock.beta_offset_div2); in radeon_enc_slice_header()
914 radeon_enc_flush_headers(enc); in radeon_enc_slice_header()
916 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header()
917 bits_copied = enc->bits_output; in radeon_enc_slice_header()
922 cdw_filled = enc->cs.current.cdw - cdw_start; in radeon_enc_slice_header()
934 static void radeon_enc_slice_header_hevc(struct radeon_encoder *enc) in radeon_enc_slice_header_hevc() argument
942 RADEON_ENC_BEGIN(enc->cmd.slice_header); in radeon_enc_slice_header_hevc()
943 radeon_enc_reset(enc); in radeon_enc_slice_header_hevc()
944 radeon_enc_set_emulation_prevention(enc, false); in radeon_enc_slice_header_hevc()
946 cdw_start = enc->cs.current.cdw; in radeon_enc_slice_header_hevc()
947 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header_hevc()
948 radeon_enc_code_fixed_bits(enc, enc->enc_pic.nal_unit_type, 6); in radeon_enc_slice_header_hevc()
949 radeon_enc_code_fixed_bits(enc, 0x0, 6); in radeon_enc_slice_header_hevc()
950 radeon_enc_code_fixed_bits(enc, 0x1, 3); in radeon_enc_slice_header_hevc()
952 radeon_enc_flush_headers(enc); in radeon_enc_slice_header_hevc()
954 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header_hevc()
955 bits_copied = enc->bits_output; in radeon_enc_slice_header_hevc()
961 if ((enc->enc_pic.nal_unit_type >= 16) && (enc->enc_pic.nal_unit_type <= 23)) in radeon_enc_slice_header_hevc()
962 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header_hevc()
964 radeon_enc_code_ue(enc, 0x0); in radeon_enc_slice_header_hevc()
966 radeon_enc_flush_headers(enc); in radeon_enc_slice_header_hevc()
968 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header_hevc()
969 bits_copied = enc->bits_output; in radeon_enc_slice_header_hevc()
978 switch (enc->enc_pic.picture_type) { in radeon_enc_slice_header_hevc()
981 radeon_enc_code_ue(enc, 0x2); in radeon_enc_slice_header_hevc()
985 radeon_enc_code_ue(enc, 0x1); in radeon_enc_slice_header_hevc()
988 radeon_enc_code_ue(enc, 0x0); in radeon_enc_slice_header_hevc()
991 radeon_enc_code_ue(enc, 0x1); in radeon_enc_slice_header_hevc()
994 if ((enc->enc_pic.nal_unit_type != 19) && (enc->enc_pic.nal_unit_type != 20)) { in radeon_enc_slice_header_hevc()
995 radeon_enc_code_fixed_bits(enc, enc->enc_pic.pic_order_cnt, enc->enc_pic.log2_max_poc); in radeon_enc_slice_header_hevc()
996 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) in radeon_enc_slice_header_hevc()
997 radeon_enc_code_fixed_bits(enc, 0x1, 1); in radeon_enc_slice_header_hevc()
999 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header_hevc()
1000 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header_hevc()
1001 radeon_enc_code_ue(enc, 0x0); in radeon_enc_slice_header_hevc()
1002 radeon_enc_code_ue(enc, 0x0); in radeon_enc_slice_header_hevc()
1006 if ((enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_P) || in radeon_enc_slice_header_hevc()
1007 (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_B)) { in radeon_enc_slice_header_hevc()
1008 radeon_enc_code_fixed_bits(enc, 0x0, 1); in radeon_enc_slice_header_hevc()
1009 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_spec_misc.cabac_init_flag, 1); in radeon_enc_slice_header_hevc()
1010 radeon_enc_code_ue(enc, 5 - enc->enc_pic.max_num_merge_cand); in radeon_enc_slice_header_hevc()
1013 radeon_enc_flush_headers(enc); in radeon_enc_slice_header_hevc()
1015 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header_hevc()
1016 bits_copied = enc->bits_output; in radeon_enc_slice_header_hevc()
1022 if ((enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled) && in radeon_enc_slice_header_hevc()
1023 (!enc->enc_pic.hevc_deblock.deblocking_filter_disabled)) { in radeon_enc_slice_header_hevc()
1024 radeon_enc_code_fixed_bits(enc, enc->enc_pic.hevc_deblock.loop_filter_across_slices_enabled, in radeon_enc_slice_header_hevc()
1027 radeon_enc_flush_headers(enc); in radeon_enc_slice_header_hevc()
1029 num_bits[inst_index] = enc->bits_output - bits_copied; in radeon_enc_slice_header_hevc()
1030 bits_copied = enc->bits_output; in radeon_enc_slice_header_hevc()
1036 cdw_filled = enc->cs.current.cdw - cdw_start; in radeon_enc_slice_header_hevc()
1048 static void radeon_enc_ctx(struct radeon_encoder *enc) in radeon_enc_ctx() argument
1050 enc->enc_pic.ctx_buf.swizzle_mode = 0; in radeon_enc_ctx()
1051 enc->enc_pic.ctx_buf.rec_luma_pitch = align(enc->base.width, enc->alignment); in radeon_enc_ctx()
1052 enc->enc_pic.ctx_buf.rec_chroma_pitch = align(enc->base.width, enc->alignment); in radeon_enc_ctx()
1053 enc->enc_pic.ctx_buf.num_reconstructed_pictures = 2; in radeon_enc_ctx()
1055 RADEON_ENC_BEGIN(enc->cmd.ctx); in radeon_enc_ctx()
1056 RADEON_ENC_READWRITE(enc->cpb.res->buf, enc->cpb.res->domains, 0); in radeon_enc_ctx()
1057 RADEON_ENC_CS(enc->enc_pic.ctx_buf.swizzle_mode); in radeon_enc_ctx()
1058 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_luma_pitch); in radeon_enc_ctx()
1059 RADEON_ENC_CS(enc->enc_pic.ctx_buf.rec_chroma_pitch); in radeon_enc_ctx()
1060 RADEON_ENC_CS(enc->enc_pic.ctx_buf.num_reconstructed_pictures); in radeon_enc_ctx()
1064 RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16)); in radeon_enc_ctx()
1066 RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 3 / 2); in radeon_enc_ctx()
1068 RADEON_ENC_CS(align(enc->base.width, enc->alignment) * align(enc->base.height, 16) * 5 / 2); in radeon_enc_ctx()
1076 static void radeon_enc_bitstream(struct radeon_encoder *enc) in radeon_enc_bitstream() argument
1078 enc->enc_pic.bit_buf.mode = RENCODE_REC_SWIZZLE_MODE_LINEAR; in radeon_enc_bitstream()
1079 enc->enc_pic.bit_buf.video_bitstream_buffer_size = enc->bs_size; in radeon_enc_bitstream()
1080 enc->enc_pic.bit_buf.video_bitstream_data_offset = 0; in radeon_enc_bitstream()
1082 RADEON_ENC_BEGIN(enc->cmd.bitstream); in radeon_enc_bitstream()
1083 RADEON_ENC_CS(enc->enc_pic.bit_buf.mode); in radeon_enc_bitstream()
1084 RADEON_ENC_WRITE(enc->bs_handle, RADEON_DOMAIN_GTT, 0); in radeon_enc_bitstream()
1085 RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_buffer_size); in radeon_enc_bitstream()
1086 RADEON_ENC_CS(enc->enc_pic.bit_buf.video_bitstream_data_offset); in radeon_enc_bitstream()
1090 static void radeon_enc_feedback(struct radeon_encoder *enc) in radeon_enc_feedback() argument
1092 enc->enc_pic.fb_buf.mode = RENCODE_FEEDBACK_BUFFER_MODE_LINEAR; in radeon_enc_feedback()
1093 enc->enc_pic.fb_buf.feedback_buffer_size = 16; in radeon_enc_feedback()
1094 enc->enc_pic.fb_buf.feedback_data_size = 40; in radeon_enc_feedback()
1096 RADEON_ENC_BEGIN(enc->cmd.feedback); in radeon_enc_feedback()
1097 RADEON_ENC_CS(enc->enc_pic.fb_buf.mode); in radeon_enc_feedback()
1098 RADEON_ENC_WRITE(enc->fb->res->buf, enc->fb->res->domains, 0x0); in radeon_enc_feedback()
1099 RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_buffer_size); in radeon_enc_feedback()
1100 RADEON_ENC_CS(enc->enc_pic.fb_buf.feedback_data_size); in radeon_enc_feedback()
1104 static void radeon_enc_intra_refresh(struct radeon_encoder *enc) in radeon_enc_intra_refresh() argument
1106 enc->enc_pic.intra_ref.intra_refresh_mode = RENCODE_INTRA_REFRESH_MODE_NONE; in radeon_enc_intra_refresh()
1107 enc->enc_pic.intra_ref.offset = 0; in radeon_enc_intra_refresh()
1108 enc->enc_pic.intra_ref.region_size = 0; in radeon_enc_intra_refresh()
1110 RADEON_ENC_BEGIN(enc->cmd.intra_refresh); in radeon_enc_intra_refresh()
1111 RADEON_ENC_CS(enc->enc_pic.intra_ref.intra_refresh_mode); in radeon_enc_intra_refresh()
1112 RADEON_ENC_CS(enc->enc_pic.intra_ref.offset); in radeon_enc_intra_refresh()
1113 RADEON_ENC_CS(enc->enc_pic.intra_ref.region_size); in radeon_enc_intra_refresh()
1117 static void radeon_enc_rc_per_pic(struct radeon_encoder *enc) in radeon_enc_rc_per_pic() argument
1119 RADEON_ENC_BEGIN(enc->cmd.rc_per_pic); in radeon_enc_rc_per_pic()
1120 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.qp); in radeon_enc_rc_per_pic()
1121 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.min_qp_app); in radeon_enc_rc_per_pic()
1122 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_qp_app); in radeon_enc_rc_per_pic()
1123 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.max_au_size); in radeon_enc_rc_per_pic()
1124 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enabled_filler_data); in radeon_enc_rc_per_pic()
1125 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.skip_frame_enable); in radeon_enc_rc_per_pic()
1126 RADEON_ENC_CS(enc->enc_pic.rc_per_pic.enforce_hrd); in radeon_enc_rc_per_pic()
1130 static void radeon_enc_encode_params(struct radeon_encoder *enc) in radeon_enc_encode_params() argument
1132 switch (enc->enc_pic.picture_type) { in radeon_enc_encode_params()
1135 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I; in radeon_enc_encode_params()
1138 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P; in radeon_enc_encode_params()
1141 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP; in radeon_enc_encode_params()
1144 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B; in radeon_enc_encode_params()
1147 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I; in radeon_enc_encode_params()
1150 if (enc->luma->meta_offset) { in radeon_enc_encode_params()
1155 enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size; in radeon_enc_encode_params()
1156 enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch; in radeon_enc_encode_params()
1157 enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch; in radeon_enc_encode_params()
1158 enc->enc_pic.enc_params.input_pic_swizzle_mode = enc->luma->u.gfx9.swizzle_mode; in radeon_enc_encode_params()
1160 if (enc->enc_pic.picture_type == PIPE_H2645_ENC_PICTURE_TYPE_IDR) in radeon_enc_encode_params()
1161 enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF; in radeon_enc_encode_params()
1163 enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2; in radeon_enc_encode_params()
1165 enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2; in radeon_enc_encode_params()
1167 RADEON_ENC_BEGIN(enc->cmd.enc_params); in radeon_enc_encode_params()
1168 RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type); in radeon_enc_encode_params()
1169 RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size); in radeon_enc_encode_params()
1170 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset); in radeon_enc_encode_params()
1171 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset); in radeon_enc_encode_params()
1172 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch); in radeon_enc_encode_params()
1173 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch); in radeon_enc_encode_params()
1174 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode); in radeon_enc_encode_params()
1175 RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index); in radeon_enc_encode_params()
1176 RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index); in radeon_enc_encode_params()
1180 static void radeon_enc_encode_params_hevc(struct radeon_encoder *enc) in radeon_enc_encode_params_hevc() argument
1182 switch (enc->enc_pic.picture_type) { in radeon_enc_encode_params_hevc()
1185 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I; in radeon_enc_encode_params_hevc()
1188 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P; in radeon_enc_encode_params_hevc()
1191 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_P_SKIP; in radeon_enc_encode_params_hevc()
1194 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_B; in radeon_enc_encode_params_hevc()
1197 enc->enc_pic.enc_params.pic_type = RENCODE_PICTURE_TYPE_I; in radeon_enc_encode_params_hevc()
1200 if (enc->luma->meta_offset) { in radeon_enc_encode_params_hevc()
1205 enc->enc_pic.enc_params.allowed_max_bitstream_size = enc->bs_size; in radeon_enc_encode_params_hevc()
1206 enc->enc_pic.enc_params.input_pic_luma_pitch = enc->luma->u.gfx9.surf_pitch; in radeon_enc_encode_params_hevc()
1207 enc->enc_pic.enc_params.input_pic_chroma_pitch = enc->chroma->u.gfx9.surf_pitch; in radeon_enc_encode_params_hevc()
1208 enc->enc_pic.enc_params.input_pic_swizzle_mode = enc->luma->u.gfx9.swizzle_mode; in radeon_enc_encode_params_hevc()
1210 if (enc->enc_pic.enc_params.pic_type == RENCODE_PICTURE_TYPE_I) in radeon_enc_encode_params_hevc()
1211 enc->enc_pic.enc_params.reference_picture_index = 0xFFFFFFFF; in radeon_enc_encode_params_hevc()
1213 enc->enc_pic.enc_params.reference_picture_index = (enc->enc_pic.frame_num - 1) % 2; in radeon_enc_encode_params_hevc()
1215 enc->enc_pic.enc_params.reconstructed_picture_index = enc->enc_pic.frame_num % 2; in radeon_enc_encode_params_hevc()
1217 RADEON_ENC_BEGIN(enc->cmd.enc_params); in radeon_enc_encode_params_hevc()
1218 RADEON_ENC_CS(enc->enc_pic.enc_params.pic_type); in radeon_enc_encode_params_hevc()
1219 RADEON_ENC_CS(enc->enc_pic.enc_params.allowed_max_bitstream_size); in radeon_enc_encode_params_hevc()
1220 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->luma->u.gfx9.surf_offset); in radeon_enc_encode_params_hevc()
1221 RADEON_ENC_READ(enc->handle, RADEON_DOMAIN_VRAM, enc->chroma->u.gfx9.surf_offset); in radeon_enc_encode_params_hevc()
1222 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_luma_pitch); in radeon_enc_encode_params_hevc()
1223 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_chroma_pitch); in radeon_enc_encode_params_hevc()
1224 RADEON_ENC_CS(enc->enc_pic.enc_params.input_pic_swizzle_mode); in radeon_enc_encode_params_hevc()
1225 RADEON_ENC_CS(enc->enc_pic.enc_params.reference_picture_index); in radeon_enc_encode_params_hevc()
1226 RADEON_ENC_CS(enc->enc_pic.enc_params.reconstructed_picture_index); in radeon_enc_encode_params_hevc()
1230 static void radeon_enc_encode_params_h264(struct radeon_encoder *enc) in radeon_enc_encode_params_h264() argument
1232 enc->enc_pic.h264_enc_params.input_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME; in radeon_enc_encode_params_h264()
1233 enc->enc_pic.h264_enc_params.interlaced_mode = RENCODE_H264_INTERLACING_MODE_PROGRESSIVE; in radeon_enc_encode_params_h264()
1234 enc->enc_pic.h264_enc_params.reference_picture_structure = RENCODE_H264_PICTURE_STRUCTURE_FRAME; in radeon_enc_encode_params_h264()
1235 enc->enc_pic.h264_enc_params.reference_picture1_index = 0xFFFFFFFF; in radeon_enc_encode_params_h264()
1237 RADEON_ENC_BEGIN(enc->cmd.enc_params_h264); in radeon_enc_encode_params_h264()
1238 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.input_picture_structure); in radeon_enc_encode_params_h264()
1239 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.interlaced_mode); in radeon_enc_encode_params_h264()
1240 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture_structure); in radeon_enc_encode_params_h264()
1241 RADEON_ENC_CS(enc->enc_pic.h264_enc_params.reference_picture1_index); in radeon_enc_encode_params_h264()
1245 static void radeon_enc_op_init(struct radeon_encoder *enc) in radeon_enc_op_init() argument
1251 static void radeon_enc_op_close(struct radeon_encoder *enc) in radeon_enc_op_close() argument
1257 static void radeon_enc_op_enc(struct radeon_encoder *enc) in radeon_enc_op_enc() argument
1263 static void radeon_enc_op_init_rc(struct radeon_encoder *enc) in radeon_enc_op_init_rc() argument
1269 static void radeon_enc_op_init_rc_vbv(struct radeon_encoder *enc) in radeon_enc_op_init_rc_vbv() argument
1275 static void radeon_enc_op_speed(struct radeon_encoder *enc) in radeon_enc_op_speed() argument
1281 static void begin(struct radeon_encoder *enc) in begin() argument
1285 enc->session_info(enc); in begin()
1286 enc->total_task_size = 0; in begin()
1287 enc->task_info(enc, enc->need_feedback); in begin()
1288 enc->op_init(enc); in begin()
1290 enc->session_init(enc); in begin()
1291 enc->slice_control(enc); in begin()
1292 enc->spec_misc(enc); in begin()
1293 enc->deblocking_filter(enc); in begin()
1295 enc->layer_control(enc); in begin()
1296 enc->rc_session_init(enc); in begin()
1297 enc->quality_params(enc); in begin()
1301 enc->enc_pic.temporal_id = i; in begin()
1302 enc->layer_select(enc); in begin()
1303 enc->rc_layer_init(enc); in begin()
1304 enc->layer_select(enc); in begin()
1305 enc->rc_per_pic(enc); in begin()
1306 } while (++i < enc->enc_pic.num_temporal_layers); in begin()
1308 enc->op_init_rc(enc); in begin()
1309 enc->op_init_rc_vbv(enc); in begin()
1310 *enc->p_task_size = (enc->total_task_size); in begin()
1313 static void radeon_enc_headers_h264(struct radeon_encoder *enc) in radeon_enc_headers_h264() argument
1315 if (enc->enc_pic.layer_ctrl.num_temporal_layers > 1) in radeon_enc_headers_h264()
1316 enc->nalu_prefix(enc); in radeon_enc_headers_h264()
1317 if (enc->enc_pic.is_idr) { in radeon_enc_headers_h264()
1318 if (enc->enc_pic.layer_ctrl.num_temporal_layers > 1) in radeon_enc_headers_h264()
1319 enc->nalu_sei(enc); in radeon_enc_headers_h264()
1320 enc->nalu_sps(enc); in radeon_enc_headers_h264()
1321 enc->nalu_pps(enc); in radeon_enc_headers_h264()
1323 enc->slice_header(enc); in radeon_enc_headers_h264()
1324 enc->encode_params(enc); in radeon_enc_headers_h264()
1325 enc->encode_params_codec_spec(enc); in radeon_enc_headers_h264()
1328 static void radeon_enc_headers_hevc(struct radeon_encoder *enc) in radeon_enc_headers_hevc() argument
1330 enc->nalu_aud(enc); in radeon_enc_headers_hevc()
1331 if (enc->enc_pic.is_idr) { in radeon_enc_headers_hevc()
1332 enc->nalu_vps(enc); in radeon_enc_headers_hevc()
1333 enc->nalu_pps(enc); in radeon_enc_headers_hevc()
1334 enc->nalu_sps(enc); in radeon_enc_headers_hevc()
1336 enc->slice_header(enc); in radeon_enc_headers_hevc()
1337 enc->encode_params(enc); in radeon_enc_headers_hevc()
1340 static void encode(struct radeon_encoder *enc) in encode() argument
1342 enc->session_info(enc); in encode()
1343 enc->total_task_size = 0; in encode()
1344 enc->task_info(enc, enc->need_feedback); in encode()
1346 enc->encode_headers(enc); in encode()
1347 enc->ctx(enc); in encode()
1348 enc->bitstream(enc); in encode()
1349 enc->feedback(enc); in encode()
1350 enc->intra_refresh(enc); in encode()
1352 enc->op_preset(enc); in encode()
1353 enc->op_enc(enc); in encode()
1354 *enc->p_task_size = (enc->total_task_size); in encode()
1357 static void destroy(struct radeon_encoder *enc) in destroy() argument
1359 enc->session_info(enc); in destroy()
1360 enc->total_task_size = 0; in destroy()
1361 enc->task_info(enc, enc->need_feedback); in destroy()
1362 enc->op_close(enc); in destroy()
1363 *enc->p_task_size = (enc->total_task_size); in destroy()
1366 void radeon_enc_1_2_init(struct radeon_encoder *enc) in radeon_enc_1_2_init() argument
1368 enc->begin = begin; in radeon_enc_1_2_init()
1369 enc->encode = encode; in radeon_enc_1_2_init()
1370 enc->destroy = destroy; in radeon_enc_1_2_init()
1371 enc->session_info = radeon_enc_session_info; in radeon_enc_1_2_init()
1372 enc->task_info = radeon_enc_task_info; in radeon_enc_1_2_init()
1373 enc->layer_control = radeon_enc_layer_control; in radeon_enc_1_2_init()
1374 enc->layer_select = radeon_enc_layer_select; in radeon_enc_1_2_init()
1375 enc->rc_session_init = radeon_enc_rc_session_init; in radeon_enc_1_2_init()
1376 enc->rc_layer_init = radeon_enc_rc_layer_init; in radeon_enc_1_2_init()
1377 enc->quality_params = radeon_enc_quality_params; in radeon_enc_1_2_init()
1378 enc->ctx = radeon_enc_ctx; in radeon_enc_1_2_init()
1379 enc->bitstream = radeon_enc_bitstream; in radeon_enc_1_2_init()
1380 enc->feedback = radeon_enc_feedback; in radeon_enc_1_2_init()
1381 enc->intra_refresh = radeon_enc_intra_refresh; in radeon_enc_1_2_init()
1382 enc->rc_per_pic = radeon_enc_rc_per_pic; in radeon_enc_1_2_init()
1383 enc->encode_params = radeon_enc_encode_params; in radeon_enc_1_2_init()
1384 enc->op_init = radeon_enc_op_init; in radeon_enc_1_2_init()
1385 enc->op_close = radeon_enc_op_close; in radeon_enc_1_2_init()
1386 enc->op_enc = radeon_enc_op_enc; in radeon_enc_1_2_init()
1387 enc->op_init_rc = radeon_enc_op_init_rc; in radeon_enc_1_2_init()
1388 enc->op_init_rc_vbv = radeon_enc_op_init_rc_vbv; in radeon_enc_1_2_init()
1389 enc->op_preset = radeon_enc_op_speed; in radeon_enc_1_2_init()
1391 if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_MPEG4_AVC) { in radeon_enc_1_2_init()
1392 enc->session_init = radeon_enc_session_init; in radeon_enc_1_2_init()
1393 enc->slice_control = radeon_enc_slice_control; in radeon_enc_1_2_init()
1394 enc->spec_misc = radeon_enc_spec_misc; in radeon_enc_1_2_init()
1395 enc->deblocking_filter = radeon_enc_deblocking_filter_h264; in radeon_enc_1_2_init()
1396 enc->nalu_sps = radeon_enc_nalu_sps; in radeon_enc_1_2_init()
1397 enc->nalu_pps = radeon_enc_nalu_pps; in radeon_enc_1_2_init()
1398 enc->slice_header = radeon_enc_slice_header; in radeon_enc_1_2_init()
1399 enc->encode_params = radeon_enc_encode_params; in radeon_enc_1_2_init()
1400 enc->encode_params_codec_spec = radeon_enc_encode_params_h264; in radeon_enc_1_2_init()
1401 enc->encode_headers = radeon_enc_headers_h264; in radeon_enc_1_2_init()
1402 enc->nalu_prefix = radeon_enc_nalu_prefix; in radeon_enc_1_2_init()
1403 enc->nalu_sei = radeon_enc_nalu_sei; in radeon_enc_1_2_init()
1404 } else if (u_reduce_video_profile(enc->base.profile) == PIPE_VIDEO_FORMAT_HEVC) { in radeon_enc_1_2_init()
1405 enc->session_init = radeon_enc_session_init_hevc; in radeon_enc_1_2_init()
1406 enc->slice_control = radeon_enc_slice_control_hevc; in radeon_enc_1_2_init()
1407 enc->spec_misc = radeon_enc_spec_misc_hevc; in radeon_enc_1_2_init()
1408 enc->deblocking_filter = radeon_enc_deblocking_filter_hevc; in radeon_enc_1_2_init()
1409 enc->nalu_sps = radeon_enc_nalu_sps_hevc; in radeon_enc_1_2_init()
1410 enc->nalu_pps = radeon_enc_nalu_pps_hevc; in radeon_enc_1_2_init()
1411 enc->nalu_vps = radeon_enc_nalu_vps; in radeon_enc_1_2_init()
1412 enc->nalu_aud = radeon_enc_nalu_aud_hevc; in radeon_enc_1_2_init()
1413 enc->slice_header = radeon_enc_slice_header_hevc; in radeon_enc_1_2_init()
1414 enc->encode_params = radeon_enc_encode_params_hevc; in radeon_enc_1_2_init()
1415 enc->encode_headers = radeon_enc_headers_hevc; in radeon_enc_1_2_init()
1418 enc->cmd.session_info = RENCODE_IB_PARAM_SESSION_INFO; in radeon_enc_1_2_init()
1419 enc->cmd.task_info = RENCODE_IB_PARAM_TASK_INFO; in radeon_enc_1_2_init()
1420 enc->cmd.session_init = RENCODE_IB_PARAM_SESSION_INIT; in radeon_enc_1_2_init()
1421 enc->cmd.layer_control = RENCODE_IB_PARAM_LAYER_CONTROL; in radeon_enc_1_2_init()
1422 enc->cmd.layer_select = RENCODE_IB_PARAM_LAYER_SELECT; in radeon_enc_1_2_init()
1423 enc->cmd.rc_session_init = RENCODE_IB_PARAM_RATE_CONTROL_SESSION_INIT; in radeon_enc_1_2_init()
1424 enc->cmd.rc_layer_init = RENCODE_IB_PARAM_RATE_CONTROL_LAYER_INIT; in radeon_enc_1_2_init()
1425 enc->cmd.rc_per_pic = RENCODE_IB_PARAM_RATE_CONTROL_PER_PICTURE; in radeon_enc_1_2_init()
1426 enc->cmd.quality_params = RENCODE_IB_PARAM_QUALITY_PARAMS; in radeon_enc_1_2_init()
1427 enc->cmd.nalu = RENCODE_IB_PARAM_DIRECT_OUTPUT_NALU; in radeon_enc_1_2_init()
1428 enc->cmd.slice_header = RENCODE_IB_PARAM_SLICE_HEADER; in radeon_enc_1_2_init()
1429 enc->cmd.enc_params = RENCODE_IB_PARAM_ENCODE_PARAMS; in radeon_enc_1_2_init()
1430 enc->cmd.intra_refresh = RENCODE_IB_PARAM_INTRA_REFRESH; in radeon_enc_1_2_init()
1431 enc->cmd.ctx = RENCODE_IB_PARAM_ENCODE_CONTEXT_BUFFER; in radeon_enc_1_2_init()
1432 enc->cmd.bitstream = RENCODE_IB_PARAM_VIDEO_BITSTREAM_BUFFER; in radeon_enc_1_2_init()
1433 enc->cmd.feedback = RENCODE_IB_PARAM_FEEDBACK_BUFFER; in radeon_enc_1_2_init()
1434 enc->cmd.slice_control_hevc = RENCODE_HEVC_IB_PARAM_SLICE_CONTROL; in radeon_enc_1_2_init()
1435 enc->cmd.spec_misc_hevc = RENCODE_HEVC_IB_PARAM_SPEC_MISC; in radeon_enc_1_2_init()
1436 enc->cmd.deblocking_filter_hevc = RENCODE_HEVC_IB_PARAM_DEBLOCKING_FILTER; in radeon_enc_1_2_init()
1437 enc->cmd.slice_control_h264 = RENCODE_H264_IB_PARAM_SLICE_CONTROL; in radeon_enc_1_2_init()
1438 enc->cmd.spec_misc_h264 = RENCODE_H264_IB_PARAM_SPEC_MISC; in radeon_enc_1_2_init()
1439 enc->cmd.enc_params_h264 = RENCODE_H264_IB_PARAM_ENCODE_PARAMS; in radeon_enc_1_2_init()
1440 enc->cmd.deblocking_filter_h264 = RENCODE_H264_IB_PARAM_DEBLOCKING_FILTER; in radeon_enc_1_2_init()
1442 enc->enc_pic.session_info.interface_version = in radeon_enc_1_2_init()