335    OUT_PKT4(ring, REG_A5XX_TPL1_TP_BORDER_COLOR_BASE_ADDR_LO, 2);  in emit_border_color()
501          OUT_PKT4(ring, REG_A5XX_VFD_FETCH(j), 4);  in fd5_emit_vertex_bufs()
506          OUT_PKT4(ring, REG_A5XX_VFD_DECODE(j), 2);  in fd5_emit_vertex_bufs()
518          OUT_PKT4(ring, REG_A5XX_VFD_DEST_CNTL(j), 1);  in fd5_emit_vertex_bufs()
527    OUT_PKT4(ring, REG_A5XX_VFD_CONTROL_0, 1);  in fd5_emit_vertex_bufs()
550       OUT_PKT4(ring, REG_A5XX_RB_RENDER_COMPONENTS, 1);  in fd5_emit_state()
568       OUT_PKT4(ring, REG_A5XX_RB_ALPHA_CONTROL, 1);  in fd5_emit_state()
571       OUT_PKT4(ring, REG_A5XX_RB_STENCIL_CONTROL, 1);  in fd5_emit_state()
588          OUT_PKT4(ring, REG_A5XX_GRAS_LRZ_CNTL, 1);  in fd5_emit_state()
597       OUT_PKT4(ring, REG_A5XX_RB_STENCILREFMASK, 2);  in fd5_emit_state()
609       OUT_PKT4(ring, REG_A5XX_RB_DEPTH_CNTL, 1);  in fd5_emit_state()
612       OUT_PKT4(ring, REG_A5XX_RB_DEPTH_PLANE_CNTL, 1);  in fd5_emit_state()
617       OUT_PKT4(ring, REG_A5XX_GRAS_SU_DEPTH_PLANE_CNTL, 1);  in fd5_emit_state()
627       OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_TL_0, 2);  in fd5_emit_state()
633       OUT_PKT4(ring, REG_A5XX_GRAS_SC_VIEWPORT_SCISSOR_TL_0, 2);  in fd5_emit_state()
652       OUT_PKT4(ring, REG_A5XX_GRAS_CL_VPORT_XOFFSET_0, 6);  in fd5_emit_state()
668       OUT_PKT4(ring, REG_A5XX_GRAS_SU_CNTL, 1);  in fd5_emit_state()
673       OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);  in fd5_emit_state()
677       OUT_PKT4(ring, REG_A5XX_GRAS_SU_POLY_OFFSET_SCALE, 3);  in fd5_emit_state()
682       OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);  in fd5_emit_state()
685       OUT_PKT4(ring, REG_A5XX_GRAS_CL_CNTL, 1);  in fd5_emit_state()
702       OUT_PKT4(ring, REG_A5XX_PC_PRIMITIVE_CNTL, 1);  in fd5_emit_state()
719       OUT_PKT4(ring, REG_A5XX_RB_FS_OUTPUT_CNTL, 1);  in fd5_emit_state()
724       OUT_PKT4(ring, REG_A5XX_SP_FS_OUTPUT_CNTL, 1);  in fd5_emit_state()
745          OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(i), 3);  in fd5_emit_state()
759             OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(i), 1);  in fd5_emit_state()
771          OUT_PKT4(ring, REG_A5XX_VPC_SO_FLUSH_BASE_LO(i), 2);  in fd5_emit_state()
814          OUT_PKT4(ring, REG_A5XX_RB_MRT_CONTROL(i), 1);  in fd5_emit_state()
817          OUT_PKT4(ring, REG_A5XX_RB_MRT_BLEND_CONTROL(i), 1);  in fd5_emit_state()
821       OUT_PKT4(ring, REG_A5XX_SP_BLEND_CNTL, 1);  in fd5_emit_state()
828       OUT_PKT4(ring, REG_A5XX_RB_BLEND_CNTL, 1);  in fd5_emit_state()
836       OUT_PKT4(ring, REG_A5XX_RB_BLEND_RED, 8);  in fd5_emit_state()
858       OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);  in fd5_emit_state()
867    OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);  in fd5_emit_state()
872    OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);  in fd5_emit_state()
902       OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 1);  in fd5_emit_cs_state()
905       OUT_PKT4(ring, REG_A5XX_TPL1_HS_TEX_COUNT, 1);  in fd5_emit_cs_state()
908       OUT_PKT4(ring, REG_A5XX_TPL1_DS_TEX_COUNT, 1);  in fd5_emit_cs_state()
911       OUT_PKT4(ring, REG_A5XX_TPL1_GS_TEX_COUNT, 1);  in fd5_emit_cs_state()
914       OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 1);  in fd5_emit_cs_state()
918    OUT_PKT4(ring, REG_A5XX_TPL1_CS_TEX_COUNT, 1);  in fd5_emit_cs_state()
942    OUT_PKT4(ring, REG_A5XX_HLSQ_UPDATE_CNTL, 1);  in fd5_emit_restore()
955    OUT_PKT4(ring, REG_A5XX_PC_RESTART_INDEX, 1);  in fd5_emit_restore()
958    OUT_PKT4(ring, REG_A5XX_PC_RASTER_CNTL, 1);  in fd5_emit_restore()
961    OUT_PKT4(ring, REG_A5XX_GRAS_SU_POINT_MINMAX, 2);  in fd5_emit_restore()
966    OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);  in fd5_emit_restore()
969    OUT_PKT4(ring, REG_A5XX_GRAS_SC_SCREEN_SCISSOR_CNTL, 1);  in fd5_emit_restore()
972    OUT_PKT4(ring, REG_A5XX_SP_VS_CONFIG_MAX_CONST, 1);  in fd5_emit_restore()
975    OUT_PKT4(ring, REG_A5XX_SP_FS_CONFIG_MAX_CONST, 1);  in fd5_emit_restore()
978    OUT_PKT4(ring, REG_A5XX_UNKNOWN_E292, 2);  in fd5_emit_restore()
982    OUT_PKT4(ring, REG_A5XX_RB_MODE_CNTL, 1);  in fd5_emit_restore()
985    OUT_PKT4(ring, REG_A5XX_RB_DBG_ECO_CNTL, 1);  in fd5_emit_restore()
988    OUT_PKT4(ring, REG_A5XX_VFD_MODE_CNTL, 1);  in fd5_emit_restore()
991    OUT_PKT4(ring, REG_A5XX_PC_MODE_CNTL, 1);  in fd5_emit_restore()
994    OUT_PKT4(ring, REG_A5XX_SP_MODE_CNTL, 1);  in fd5_emit_restore()
998       OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);  in fd5_emit_restore()
1001       OUT_PKT4(ring, REG_A5XX_HLSQ_DBG_ECO_CNTL, 1);  in fd5_emit_restore()
1004       OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1);  in fd5_emit_restore()
1007       OUT_PKT4(ring, REG_A5XX_SP_DBG_ECO_CNTL, 1);  in fd5_emit_restore()
1011    OUT_PKT4(ring, REG_A5XX_TPL1_MODE_CNTL, 1);  in fd5_emit_restore()
1014    OUT_PKT4(ring, REG_A5XX_HLSQ_TIMEOUT_THRESHOLD_0, 2);  in fd5_emit_restore()
1018    OUT_PKT4(ring, REG_A5XX_VPC_DBG_ECO_CNTL, 1);  in fd5_emit_restore()
1021    OUT_PKT4(ring, REG_A5XX_HLSQ_MODE_CNTL, 1);  in fd5_emit_restore()
1024    OUT_PKT4(ring, REG_A5XX_VPC_MODE_CNTL, 1);  in fd5_emit_restore()
1035    OUT_PKT4(ring, REG_A5XX_GRAS_SU_CONSERVATIVE_RAS_CNTL, 1);  in fd5_emit_restore()
1038    OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);  in fd5_emit_restore()
1041    OUT_PKT4(ring, REG_A5XX_GRAS_SC_BIN_CNTL, 1);  in fd5_emit_restore()
1044    OUT_PKT4(ring, REG_A5XX_VPC_FS_PRIMITIVEID_CNTL, 1);  in fd5_emit_restore()
1047    OUT_PKT4(ring, REG_A5XX_VPC_SO_OVERRIDE, 1);  in fd5_emit_restore()
1050    OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(0), 3);  in fd5_emit_restore()
1055    OUT_PKT4(ring, REG_A5XX_VPC_SO_FLUSH_BASE_LO(0), 2);  in fd5_emit_restore()
1059    OUT_PKT4(ring, REG_A5XX_PC_GS_PARAM, 1);  in fd5_emit_restore()
1062    OUT_PKT4(ring, REG_A5XX_PC_HS_PARAM, 1);  in fd5_emit_restore()
1065    OUT_PKT4(ring, REG_A5XX_TPL1_TP_FS_ROTATION_CNTL, 1);  in fd5_emit_restore()
1068    OUT_PKT4(ring, REG_A5XX_UNKNOWN_E004, 1);  in fd5_emit_restore()
1071    OUT_PKT4(ring, REG_A5XX_GRAS_SU_LAYERED, 1);  in fd5_emit_restore()
1074    OUT_PKT4(ring, REG_A5XX_VPC_SO_BUF_CNTL, 1);  in fd5_emit_restore()
1077    OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(0), 1);  in fd5_emit_restore()
1080    OUT_PKT4(ring, REG_A5XX_PC_GS_LAYERED, 1);  in fd5_emit_restore()
1083    OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5AB, 1);  in fd5_emit_restore()
1086    OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5C2, 1);  in fd5_emit_restore()
1089    OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_BASE_LO(1), 3);  in fd5_emit_restore()
1094    OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(1), 6);  in fd5_emit_restore()
1102    OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(2), 6);  in fd5_emit_restore()
1110    OUT_PKT4(ring, REG_A5XX_VPC_SO_BUFFER_OFFSET(3), 3);  in fd5_emit_restore()
1115    OUT_PKT4(ring, REG_A5XX_UNKNOWN_E5DB, 1);  in fd5_emit_restore()
1118    OUT_PKT4(ring, REG_A5XX_SP_HS_CTRL_REG0, 1);  in fd5_emit_restore()
1121    OUT_PKT4(ring, REG_A5XX_SP_GS_CTRL_REG0, 1);  in fd5_emit_restore()
1124    OUT_PKT4(ring, REG_A5XX_TPL1_VS_TEX_COUNT, 4);  in fd5_emit_restore()
1130    OUT_PKT4(ring, REG_A5XX_TPL1_FS_TEX_COUNT, 2);  in fd5_emit_restore()
1134    OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C0, 3);  in fd5_emit_restore()
1139    OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7C5, 3);  in fd5_emit_restore()
1144    OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CA, 3);  in fd5_emit_restore()
1149    OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7CF, 3);  in fd5_emit_restore()
1154    OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D4, 3);  in fd5_emit_restore()
1159    OUT_PKT4(ring, REG_A5XX_UNKNOWN_E7D9, 3);  in fd5_emit_restore()
1164    OUT_PKT4(ring, REG_A5XX_RB_CLEAR_CNTL, 1);  in fd5_emit_restore()