Lines Matching refs:dst
1564 public void adrp(Register dst) {
1565 emitInt(ADRP.encoding | PcRelImmOp | rd(dst));
1574 public void adr(Register dst, int imm21) {
1575 emitInt(ADR.encoding | PcRelImmOp | rd(dst) | getPcRelativeImmEncoding(imm21));
1585 public void adr(Register dst, int imm21, int pos) {
1586 emitInt(ADR.encoding | PcRelImmOp | rd(dst) | getPcRelativeImmEncoding(imm21), pos);
1610 protected void add(int size, Register dst, Register src, int aimm) {
1611 assert !dst.equals(zr);
1613 addSubImmInstruction(ADD, dst, src, aimm, generalFromSize(size));
1625 protected void adds(int size, Register dst, Register src, int aimm) {
1626 assert !dst.equals(sp);
1628 addSubImmInstruction(ADDS, dst, src, aimm, generalFromSize(size));
1640 protected void sub(int size, Register dst, Register src, int aimm) {
1641 assert !dst.equals(zr);
1643 addSubImmInstruction(SUB, dst, src, aimm, generalFromSize(size));
1655 protected void subs(int size, Register dst, Register src, int aimm) {
1656 assert !dst.equals(sp);
1658 addSubImmInstruction(SUBS, dst, src, aimm, generalFromSize(size));
1661 …private void addSubImmInstruction(Instruction instr, Register dst, Register src, int aimm, Instruc…
1662 … emitInt(type.encoding | instr.encoding | AddSubImmOp | encodeAimm(aimm) | rd(dst) | rs1(src));
1708 public void and(int size, Register dst, Register src, long bimm) {
1709 assert !dst.equals(zr);
1711 logicalImmInstruction(AND, dst, src, bimm, generalFromSize(size));
1722 public void ands(int size, Register dst, Register src, long bimm) {
1723 assert !dst.equals(sp);
1725 logicalImmInstruction(ANDS, dst, src, bimm, generalFromSize(size));
1736 public void eor(int size, Register dst, Register src, long bimm) {
1737 assert !dst.equals(zr);
1739 logicalImmInstruction(EOR, dst, src, bimm, generalFromSize(size));
1750 protected void orr(int size, Register dst, Register src, long bimm) {
1751 assert !dst.equals(zr);
1753 logicalImmInstruction(ORR, dst, src, bimm, generalFromSize(size));
1756 …private void logicalImmInstruction(Instruction instr, Register dst, Register src, long bimm, Instr…
1766 emitInt(type.encoding | instr.encoding | LogicalImmOp | immEncoding | rd(dst) | rs1(src));
1780 protected void movz(int size, Register dst, int uimm16, int shiftAmt) {
1781 moveWideImmInstruction(MOVZ, dst, uimm16, shiftAmt, generalFromSize(size));
1793 protected void movn(int size, Register dst, int uimm16, int shiftAmt) {
1794 moveWideImmInstruction(MOVN, dst, uimm16, shiftAmt, generalFromSize(size));
1806 protected void movk(int size, Register dst, int uimm16, int pos) {
1807 moveWideImmInstruction(MOVK, dst, uimm16, pos, generalFromSize(size));
1810 …private void moveWideImmInstruction(Instruction instr, Register dst, int uimm16, int shiftAmt, Ins…
1811 assert dst.getRegisterCategory().equals(CPU);
1815 …emitInt(type.encoding | instr.encoding | MoveWideImmOp | rd(dst) | uimm16 << MoveWideImmOffset | s…
1829 public void bfm(int size, Register dst, Register src, int r, int s) {
1830 bitfieldInstruction(BFM, dst, src, r, s, generalFromSize(size));
1842 public void ubfm(int size, Register dst, Register src, int r, int s) {
1843 bitfieldInstruction(UBFM, dst, src, r, s, generalFromSize(size));
1855 protected void sbfm(int size, Register dst, Register src, int r, int s) {
1856 bitfieldInstruction(SBFM, dst, src, r, s, generalFromSize(size));
1859 …private void bitfieldInstruction(Instruction instr, Register dst, Register src, int r, int s, Inst…
1860 assert !dst.equals(sp) && !dst.equals(zr);
1864 …ing | BitfieldImmOp | sf | r << ImmediateRotateOffset | s << ImmediateOffset | rd(dst) | rs1(src));
1878 protected void extr(int size, Register dst, Register src1, Register src2, int lsb) {
1879 assert !dst.equals(sp);
1885 …emitInt(type.encoding | EXTR.encoding | sf | lsb << ImmediateOffset | rd(dst) | rs1(src1) | rs2(sr…
1900 …protected void add(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int …
1901 addSubShiftedInstruction(ADD, dst, src1, src2, shiftType, imm, generalFromSize(size));
1914 …public void adds(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int im…
1915 addSubShiftedInstruction(ADDS, dst, src1, src2, shiftType, imm, generalFromSize(size));
1928 …protected void sub(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int …
1929 addSubShiftedInstruction(SUB, dst, src1, src2, shiftType, imm, generalFromSize(size));
1942 …public void subs(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int im…
1943 addSubShiftedInstruction(SUBS, dst, src1, src2, shiftType, imm, generalFromSize(size));
1946 …private void addSubShiftedInstruction(Instruction instr, Register dst, Register src1, Register src…
1949 …edOp | imm << ImmediateOffset | shiftType.encoding << ShiftTypeOffset | rd(dst) | rs1(src1) | rs2(…
1963 …public void add(int size, Register dst, Register src1, Register src2, ExtendType extendType, int s…
1964 assert !dst.equals(zr);
1967 … addSubExtendedInstruction(ADD, dst, src1, src2, extendType, shiftAmt, generalFromSize(size));
1980 …protected void adds(int size, Register dst, Register src1, Register src2, ExtendType extendType, i…
1981 assert !dst.equals(sp);
1984 … addSubExtendedInstruction(ADDS, dst, src1, src2, extendType, shiftAmt, generalFromSize(size));
1997 …public void sub(int size, Register dst, Register src1, Register src2, ExtendType extendType, int s…
1998 assert !dst.equals(zr);
2001 … addSubExtendedInstruction(SUB, dst, src1, src2, extendType, shiftAmt, generalFromSize(size));
2014 …public void subs(int size, Register dst, Register src1, Register src2, ExtendType extendType, int …
2015 assert !dst.equals(sp);
2018 … addSubExtendedInstruction(SUBS, dst, src1, src2, extendType, shiftAmt, generalFromSize(size));
2021 …private void addSubExtendedInstruction(Instruction instr, Register dst, Register src1, Register sr…
2023 …shiftAmt << ImmediateOffset | extendType.encoding << ExtendTypeOffset | rd(dst) | rs1(src1) | rs2(…
2037 …protected void and(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int …
2038 logicalRegInstruction(AND, dst, src1, src2, shiftType, shiftAmt, generalFromSize(size));
2051 …protected void ands(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int…
2052 logicalRegInstruction(ANDS, dst, src1, src2, shiftType, shiftAmt, generalFromSize(size));
2065 …protected void bic(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int …
2066 logicalRegInstruction(BIC, dst, src1, src2, shiftType, shiftAmt, generalFromSize(size));
2079 …protected void bics(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int…
2080 logicalRegInstruction(BICS, dst, src1, src2, shiftType, shiftAmt, generalFromSize(size));
2093 …protected void eon(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int …
2094 logicalRegInstruction(EON, dst, src1, src2, shiftType, shiftAmt, generalFromSize(size));
2107 …protected void eor(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int …
2108 logicalRegInstruction(EOR, dst, src1, src2, shiftType, shiftAmt, generalFromSize(size));
2121 …protected void orr(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int …
2122 logicalRegInstruction(ORR, dst, src1, src2, shiftType, shiftAmt, generalFromSize(size));
2135 …protected void orn(int size, Register dst, Register src1, Register src2, ShiftType shiftType, int …
2136 logicalRegInstruction(ORN, dst, src1, src2, shiftType, shiftAmt, generalFromSize(size));
2139 …private void logicalRegInstruction(Instruction instr, Register dst, Register src1, Register src2, …
2140 assert !dst.equals(sp);
2144 …| shiftAmt << ImmediateOffset | shiftType.encoding << ShiftTypeOffset | rd(dst) | rs1(src1) | rs2(…
2156 protected void asr(int size, Register dst, Register src1, Register src2) {
2157 dataProcessing2SourceOp(ASRV, dst, src1, src2, generalFromSize(size));
2168 protected void lsl(int size, Register dst, Register src1, Register src2) {
2169 dataProcessing2SourceOp(LSLV, dst, src1, src2, generalFromSize(size));
2180 protected void lsr(int size, Register dst, Register src1, Register src2) {
2181 dataProcessing2SourceOp(LSRV, dst, src1, src2, generalFromSize(size));
2192 protected void rorv(int size, Register dst, Register src1, Register src2) {
2193 dataProcessing2SourceOp(RORV, dst, src1, src2, generalFromSize(size));
2207 protected void cls(int size, Register dst, Register src) {
2208 dataProcessing1SourceOp(CLS, dst, src, generalFromSize(size));
2218 public void clz(int size, Register dst, Register src) {
2219 dataProcessing1SourceOp(CLZ, dst, src, generalFromSize(size));
2229 public void rbit(int size, Register dst, Register src) {
2230 dataProcessing1SourceOp(RBIT, dst, src, generalFromSize(size));
2240 public void rev(int size, Register dst, Register src) {
2242 dataProcessing1SourceOp(REVX, dst, src, generalFromSize(size));
2245 dataProcessing1SourceOp(REVW, dst, src, generalFromSize(size));
2260 …protected void csel(int size, Register dst, Register src1, Register src2, ConditionFlag condition)…
2261 conditionalSelectInstruction(CSEL, dst, src1, src2, condition, generalFromSize(size));
2273 …protected void csneg(int size, Register dst, Register src1, Register src2, ConditionFlag condition…
2274 conditionalSelectInstruction(CSNEG, dst, src1, src2, condition, generalFromSize(size));
2286 …protected void csinc(int size, Register dst, Register src1, Register src2, ConditionFlag condition…
2287 conditionalSelectInstruction(CSINC, dst, src1, src2, condition, generalFromSize(size));
2290 …private void conditionalSelectInstruction(Instruction instr, Register dst, Register src1, Register…
2291 assert !dst.equals(sp);
2294 …emitInt(type.encoding | instr.encoding | ConditionalSelectOp | rd(dst) | rs1(src1) | rs2(src2) | c…
2308 protected void madd(int size, Register dst, Register src1, Register src2, Register src3) {
2309 mulInstruction(MADD, dst, src1, src2, src3, generalFromSize(size));
2321 protected void msub(int size, Register dst, Register src1, Register src2, Register src3) {
2322 mulInstruction(MSUB, dst, src1, src2, src3, generalFromSize(size));
2332 protected void smulh(Register dst, Register src1, Register src2) {
2333 assert !dst.equals(sp);
2336 … emitInt(0b10011011010 << 21 | dst.encoding | rs1(src1) | rs2(src2) | 0b011111 << ImmediateOffset);
2346 protected void umulh(Register dst, Register src1, Register src2) {
2347 assert !dst.equals(sp);
2350 … emitInt(0b10011011110 << 21 | dst.encoding | rs1(src1) | rs2(src2) | 0b011111 << ImmediateOffset);
2361 protected void umaddl(Register dst, Register src1, Register src2, Register src3) {
2362 assert !dst.equals(sp);
2366 … emitInt(0b10011011101 << 21 | dst.encoding | rs1(src1) | rs2(src2) | 0b011111 << ImmediateOffset);
2377 public void smaddl(Register dst, Register src1, Register src2, Register src3) {
2378 smullInstruction(MADD, dst, src1, src2, src3);
2389 public void smsubl(Register dst, Register src1, Register src2, Register src3) {
2390 smullInstruction(MSUB, dst, src1, src2, src3);
2393 …private void mulInstruction(Instruction instr, Register dst, Register src1, Register src2, Registe…
2394 assert !dst.equals(sp);
2398 … emitInt(type.encoding | instr.encoding | MulOp | rd(dst) | rs1(src1) | rs2(src2) | rs3(src3));
2401 …private void smullInstruction(Instruction instr, Register dst, Register src1, Register src2, Regis…
2402 assert !dst.equals(sp);
2406 emitInt(instr.encoding | SignedMulLongOp | rd(dst) | rs1(src1) | rs2(src2) | rs3(src3));
2417 public void sdiv(int size, Register dst, Register src1, Register src2) {
2418 dataProcessing2SourceOp(SDIV, dst, src1, src2, generalFromSize(size));
2429 public void udiv(int size, Register dst, Register src1, Register src2) {
2430 dataProcessing2SourceOp(UDIV, dst, src1, src2, generalFromSize(size));
2433 …private void dataProcessing1SourceOp(Instruction instr, Register dst, Register src, InstructionTyp…
2434 emitInt(type.encoding | instr.encoding | DataProcessing1SourceOp | rd(dst) | rs1(src));
2437 …private void dataProcessing2SourceOp(Instruction instr, Register dst, Register src1, Register src2…
2438 assert !dst.equals(sp);
2441 …emitInt(type.encoding | instr.encoding | DataProcessing2SourceOp | rd(dst) | rs1(src1) | rs2(src2)…
2484 protected void fmov(int size, Register dst, Register src) {
2485 fpDataProcessing1Source(FMOV, dst, src, floatFromSize(size));
2495 protected void fmovFpu2Cpu(int size, Register dst, Register src) {
2496 assert dst.getRegisterCategory().equals(CPU);
2498 fmovCpuFpuInstruction(dst, src, size == 64, Instruction.FMOVFPU2CPU);
2508 protected void fmovCpu2Fpu(int size, Register dst, Register src) {
2509 assert dst.getRegisterCategory().equals(SIMD);
2511 fmovCpuFpuInstruction(dst, src, size == 64, Instruction.FMOVCPU2FPU);
2514 …private void fmovCpuFpuInstruction(Register dst, Register src, boolean is64bit, Instruction instr)…
2516 emitInt(sf | instr.encoding | FpConvertOp | rd(dst) | rs1(src));
2531 protected void fmov(int size, Register dst, double imm) {
2532 assert dst.getRegisterCategory().equals(SIMD);
2541 emitInt(type.encoding | FMOV.encoding | FpImmOp | immEncoding | rd(dst));
2611 public void fcvt(int srcSize, Register dst, Register src) {
2613 fpDataProcessing1Source(FCVTDS, dst, src, floatFromSize(srcSize));
2615 fpDataProcessing1Source(FCVTSD, dst, src, floatFromSize(srcSize));
2629 public void fcvtzs(int targetSize, int srcSize, Register dst, Register src) {
2630 assert !dst.equals(zr) && !dst.equals(sp);
2632 … fcvtCpuFpuInstruction(FCVTZS, dst, src, generalFromSize(targetSize), floatFromSize(srcSize));
2644 public void scvtf(int targetSize, int srcSize, Register dst, Register src) {
2645 assert dst.getRegisterCategory().equals(SIMD);
2647 fcvtCpuFpuInstruction(SCVTF, dst, src, floatFromSize(targetSize), generalFromSize(srcSize));
2650 …private void fcvtCpuFpuInstruction(Instruction instr, Register dst, Register src, InstructionType …
2651 … emitInt(type1.encoding | type2.encoding | instr.encoding | FpConvertOp | rd(dst) | rs1(src));
2663 protected void frintz(int size, Register dst, Register src) {
2664 fpDataProcessing1Source(FRINTZ, dst, src, floatFromSize(size));
2674 public void frintn(int size, Register dst, Register src) {
2675 fpDataProcessing1Source(FRINTN, dst, src, floatFromSize(size));
2685 public void frintm(int size, Register dst, Register src) {
2686 fpDataProcessing1Source(FRINTM, dst, src, floatFromSize(size));
2696 public void frintp(int size, Register dst, Register src) {
2697 fpDataProcessing1Source(FRINTP, dst, src, floatFromSize(size));
2709 public void fabs(int size, Register dst, Register src) {
2710 fpDataProcessing1Source(FABS, dst, src, floatFromSize(size));
2720 public void fneg(int size, Register dst, Register src) {
2721 fpDataProcessing1Source(FNEG, dst, src, floatFromSize(size));
2731 public void fsqrt(int size, Register dst, Register src) {
2732 fpDataProcessing1Source(FSQRT, dst, src, floatFromSize(size));
2735 …private void fpDataProcessing1Source(Instruction instr, Register dst, Register src, InstructionTyp…
2736 assert dst.getRegisterCategory().equals(SIMD);
2738 emitInt(type.encoding | instr.encoding | Fp1SourceOp | rd(dst) | rs1(src));
2751 public void fadd(int size, Register dst, Register src1, Register src2) {
2752 fpDataProcessing2Source(FADD, dst, src1, src2, floatFromSize(size));
2763 public void fsub(int size, Register dst, Register src1, Register src2) {
2764 fpDataProcessing2Source(FSUB, dst, src1, src2, floatFromSize(size));
2775 public void fmul(int size, Register dst, Register src1, Register src2) {
2776 fpDataProcessing2Source(FMUL, dst, src1, src2, floatFromSize(size));
2787 public void fdiv(int size, Register dst, Register src1, Register src2) {
2788 fpDataProcessing2Source(FDIV, dst, src1, src2, floatFromSize(size));
2791 …private void fpDataProcessing2Source(Instruction instr, Register dst, Register src1, Register src2…
2792 assert dst.getRegisterCategory().equals(SIMD);
2795 emitInt(type.encoding | instr.encoding | Fp2SourceOp | rd(dst) | rs1(src1) | rs2(src2));
2809 protected void fmadd(int size, Register dst, Register src1, Register src2, Register src3) {
2810 fpDataProcessing3Source(FMADD, dst, src1, src2, src3, floatFromSize(size));
2822 protected void fmsub(int size, Register dst, Register src1, Register src2, Register src3) {
2823 fpDataProcessing3Source(FMSUB, dst, src1, src2, src3, floatFromSize(size));
2826 …private void fpDataProcessing3Source(Instruction instr, Register dst, Register src1, Register src2…
2827 assert dst.getRegisterCategory().equals(SIMD);
2831 …emitInt(type.encoding | instr.encoding | Fp3SourceOp | rd(dst) | rs1(src1) | rs2(src2) | rs3(src3)…
2916 …protected void fcsel(int size, Register dst, Register src1, Register src2, ConditionFlag condition…
2917 assert dst.getRegisterCategory().equals(SIMD);
2921 …emitInt(type.encoding | FCSEL.encoding | rd(dst) | rs1(src1) | rs2(src2) | condition.encoding << C…
3033 public void mrs(Register dst, SystemRegister systemRegister) {
3034 emitInt(MRS.encoding | systemRegister.encoding() | rt(dst));
3165 public void cnt(int size, Register dst, Register src) {
3167 emitInt((size >> 7) << SIMDQBitOffset | CNT.encoding | rd(dst) | rs1(src));
3178 public void addv(int size, SIMDElementSize laneWidth, Register dst, Register src) {
3182 … 7) << SIMDQBitOffset | laneWidth.encoding << SIMDSizeOffset | ADDV.encoding | rd(dst) | rs1(src));
3193 public void umov(int size, Register dst, int srcIdx, Register src) {
3197 …emitInt((size >> 6) << SIMDQBitOffset | imm5 << SIMDImm5Offset | UMOV.encoding | rd(dst) | rs1(src…