3493   int i, epilogue_p, regno, alt_regno, cfa_off, n_varargs;  in ia64_expand_prologue()  local
3688 	  alt_regno = next_scratch_gr_reg ();  in ia64_expand_prologue()
3689 	  ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);  in ia64_expand_prologue()
3690 	  current_frame_info.gr_used_mask |= 1 << alt_regno;  in ia64_expand_prologue()
3747 	  alt_regno = next_scratch_gr_reg ();  in ia64_expand_prologue()
3748 	  alt_reg = gen_rtx_REG (DImode, alt_regno);  in ia64_expand_prologue()
3793 	  alt_regno = next_scratch_gr_reg ();  in ia64_expand_prologue()
3794 	  alt_reg = gen_rtx_REG (DImode, alt_regno);  in ia64_expand_prologue()
3820 	  alt_regno = next_scratch_gr_reg ();  in ia64_expand_prologue()
3821 	  alt_reg = gen_rtx_REG (DImode, alt_regno);  in ia64_expand_prologue()
3853 	alt_regno = next_scratch_gr_reg ();  in ia64_expand_prologue()
3854 	alt_reg = gen_rtx_REG (DImode, alt_regno);  in ia64_expand_prologue()
3904   int regno, alt_regno, cfa_off;  in ia64_expand_epilogue()  local
3941 	  alt_regno = next_scratch_gr_reg ();  in ia64_expand_epilogue()
3942 	  alt_reg = gen_rtx_REG (DImode, alt_regno);  in ia64_expand_epilogue()
3964 	  alt_regno = next_scratch_gr_reg ();  in ia64_expand_epilogue()
3965 	  ar_unat_save_reg = gen_rtx_REG (DImode, alt_regno);  in ia64_expand_epilogue()
3966 	  current_frame_info.gr_used_mask |= 1 << alt_regno;  in ia64_expand_epilogue()
3983       alt_regno = next_scratch_gr_reg ();  in ia64_expand_epilogue()
3984       alt_reg = gen_rtx_REG (DImode, alt_regno);  in ia64_expand_epilogue()
4000 	  alt_regno = next_scratch_gr_reg ();  in ia64_expand_epilogue()
4001 	  alt_reg = gen_rtx_REG (DImode, alt_regno);  in ia64_expand_epilogue()
4019 	  alt_regno = next_scratch_gr_reg ();  in ia64_expand_epilogue()
4020 	  alt_reg = gen_rtx_REG (DImode, alt_regno);  in ia64_expand_epilogue()
4050 	alt_regno = next_scratch_gr_reg ();  in ia64_expand_epilogue()
4051 	alt_reg = gen_rtx_REG (DImode, alt_regno);  in ia64_expand_epilogue()