comp/armv6/geninstr.sl

146 		   (,(subst "" '*set* namepattern) . ,(subst 0 '*setbit* l))
147 		   (,(subst 'S '*set* namepattern) . ,(subst 1 '*setbit* l))
184     (if (not (or (memq '*condbits* l) (memq '*setbit* l)))
188 		     (if (or (numberp x) (memq x '(*condbits* *setbit*)))
362 …tr AND (AND *cond* *set*)  (reg reg reg-shifter)     OP-reg-shifter  *condbits* 2#0000000 *setbit*)
363 …tr AND (AND *cond* *set*)  (reg reg imm8-rotated)    OP-reg-imm8     *condbits* 2#0010000 *setbit*)
364 …tr EOR (EOR *cond* *set*)  (reg reg reg-shifter)     OP-reg-shifter  *condbits* 2#0000001 *setbit*)
365 …tr EOR (EOR *cond* *set*)  (reg reg imm8-rotated)    OP-reg-imm8     *condbits* 2#0010001 *setbit*)
366 …tr SUB (SUB *cond* *set*)  (reg reg reg-shifter)     OP-reg-shifter  *condbits* 2#0000010 *setbit*)
367 …tr SUB (SUB *cond* *set*)  (reg reg imm8-rotated)    OP-reg-imm8     *condbits* 2#0010010 *setbit*)
368 …tr RSB (RSB *cond* *set*)  (reg reg reg-shifter)     OP-reg-shifter  *condbits* 2#0000011 *setbit*)
369 …tr RSB (RSB *cond* *set*)  (reg reg imm8-rotated)    OP-reg-imm8     *condbits* 2#0010011 *setbit*)
370 …tr ADD (ADD *cond* *set*)  (reg reg reg-shifter)     OP-reg-shifter  *condbits* 2#0000100 *setbit*)
371 …tr ADD (ADD *cond* *set*)  (reg reg imm8-rotated)    OP-reg-imm8     *condbits* 2#0010100 *setbit*)
372 …tr ADC (ADC *cond* *set*)  (reg reg reg-shifter)     OP-reg-shifter  *condbits* 2#0000101 *setbit*)
373 …tr ADC (ADC *cond* *set*)  (reg reg imm8-rotated)    OP-reg-imm8     *condbits* 2#0010101 *setbit*)
374 …tr SBC (SBC *cond* *set*)  (reg reg reg-shifter)     OP-reg-shifter  *condbits* 2#0000110 *setbit*)
375 …tr SBC (SBC *cond* *set*)  (reg reg imm8-rotated)    OP-reg-imm8     *condbits* 2#0010110 *setbit*)
376 …tr RSC (RSC *cond* *set*)  (reg reg reg-shifter)     OP-reg-shifter  *condbits* 2#0000111 *setbit*)
377 …tr RSC (RSC *cond* *set*)  (reg reg imm8-rotated)    OP-reg-imm8     *condbits* 2#0010111 *setbit*)
386 …tr ORR (ORR *cond* *set*)  (reg reg reg-shifter)     OP-reg-shifter  *condbits* 2#0001100 *setbit*)
387 …tr ORR (ORR *cond* *set*)  (reg reg imm8-rotated)    OP-reg-imm8     *condbits* 2#0011100 *setbit*)
388 …tr MOV (MOV *cond* *set*)  (reg reg-shifter)         OP-regd-shifter *condbits* 2#0001101 *setbit*)
389 …tr MOV (MOV *cond* *set*)  (reg imm8-rotated)        OP-regd-imm8    *condbits* 2#0011101 *setbit*)
390 …tr BIC (BIC *cond* *set*)  (reg reg reg-shifter)     OP-reg-shifter  *condbits* 2#0001110 *setbit*)
391 …tr BIC (BIC *cond* *set*)  (reg reg imm8-rotated)    OP-reg-imm8     *condbits* 2#0011110 *setbit*)
392 …tr MVN (MVN *cond* *set*)  (reg reg-shifter)         OP-regd-shifter *condbits* 2#0001111 *setbit*)
393 …tr MVN (MVN *cond* *set*)  (reg imm8-rotated)        OP-regd-imm8    *condbits* 2#0011111 *setbit*)
404 (instr MUL (MUL *cond* *set*)  (reg reg reg)             OP-mul3      *condbits* 2#0000000 *setbit*…
405 (instr MLA (MLA *cond* *set*)  (reg reg reg reg)         OP-mul4      *condbits* 2#0000001 *setbit*…
406 (instr UMULL (UMULL *cond* *set*)(reg reg reg reg)       OP-mul4      *condbits* 2#0000100 *setbit*…
407 (instr UMLAL (UMLAL *cond* *set*)(reg reg reg reg)       OP-mul4      *condbits* 2#0000101 *setbit*…
408 (instr SMULL (SMULL *cond* *set*)(reg reg reg reg)       OP-mul4      *condbits* 2#0000110 *setbit*…
409 (instr SMLAL (SMLAL *cond* *set*)(reg reg reg reg)       OP-mul4      *condbits* 2#0000111 *setbit*…