Lines Matching refs:MCFG_BUS_ANY
39 #define MCFG_BUS_ANY MCFG_BUS_RANGE(0x0, 0xff) macro
45 { "AMAZON", table_id, rev, seg, MCFG_BUS_ANY, ops }
57 { "QCOM ", "QDF2432 ", 1, seg, MCFG_BUS_ANY, &pci_32b_ops }
69 { "HISI ", table_id, 0, (seg) + 0, MCFG_BUS_ANY, ops }, \
70 { "HISI ", table_id, 0, (seg) + 1, MCFG_BUS_ANY, ops }, \
71 { "HISI ", table_id, 0, (seg) + 2, MCFG_BUS_ANY, ops }, \
72 { "HISI ", table_id, 0, (seg) + 3, MCFG_BUS_ANY, ops }
85 { "CAVIUM", "THUNDERX", rev, 4 + (10 * (node)), MCFG_BUS_ANY, \
87 { "CAVIUM", "THUNDERX", rev, 5 + (10 * (node)), MCFG_BUS_ANY, \
89 { "CAVIUM", "THUNDERX", rev, 6 + (10 * (node)), MCFG_BUS_ANY, \
91 { "CAVIUM", "THUNDERX", rev, 7 + (10 * (node)), MCFG_BUS_ANY, \
93 { "CAVIUM", "THUNDERX", rev, 8 + (10 * (node)), MCFG_BUS_ANY, \
95 { "CAVIUM", "THUNDERX", rev, 9 + (10 * (node)), MCFG_BUS_ANY, \
99 { "CAVIUM", "THUNDERX", rev, seg, MCFG_BUS_ANY, \
119 { "NVIDIA", "TEGRA194", 1, 0, MCFG_BUS_ANY, &tegra194_pcie_ops},
120 { "NVIDIA", "TEGRA194", 1, 1, MCFG_BUS_ANY, &tegra194_pcie_ops},
121 { "NVIDIA", "TEGRA194", 1, 2, MCFG_BUS_ANY, &tegra194_pcie_ops},
122 { "NVIDIA", "TEGRA194", 1, 3, MCFG_BUS_ANY, &tegra194_pcie_ops},
123 { "NVIDIA", "TEGRA194", 1, 4, MCFG_BUS_ANY, &tegra194_pcie_ops},
124 { "NVIDIA", "TEGRA194", 1, 5, MCFG_BUS_ANY, &tegra194_pcie_ops},
127 {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
131 {"APM ", "XGENE ", rev, seg, MCFG_BUS_ANY, \
154 { "Ampere", "Altra ", rev, seg, MCFG_BUS_ANY, &pci_32b_read_ops }