2058 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {  in gfx_v6_0_cp_gfx_start()
2380 	adev->gfx.rlc.reg_list = verde_rlc_save_restore_register_list;  in gfx_v6_0_rlc_init()
2381 	adev->gfx.rlc.reg_list_size =  in gfx_v6_0_rlc_init()
2384 	adev->gfx.rlc.cs_data = si_cs_data;  in gfx_v6_0_rlc_init()
2385 	src_ptr = adev->gfx.rlc.reg_list;  in gfx_v6_0_rlc_init()
2386 	dws = adev->gfx.rlc.reg_list_size;  in gfx_v6_0_rlc_init()
2387 	cs_data = adev->gfx.rlc.cs_data;  in gfx_v6_0_rlc_init()
2398 		adev->gfx.rlc.clear_state_size = gfx_v6_0_get_csb_size(adev);  in gfx_v6_0_rlc_init()
2399 		dws = adev->gfx.rlc.clear_state_size + (256 / 4);  in gfx_v6_0_rlc_init()
2403 					      &adev->gfx.rlc.clear_state_obj,  in gfx_v6_0_rlc_init()
2404 					      &adev->gfx.rlc.clear_state_gpu_addr,  in gfx_v6_0_rlc_init()
2405 					      (void **)&adev->gfx.rlc.cs_ptr);  in gfx_v6_0_rlc_init()
2413 		dst_ptr = adev->gfx.rlc.cs_ptr;  in gfx_v6_0_rlc_init()
2414 		reg_list_mc_addr = adev->gfx.rlc.clear_state_gpu_addr + 256;  in gfx_v6_0_rlc_init()
2417 		dst_ptr[2] = cpu_to_le32(adev->gfx.rlc.clear_state_size);  in gfx_v6_0_rlc_init()
2419 		amdgpu_bo_kunmap(adev->gfx.rlc.clear_state_obj);  in gfx_v6_0_rlc_init()
2420 		amdgpu_bo_unreserve(adev->gfx.rlc.clear_state_obj);  in gfx_v6_0_rlc_init()
2453 static void gfx_v6_0_update_rlc(struct amdgpu_device *adev, u32 rlc)  in gfx_v6_0_update_rlc()  argument
2458 	if (tmp != rlc)  in gfx_v6_0_update_rlc()
2459 		WREG32(mmRLC_CNTL, rlc);  in gfx_v6_0_update_rlc()
2529 	adev->gfx.rlc.funcs->stop(adev);  in gfx_v6_0_rlc_resume()
2530 	adev->gfx.rlc.funcs->reset(adev);  in gfx_v6_0_rlc_resume()
2558 	adev->gfx.rlc.funcs->start(adev);  in gfx_v6_0_rlc_resume()
2824 	WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);  in gfx_v6_0_init_gfx_cgpg()
2826 	WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);  in gfx_v6_0_init_gfx_cgpg()
2848 	if (adev->gfx.rlc.cs_data == NULL)  in gfx_v6_0_get_csb_size()
2856 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {  in gfx_v6_0_get_csb_size()
2881 	if (adev->gfx.rlc.cs_data == NULL)  in gfx_v6_0_get_csb_buffer()
2892 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {  in gfx_v6_0_get_csb_buffer()
2932 			WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);  in gfx_v6_0_init_pg()
2933 			WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);  in gfx_v6_0_init_pg()
2940 		WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);  in gfx_v6_0_init_pg()
2941 		WREG32(mmRLC_CLEAR_STATE_RESTORE_BASE, adev->gfx.rlc.clear_state_gpu_addr >> 8);  in gfx_v6_0_init_pg()
3071 	adev->gfx.rlc.funcs = &gfx_v6_0_rlc_funcs;  in gfx_v6_0_early_init()
3104 	r = adev->gfx.rlc.funcs->init(adev);  in gfx_v6_0_sw_init()
3170 	r = adev->gfx.rlc.funcs->resume(adev);  in gfx_v6_0_hw_init()
3188 	adev->gfx.rlc.funcs->stop(adev);  in gfx_v6_0_hw_fini()