Lines Matching refs:pmu_base
188 void __iomem *pmu_base; member
690 u64 reg = readq_relaxed(xp->pmu_base + offset); in arm_cmn_read_dtm()
777 writeq_relaxed(val, dn->pmu_base + CMN_DTM_WPn_VAL(wp_idx)); in arm_cmn_event_start()
778 writeq_relaxed(mask, dn->pmu_base + CMN_DTM_WPn_MASK(wp_idx)); in arm_cmn_event_start()
784 writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL); in arm_cmn_event_start()
803 writeq_relaxed(0, dn->pmu_base + CMN_DTM_WPn_MASK(wp_idx)); in arm_cmn_event_stop()
804 writeq_relaxed(~0ULL, dn->pmu_base + CMN_DTM_WPn_VAL(wp_idx)); in arm_cmn_event_stop()
810 writel_relaxed(le32_to_cpu(dn->event_sel), dn->pmu_base + CMN_PMU_EVENT_SEL); in arm_cmn_event_stop()
1001 writel_relaxed(xp->pmu_config_low, xp->pmu_base + CMN_DTM_PMU_CONFIG); in arm_cmn_event_clear()
1068 writel_relaxed(cfg, dn->pmu_base + CMN_DTM_WPn_CONFIG(wp_idx)); in arm_cmn_event_add()
1082 dn->pmu_base + CMN_PMU_EVENT_SEL + 4); in arm_cmn_event_add()
1098 writeq_relaxed(reg, xp->pmu_base + CMN_DTM_PMU_CONFIG); in arm_cmn_event_add()
1240 writeq_relaxed(0, xp->pmu_base + CMN_DTM_WPn_MASK(i)); in arm_cmn_init_dtm()
1241 writeq_relaxed(~0ULL, xp->pmu_base + CMN_DTM_WPn_VAL(i)); in arm_cmn_init_dtm()
1252 dtc->base = dn->pmu_base - CMN_PMU_OFFSET; in arm_cmn_init_dtc()
1320 node->pmu_base = cmn->base + offset + CMN_PMU_OFFSET; in arm_cmn_init_node_info()