Lines Matching refs:gmc
267 err = request_firmware(&adev->gmc.fw, fw_name, adev->dev); in gmc_v8_0_init_microcode()
270 err = amdgpu_ucode_validate(adev->gmc.fw); in gmc_v8_0_init_microcode()
275 release_firmware(adev->gmc.fw); in gmc_v8_0_init_microcode()
276 adev->gmc.fw = NULL; in gmc_v8_0_init_microcode()
305 if (!adev->gmc.fw) in gmc_v8_0_tonga_mc_load_microcode()
308 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v8_0_tonga_mc_load_microcode()
311 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v8_0_tonga_mc_load_microcode()
314 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v8_0_tonga_mc_load_microcode()
317 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v8_0_tonga_mc_load_microcode()
374 if (!adev->gmc.fw) in gmc_v8_0_polaris_mc_load_microcode()
377 hdr = (const struct mc_firmware_header_v1_0 *)adev->gmc.fw->data; in gmc_v8_0_polaris_mc_load_microcode()
380 adev->gmc.fw_version = le32_to_cpu(hdr->header.ucode_version); in gmc_v8_0_polaris_mc_load_microcode()
383 (adev->gmc.fw->data + le32_to_cpu(hdr->io_debug_array_offset_bytes)); in gmc_v8_0_polaris_mc_load_microcode()
386 (adev->gmc.fw->data + le32_to_cpu(hdr->header.ucode_array_offset_bytes)); in gmc_v8_0_polaris_mc_load_microcode()
473 adev->gmc.vram_start >> 12); in gmc_v8_0_mc_program()
475 adev->gmc.vram_end >> 12); in gmc_v8_0_mc_program()
480 tmp = ((adev->gmc.vram_end >> 24) & 0xFFFF) << 16; in gmc_v8_0_mc_program()
481 tmp |= ((adev->gmc.vram_start >> 24) & 0xFFFF); in gmc_v8_0_mc_program()
484 WREG32(mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); in gmc_v8_0_mc_program()
519 adev->gmc.vram_width = amdgpu_atombios_get_vram_width(adev); in gmc_v8_0_mc_init()
520 if (!adev->gmc.vram_width) { in gmc_v8_0_mc_init()
562 adev->gmc.vram_width = numchan * chansize; in gmc_v8_0_mc_init()
565 adev->gmc.mc_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; in gmc_v8_0_mc_init()
566 adev->gmc.real_vram_size = RREG32(mmCONFIG_MEMSIZE) * 1024ULL * 1024ULL; in gmc_v8_0_mc_init()
573 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); in gmc_v8_0_mc_init()
574 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); in gmc_v8_0_mc_init()
578 adev->gmc.aper_base = ((u64)RREG32(mmMC_VM_FB_OFFSET)) << 22; in gmc_v8_0_mc_init()
579 adev->gmc.aper_size = adev->gmc.real_vram_size; in gmc_v8_0_mc_init()
584 adev->gmc.visible_vram_size = adev->gmc.aper_size; in gmc_v8_0_mc_init()
585 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) in gmc_v8_0_mc_init()
586 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; in gmc_v8_0_mc_init()
596 adev->gmc.gart_size = 256ULL << 20; in gmc_v8_0_mc_init()
602 adev->gmc.gart_size = 1024ULL << 20; in gmc_v8_0_mc_init()
606 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; in gmc_v8_0_mc_init()
609 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; in gmc_v8_0_mc_init()
610 gmc_v8_0_vram_gtt_location(adev, &adev->gmc); in gmc_v8_0_mc_init()
772 if (enable && !adev->gmc.prt_warning) { in gmc_v8_0_set_prt()
774 adev->gmc.prt_warning = true; in gmc_v8_0_set_prt()
891 WREG32(mmVM_CONTEXT0_PAGE_TABLE_START_ADDR, adev->gmc.gart_start >> 12); in gmc_v8_0_gart_enable()
892 WREG32(mmVM_CONTEXT0_PAGE_TABLE_END_ADDR, adev->gmc.gart_end >> 12); in gmc_v8_0_gart_enable()
947 (unsigned)(adev->gmc.gart_size >> 20), in gmc_v8_0_gart_enable()
1058 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; in gmc_v8_0_early_init()
1059 adev->gmc.shared_aperture_end = in gmc_v8_0_early_init()
1060 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; in gmc_v8_0_early_init()
1061 adev->gmc.private_aperture_start = in gmc_v8_0_early_init()
1062 adev->gmc.shared_aperture_end + 1; in gmc_v8_0_early_init()
1063 adev->gmc.private_aperture_end = in gmc_v8_0_early_init()
1064 adev->gmc.private_aperture_start + (4ULL << 30) - 1; in gmc_v8_0_early_init()
1074 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); in gmc_v8_0_late_init()
1106 adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN; in gmc_v8_0_sw_init()
1116 adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp); in gmc_v8_0_sw_init()
1119 …_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault); in gmc_v8_0_sw_init()
1123 …_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault); in gmc_v8_0_sw_init()
1137 adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */ in gmc_v8_0_sw_init()
1186 adev->gmc.vm_fault_info = kmalloc(sizeof(struct kfd_vm_fault_info), in gmc_v8_0_sw_init()
1188 if (!adev->gmc.vm_fault_info) in gmc_v8_0_sw_init()
1190 atomic_set(&adev->gmc.vm_fault_info_updated, 0); in gmc_v8_0_sw_init()
1201 kfree(adev->gmc.vm_fault_info); in gmc_v8_0_sw_fini()
1205 release_firmware(adev->gmc.fw); in gmc_v8_0_sw_fini()
1206 adev->gmc.fw = NULL; in gmc_v8_0_sw_fini()
1247 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); in gmc_v8_0_hw_fini()
1327 adev->gmc.srbm_soft_reset = srbm_soft_reset; in gmc_v8_0_check_soft_reset()
1330 adev->gmc.srbm_soft_reset = 0; in gmc_v8_0_check_soft_reset()
1339 if (!adev->gmc.srbm_soft_reset) in gmc_v8_0_pre_soft_reset()
1355 if (!adev->gmc.srbm_soft_reset) in gmc_v8_0_soft_reset()
1357 srbm_soft_reset = adev->gmc.srbm_soft_reset; in gmc_v8_0_soft_reset()
1385 if (!adev->gmc.srbm_soft_reset) in gmc_v8_0_post_soft_reset()
1479 && !atomic_read(&adev->gmc.vm_fault_info_updated)) { in gmc_v8_0_process_interrupt()
1480 struct kfd_vm_fault_info *info = adev->gmc.vm_fault_info; in gmc_v8_0_process_interrupt()
1496 atomic_set(&adev->gmc.vm_fault_info_updated, 1); in gmc_v8_0_process_interrupt()
1746 adev->gmc.gmc_funcs = &gmc_v8_0_gmc_funcs; in gmc_v8_0_set_gmc_funcs()
1751 adev->gmc.vm_fault.num_types = 1; in gmc_v8_0_set_irq_funcs()
1752 adev->gmc.vm_fault.funcs = &gmc_v8_0_irq_funcs; in gmc_v8_0_set_irq_funcs()