Lines Matching refs:gmc
654 adev->gmc.vm_fault.num_types = 1; in gmc_v9_0_set_irq_funcs()
655 adev->gmc.vm_fault.funcs = &gmc_v9_0_irq_funcs; in gmc_v9_0_set_irq_funcs()
658 !adev->gmc.xgmi.connected_to_cpu) { in gmc_v9_0_set_irq_funcs()
659 adev->gmc.ecc_irq.num_types = 1; in gmc_v9_0_set_irq_funcs()
660 adev->gmc.ecc_irq.funcs = &gmc_v9_0_ecc_funcs; in gmc_v9_0_set_irq_funcs()
743 if (adev->gmc.xgmi.num_physical_nodes && in gmc_v9_0_flush_gpu_tlb()
773 spin_lock(&adev->gmc.invalidate_lock); in gmc_v9_0_flush_gpu_tlb()
832 spin_unlock(&adev->gmc.invalidate_lock); in gmc_v9_0_flush_gpu_tlb()
872 bool vega20_xgmi_wa = (adev->gmc.xgmi.num_physical_nodes && in gmc_v9_0_flush_gpu_tlb_pasid()
1056 if (!adev->gmc.translate_further) in gmc_v9_0_get_vm_pde()
1145 adev->gmc.gmc_funcs = &gmc_v9_0_gmc_funcs; in gmc_v9_0_set_gmc_funcs()
1219 adev->gmc.xgmi.supported = true; in gmc_v9_0_early_init()
1222 adev->gmc.xgmi.supported = true; in gmc_v9_0_early_init()
1223 adev->gmc.xgmi.connected_to_cpu = in gmc_v9_0_early_init()
1234 adev->gmc.shared_aperture_start = 0x2000000000000000ULL; in gmc_v9_0_early_init()
1235 adev->gmc.shared_aperture_end = in gmc_v9_0_early_init()
1236 adev->gmc.shared_aperture_start + (4ULL << 30) - 1; in gmc_v9_0_early_init()
1237 adev->gmc.private_aperture_start = 0x1000000000000000ULL; in gmc_v9_0_early_init()
1238 adev->gmc.private_aperture_end = in gmc_v9_0_early_init()
1239 adev->gmc.private_aperture_start + (4ULL << 30) - 1; in gmc_v9_0_early_init()
1272 return amdgpu_irq_get(adev, &adev->gmc.vm_fault, 0); in gmc_v9_0_late_init()
1284 base += adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; in gmc_v9_0_vram_gtt_location()
1285 if (adev->gmc.xgmi.connected_to_cpu) { in gmc_v9_0_vram_gtt_location()
1297 adev->gmc.xgmi.physical_node_id * adev->gmc.xgmi.node_segment_size; in gmc_v9_0_vram_gtt_location()
1314 adev->gmc.mc_vram_size = in gmc_v9_0_mc_init()
1316 adev->gmc.real_vram_size = adev->gmc.mc_vram_size; in gmc_v9_0_mc_init()
1319 !adev->gmc.xgmi.connected_to_cpu) { in gmc_v9_0_mc_init()
1324 adev->gmc.aper_base = pci_resource_start(adev->pdev, 0); in gmc_v9_0_mc_init()
1325 adev->gmc.aper_size = pci_resource_len(adev->pdev, 0); in gmc_v9_0_mc_init()
1341 (adev->gmc.xgmi.supported && in gmc_v9_0_mc_init()
1342 adev->gmc.xgmi.connected_to_cpu)) { in gmc_v9_0_mc_init()
1343 adev->gmc.aper_base = in gmc_v9_0_mc_init()
1345 adev->gmc.xgmi.physical_node_id * in gmc_v9_0_mc_init()
1346 adev->gmc.xgmi.node_segment_size; in gmc_v9_0_mc_init()
1347 adev->gmc.aper_size = adev->gmc.real_vram_size; in gmc_v9_0_mc_init()
1352 adev->gmc.visible_vram_size = adev->gmc.aper_size; in gmc_v9_0_mc_init()
1353 if (adev->gmc.visible_vram_size > adev->gmc.real_vram_size) in gmc_v9_0_mc_init()
1354 adev->gmc.visible_vram_size = adev->gmc.real_vram_size; in gmc_v9_0_mc_init()
1365 adev->gmc.gart_size = 512ULL << 20; in gmc_v9_0_mc_init()
1369 adev->gmc.gart_size = 1024ULL << 20; in gmc_v9_0_mc_init()
1373 adev->gmc.gart_size = (u64)amdgpu_gart_size << 20; in gmc_v9_0_mc_init()
1376 adev->gmc.gart_size += adev->pm.smu_prv_buffer_size; in gmc_v9_0_mc_init()
1378 gmc_v9_0_vram_gtt_location(adev, &adev->gmc); in gmc_v9_0_mc_init()
1392 if (adev->gmc.xgmi.connected_to_cpu) { in gmc_v9_0_gart_init()
1393 adev->gmc.vmid0_page_table_depth = 1; in gmc_v9_0_gart_init()
1394 adev->gmc.vmid0_page_table_block_size = 12; in gmc_v9_0_gart_init()
1396 adev->gmc.vmid0_page_table_depth = 0; in gmc_v9_0_gart_init()
1397 adev->gmc.vmid0_page_table_block_size = 0; in gmc_v9_0_gart_init()
1412 if (adev->gmc.xgmi.connected_to_cpu) { in gmc_v9_0_gart_init()
1430 adev->gmc.sdpif_register = RREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0); in gmc_v9_0_save_registers()
1442 spin_lock_init(&adev->gmc.invalidate_lock); in gmc_v9_0_sw_init()
1451 adev->gmc.vram_width = 2048; in gmc_v9_0_sw_init()
1453 adev->gmc.vram_width = vram_width; in gmc_v9_0_sw_init()
1455 if (!adev->gmc.vram_width) { in gmc_v9_0_sw_init()
1465 adev->gmc.vram_width = numchan * chansize; in gmc_v9_0_sw_init()
1468 adev->gmc.vram_type = vram_type; in gmc_v9_0_sw_init()
1469 adev->gmc.vram_vendor = vram_vendor; in gmc_v9_0_sw_init()
1479 adev->gmc.translate_further = in gmc_v9_0_sw_init()
1514 &adev->gmc.vm_fault); in gmc_v9_0_sw_init()
1520 &adev->gmc.vm_fault); in gmc_v9_0_sw_init()
1526 &adev->gmc.vm_fault); in gmc_v9_0_sw_init()
1532 !adev->gmc.xgmi.connected_to_cpu) { in gmc_v9_0_sw_init()
1535 &adev->gmc.ecc_irq); in gmc_v9_0_sw_init()
1544 adev->gmc.mc_mask = 0xffffffffffffULL; /* 48 bit MC */ in gmc_v9_0_sw_init()
1553 if (adev->gmc.xgmi.supported) { in gmc_v9_0_sw_init()
1603 amdgpu_bo_unref(&adev->gmc.pdb0_bo); in gmc_v9_0_sw_fini()
1649 WREG32_SOC15(DCE, 0, mmDCHUBBUB_SDPIF_MMIO_CNTRL_0, adev->gmc.sdpif_register); in gmc_v9_0_restore_registers()
1650 WARN_ON(adev->gmc.sdpif_register != in gmc_v9_0_restore_registers()
1664 if (adev->gmc.xgmi.connected_to_cpu) in gmc_v9_0_gart_enable()
1685 (unsigned)(adev->gmc.gart_size >> 20)); in gmc_v9_0_gart_enable()
1686 if (adev->gmc.pdb0_bo) in gmc_v9_0_gart_enable()
1688 (unsigned long long)amdgpu_bo_gpu_offset(adev->gmc.pdb0_bo)); in gmc_v9_0_gart_enable()
1764 amdgpu_irq_put(adev, &adev->gmc.ecc_irq, 0); in gmc_v9_0_hw_fini()
1765 amdgpu_irq_put(adev, &adev->gmc.vm_fault, 0); in gmc_v9_0_hw_fini()