2556 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {  in gfx_v7_0_cp_gfx_start()
3307 			adev->gfx.rlc.reg_list = spectre_rlc_save_restore_register_list;  in gfx_v7_0_rlc_init()
3308 			adev->gfx.rlc.reg_list_size =  in gfx_v7_0_rlc_init()
3311 			adev->gfx.rlc.reg_list = kalindi_rlc_save_restore_register_list;  in gfx_v7_0_rlc_init()
3312 			adev->gfx.rlc.reg_list_size =  in gfx_v7_0_rlc_init()
3316 	adev->gfx.rlc.cs_data = ci_cs_data;  in gfx_v7_0_rlc_init()
3317 	adev->gfx.rlc.cp_table_size = ALIGN(CP_ME_TABLE_SIZE * 5 * 4, 2048); /* CP JT */  in gfx_v7_0_rlc_init()
3318 	adev->gfx.rlc.cp_table_size += 64 * 1024; /* GDS */  in gfx_v7_0_rlc_init()
3320 	src_ptr = adev->gfx.rlc.reg_list;  in gfx_v7_0_rlc_init()
3321 	dws = adev->gfx.rlc.reg_list_size;  in gfx_v7_0_rlc_init()
3324 	cs_data = adev->gfx.rlc.cs_data;  in gfx_v7_0_rlc_init()
3340 	if (adev->gfx.rlc.cp_table_size) {  in gfx_v7_0_rlc_init()
3347 	if (adev->gfx.rlc.funcs->update_spm_vmid)  in gfx_v7_0_rlc_init()
3348 		adev->gfx.rlc.funcs->update_spm_vmid(adev, 0xf);  in gfx_v7_0_rlc_init()
3395 static void gfx_v7_0_update_rlc(struct amdgpu_device *adev, u32 rlc)  in gfx_v7_0_update_rlc()  argument
3400 	if (tmp != rlc)  in gfx_v7_0_update_rlc()
3401 		WREG32(mmRLC_CNTL, rlc);  in gfx_v7_0_update_rlc()
3532 	adev->gfx.rlc.funcs->stop(adev);  in gfx_v7_0_rlc_resume()
3538 	adev->gfx.rlc.funcs->reset(adev);  in gfx_v7_0_rlc_resume()
3569 	adev->gfx.rlc.funcs->start(adev);  in gfx_v7_0_rlc_resume()
3898 	if (adev->gfx.rlc.cs_data) {  in gfx_v7_0_init_gfx_cgpg()
3900 		WREG32(mmRLC_GPM_SCRATCH_DATA, upper_32_bits(adev->gfx.rlc.clear_state_gpu_addr));  in gfx_v7_0_init_gfx_cgpg()
3901 		WREG32(mmRLC_GPM_SCRATCH_DATA, lower_32_bits(adev->gfx.rlc.clear_state_gpu_addr));  in gfx_v7_0_init_gfx_cgpg()
3902 		WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.clear_state_size);  in gfx_v7_0_init_gfx_cgpg()
3908 	if (adev->gfx.rlc.reg_list) {  in gfx_v7_0_init_gfx_cgpg()
3910 		for (i = 0; i < adev->gfx.rlc.reg_list_size; i++)  in gfx_v7_0_init_gfx_cgpg()
3911 			WREG32(mmRLC_GPM_SCRATCH_DATA, adev->gfx.rlc.reg_list[i]);  in gfx_v7_0_init_gfx_cgpg()
3919 	WREG32(mmRLC_SAVE_AND_RESTORE_BASE, adev->gfx.rlc.save_restore_gpu_addr >> 8);  in gfx_v7_0_init_gfx_cgpg()
3920 	WREG32(mmRLC_JUMP_TABLE_RESTORE, adev->gfx.rlc.cp_table_gpu_addr >> 8);  in gfx_v7_0_init_gfx_cgpg()
3955 	if (adev->gfx.rlc.cs_data == NULL)  in gfx_v7_0_get_csb_size()
3963 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {  in gfx_v7_0_get_csb_size()
3988 	if (adev->gfx.rlc.cs_data == NULL)  in gfx_v7_0_get_csb_buffer()
4000 	for (sect = adev->gfx.rlc.cs_data; sect->section != NULL; ++sect) {  in gfx_v7_0_get_csb_buffer()
4249 	adev->gfx.rlc.funcs = &gfx_v7_0_rlc_funcs;  in gfx_v7_0_early_init()
4495 	r = adev->gfx.rlc.funcs->init(adev);  in gfx_v7_0_sw_init()
4559 	amdgpu_bo_free_kernel(&adev->gfx.rlc.clear_state_obj,  in gfx_v7_0_sw_fini()
4560 				&adev->gfx.rlc.clear_state_gpu_addr,  in gfx_v7_0_sw_fini()
4561 				(void **)&adev->gfx.rlc.cs_ptr);  in gfx_v7_0_sw_fini()
4562 	if (adev->gfx.rlc.cp_table_size) {  in gfx_v7_0_sw_fini()
4563 		amdgpu_bo_free_kernel(&adev->gfx.rlc.cp_table_obj,  in gfx_v7_0_sw_fini()
4564 				&adev->gfx.rlc.cp_table_gpu_addr,  in gfx_v7_0_sw_fini()
4565 				(void **)&adev->gfx.rlc.cp_table_ptr);  in gfx_v7_0_sw_fini()
4580 	adev->gfx.rlc.funcs->get_csb_buffer(adev, adev->gfx.rlc.cs_ptr);  in gfx_v7_0_hw_init()
4582 	r = adev->gfx.rlc.funcs->resume(adev);  in gfx_v7_0_hw_init()
4600 	adev->gfx.rlc.funcs->stop(adev);  in gfx_v7_0_hw_fini()
4685 		adev->gfx.rlc.funcs->stop(adev);  in gfx_v7_0_soft_reset()