Lines Matching refs:sdma_cntl
596 u32 sdma_cntl; in si_dma_set_trap_irq_state() local
602 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
603 sdma_cntl &= ~TRAP_ENABLE; in si_dma_set_trap_irq_state()
604 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
607 sdma_cntl = RREG32(DMA_CNTL + DMA0_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
608 sdma_cntl |= TRAP_ENABLE; in si_dma_set_trap_irq_state()
609 WREG32(DMA_CNTL + DMA0_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
618 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
619 sdma_cntl &= ~TRAP_ENABLE; in si_dma_set_trap_irq_state()
620 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()
623 sdma_cntl = RREG32(DMA_CNTL + DMA1_REGISTER_OFFSET); in si_dma_set_trap_irq_state()
624 sdma_cntl |= TRAP_ENABLE; in si_dma_set_trap_irq_state()
625 WREG32(DMA_CNTL + DMA1_REGISTER_OFFSET, sdma_cntl); in si_dma_set_trap_irq_state()