Lines Matching refs:reset_req

748     u_sc_pcie_hilink_pcs_reset_req reset_req;
753 reset_req.UInt32 = 0;
754 reset_req.UInt32 = reset_req.UInt32 | (0x1 << PortIndexInSicl);
755 …ubctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32);
756 …_subctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_APB_RESET_REQ_REG, reset_req.UInt32);
758 reset_req.UInt32 = 0;
759 reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * PortIndexInSicl));
760 …_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32);
769 reset_req.UInt32 = 0;
770 reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
771 …rite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_REQ_REG, reset_req.UInt32);
773 reset_req.UInt32 = 0;
774 reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
775 …cie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_REQ_REG, reset_req.UInt32);
784 u_sc_pcie_hilink_pcs_reset_req reset_req;
789 reset_req.UInt32 = 0;
790 reset_req.UInt32 = reset_req.UInt32 | (0x1 << PortIndexInSicl);
791 RegWrite(pcie_subctrl_base_1610[HostBridgeNum][Port] + 0xacc, reset_req.UInt32);
792 …bctrl_base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32);
794 reset_req.UInt32 = 0;
795 reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * PortIndexInSicl));
796 …base_1610[HostBridgeNum][Port] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32);
805 reset_req.UInt32 = 0;
806 reset_req.UInt32 = reset_req.UInt32 | (0x1 << Port);
807 …ite(pcie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCS_LOCAL_RESET_DREQ_REG, reset_req.UInt32);
809 reset_req.UInt32 = 0;
810 reset_req.UInt32 = reset_req.UInt32 | (0xFF << (8 * Port));
811 …ie_subctrl_base[HostBridgeNum] + PCIE_SUBCTRL_SC_PCIE_HILINK_PCS_RESET_DREQ_REG, reset_req.UInt32);