26 struct mxc_ccm_reg *imx_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;  variable
33 	reg = __raw_readl(&imx_ccm->CCGR2);  in enable_ocotp_clk()
38 	__raw_writel(reg, &imx_ccm->CCGR2);  in enable_ocotp_clk()
46 	clrbits_le32(&imx_ccm->CCGR4,  in setup_gpmi_io_clk()
54 	clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);  in setup_gpmi_io_clk()
56 	clrsetbits_le32(&imx_ccm->cs2cdr,  in setup_gpmi_io_clk()
62 	setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK);  in setup_gpmi_io_clk()
64 	clrbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);  in setup_gpmi_io_clk()
66 	clrsetbits_le32(&imx_ccm->cs2cdr,  in setup_gpmi_io_clk()
72 	setbits_le32(&imx_ccm->CCGR2, MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK);  in setup_gpmi_io_clk()
74 	setbits_le32(&imx_ccm->CCGR4,  in setup_gpmi_io_clk()
87 	reg = __raw_readl(&imx_ccm->CCGR6);  in enable_usboh3_clk()
92 	__raw_writel(reg, &imx_ccm->CCGR6);  in enable_usboh3_clk()
103 		addr = &imx_ccm->CCGR0;  in enable_enet_clk()
106 		addr = &imx_ccm->CCGR3;  in enable_enet_clk()
109 		addr = &imx_ccm->CCGR1;  in enable_enet_clk()
130 		setbits_le32(&imx_ccm->CCGR5, mask);  in enable_uart_clk()
132 		clrbits_le32(&imx_ccm->CCGR5, mask);  in enable_uart_clk()
146 		setbits_le32(&imx_ccm->CCGR6, mask);  in enable_usdhc_clk()
148 		clrbits_le32(&imx_ccm->CCGR6, mask);  in enable_usdhc_clk()
168 		reg = __raw_readl(&imx_ccm->CCGR2);  in enable_i2c_clk()
173 		__raw_writel(reg, &imx_ccm->CCGR2);  in enable_i2c_clk()
179 			addr = &imx_ccm->CCGR6;  in enable_i2c_clk()
182 			addr = &imx_ccm->CCGR1;  in enable_i2c_clk()
205 	reg = __raw_readl(&imx_ccm->CCGR1);  in enable_spi_clk()
210 	__raw_writel(reg, &imx_ccm->CCGR1);  in enable_spi_clk()
219 		div = __raw_readl(&imx_ccm->analog_pll_sys);  in decode_pll()
224 		div = __raw_readl(&imx_ccm->analog_pll_528);  in decode_pll()
229 		div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl);  in decode_pll()
234 		div = __raw_readl(&imx_ccm->analog_pll_enet);  in decode_pll()
239 		div = __raw_readl(&imx_ccm->analog_pll_audio);  in decode_pll()
245 		pll_num = __raw_readl(&imx_ccm->analog_pll_audio_num);  in decode_pll()
246 		pll_denom = __raw_readl(&imx_ccm->analog_pll_audio_denom);  in decode_pll()
258 		div = __raw_readl(&imx_ccm->analog_pll_video);  in decode_pll()
264 		pll_num = __raw_readl(&imx_ccm->analog_pll_video_num);  in decode_pll()
265 		pll_denom = __raw_readl(&imx_ccm->analog_pll_video_denom);  in decode_pll()
294 		div = __raw_readl(&imx_ccm->analog_pfd_528);  in mxc_get_pll_pfd()
298 		div = __raw_readl(&imx_ccm->analog_pfd_480);  in mxc_get_pll_pfd()
314 	reg = __raw_readl(&imx_ccm->cacrr);  in get_mcu_main_clk()
326 	reg = __raw_readl(&imx_ccm->cbcdr);  in get_periph_clk()
330 		reg = __raw_readl(&imx_ccm->cbcmr);  in get_periph_clk()
346 		reg = __raw_readl(&imx_ccm->cbcmr);  in get_periph_clk()
376 	reg = __raw_readl(&imx_ccm->cbcdr);  in get_ipg_clk()
387 	reg = __raw_readl(&imx_ccm->cscmr1);  in get_ipg_per_clk()
403 	reg = __raw_readl(&imx_ccm->cscdr1);  in get_uart_clk()
421 	reg = __raw_readl(&imx_ccm->cscdr2);  in get_cspi_clk()
437 	u32 cbcdr =  __raw_readl(&imx_ccm->cbcdr);  in get_axi_clk()
457 	cscmr1 =  __raw_readl(&imx_ccm->cscmr1);  in get_emi_slow_clk()
483 	u32 cbcmr = __raw_readl(&imx_ccm->cbcmr);  in get_mmdc_ch0_clk()
484 	u32 cbcdr = __raw_readl(&imx_ccm->cbcdr);  in get_mmdc_ch0_clk()
526 				pmu_misc2_audio_div = PMU_MISC2_AUDIO_DIV(__raw_readl(&imx_ccm->pmu_misc2));  in get_mmdc_ch0_clk()
567 	       &imx_ccm->analog_pll_video_clr);  in enable_pll_video()
574 		       &imx_ccm->analog_pll_video_set);  in enable_pll_video()
579 		       &imx_ccm->analog_pll_video_set);  in enable_pll_video()
584 		       &imx_ccm->analog_pll_video_set);  in enable_pll_video()
592 	       &imx_ccm->analog_pll_video_num);  in enable_pll_video()
594 	       &imx_ccm->analog_pll_video_denom);  in enable_pll_video()
600 		reg = readl(&imx_ccm->analog_pll_video);  in enable_pll_video()
604 			       &imx_ccm->analog_pll_video_set);  in enable_pll_video()
640 			reg = readl(&imx_ccm->cscdr2);  in mxs_set_lcdclk()
648 		reg = readl(&imx_ccm->cscdr2);  in mxs_set_lcdclk()
718 			clrsetbits_le32(&imx_ccm->cscdr2,  in mxs_set_lcdclk()
726 			clrsetbits_le32(&imx_ccm->cbcmr,  in mxs_set_lcdclk()
732 			clrsetbits_le32(&imx_ccm->cscdr2,  in mxs_set_lcdclk()
740 			clrsetbits_le32(&imx_ccm->cscmr1,  in mxs_set_lcdclk()
754 		clrsetbits_le32(&imx_ccm->cscdr2,  in mxs_set_lcdclk()
762 		clrsetbits_le32(&imx_ccm->cscmr1,  in mxs_set_lcdclk()
805 		reg = readl(&imx_ccm->CCGR3);  in enable_lcdif_clock()
808 		writel(reg, &imx_ccm->CCGR3);  in enable_lcdif_clock()
811 			reg = readl(&imx_ccm->cscdr3);  in enable_lcdif_clock()
814 			writel(reg, &imx_ccm->cscdr3);  in enable_lcdif_clock()
816 			reg = readl(&imx_ccm->CCGR3);  in enable_lcdif_clock()
819 			writel(reg, &imx_ccm->CCGR3);  in enable_lcdif_clock()
828 	reg = readl(&imx_ccm->CCGR3);  in enable_lcdif_clock()
830 	writel(reg, &imx_ccm->CCGR3);  in enable_lcdif_clock()
832 	reg = readl(&imx_ccm->CCGR2);  in enable_lcdif_clock()
834 	writel(reg, &imx_ccm->CCGR2);  in enable_lcdif_clock()
838 		reg = readl(&imx_ccm->cscdr2);  in enable_lcdif_clock()
840 		writel(reg, &imx_ccm->cscdr2);  in enable_lcdif_clock()
843 		reg = readl(&imx_ccm->CCGR3);  in enable_lcdif_clock()
845 		writel(reg, &imx_ccm->CCGR3);  in enable_lcdif_clock()
847 		reg = readl(&imx_ccm->CCGR2);  in enable_lcdif_clock()
849 		writel(reg, &imx_ccm->CCGR2);  in enable_lcdif_clock()
865 		clrbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);  in enable_qspi_clk()
868 		reg = readl(&imx_ccm->cscmr1);  in enable_qspi_clk()
873 		writel(reg, &imx_ccm->cscmr1);  in enable_qspi_clk()
876 		setbits_le32(&imx_ccm->CCGR3, MXC_CCM_CCGR3_QSPI1_MASK);  in enable_qspi_clk()
884 		clrbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |  in enable_qspi_clk()
888 		reg = readl(&imx_ccm->cs2cdr);  in enable_qspi_clk()
894 		writel(reg, &imx_ccm->cs2cdr);  in enable_qspi_clk()
897 		setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_QSPI2_ENFC_MASK |  in enable_qspi_clk()
955 	reg = readl(&imx_ccm->CCGR3);  in enable_fec_anatop_clock()
957 	writel(reg, &imx_ccm->CCGR3);  in enable_fec_anatop_clock()
963 	reg = readl(&imx_ccm->chsccdr);  in enable_fec_anatop_clock()
972 	writel(reg, &imx_ccm->chsccdr);  in enable_fec_anatop_clock()
975 	reg = readl(&imx_ccm->CCGR3);  in enable_fec_anatop_clock()
977 	writel(reg, &imx_ccm->CCGR3);  in enable_fec_anatop_clock()
986 	u32 cscmr1 = __raw_readl(&imx_ccm->cscmr1);  in get_usdhc_clk()
987 	u32 cscdr1 = __raw_readl(&imx_ccm->cscdr1);  in get_usdhc_clk()
1049 	struct mxc_ccm_reg *const imx_ccm  in enable_enet_pll()  local
1055 	reg = readl(&imx_ccm->analog_pll_enet);  in enable_enet_pll()
1057 	writel(reg, &imx_ccm->analog_pll_enet);  in enable_enet_pll()
1060 		if (readl(&imx_ccm->analog_pll_enet) & BM_ANADIG_PLL_SYS_LOCK)  in enable_enet_pll()
1066 	writel(reg, &imx_ccm->analog_pll_enet);  in enable_enet_pll()
1068 	writel(reg, &imx_ccm->analog_pll_enet);  in enable_enet_pll()
1076 	struct mxc_ccm_reg *const imx_ccm =  in ungate_sata_clock()  local
1080 	setbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);  in ungate_sata_clock()
1091 	struct mxc_ccm_reg *const imx_ccm =  in disable_sata_clock()  local
1094 	clrbits_le32(&imx_ccm->CCGR5, MXC_CCM_CCGR5_SATA_MASK);  in disable_sata_clock()
1101 	struct mxc_ccm_reg *const imx_ccm =  in ungate_pcie_clock()  local
1105 	setbits_le32(&imx_ccm->CCGR4, MXC_CCM_CCGR4_PCIE_MASK);  in ungate_pcie_clock()
1164 		reg = __raw_readl(&imx_ccm->CCGR0);  in hab_caam_clock_enable()
1169 		__raw_writel(reg, &imx_ccm->CCGR0);  in hab_caam_clock_enable()
1172 		reg = __raw_readl(&imx_ccm->CCGR0);  in hab_caam_clock_enable()
1181 		__raw_writel(reg, &imx_ccm->CCGR0);  in hab_caam_clock_enable()
1185 	reg = __raw_readl(&imx_ccm->CCGR6);  in hab_caam_clock_enable()
1190 	__raw_writel(reg, &imx_ccm->CCGR6);  in hab_caam_clock_enable()
1229 	reg = __raw_readl(&imx_ccm->CCGR6);  in enable_eim_clk()
1234 	__raw_writel(reg, &imx_ccm->CCGR6);  in enable_eim_clk()