Lines Matching refs:reg
71 u32 reg; in wait_refresh_op_complete() local
75 reg = reg_read(REG_SDRAM_OPERATION_ADDR) & in wait_refresh_op_complete()
77 } while (reg); /* Wait for '0' */ in wait_refresh_op_complete()
117 u32 reg, freq_par, tmp; in ddr3_dfs_high_2_low() local
133 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
135 reg |= (1 << REG_DFS_DLLNEXTSTATE_OFFS); in ddr3_dfs_high_2_low()
136 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
142 reg = reg_read(REG_METAL_MASK_ADDR); in ddr3_dfs_high_2_low()
144 reg &= ~(1 << REG_METAL_MASK_RETRY_OFFS); in ddr3_dfs_high_2_low()
146 dfs_reg_write(REG_METAL_MASK_ADDR, reg); in ddr3_dfs_high_2_low()
149 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
150 reg |= (1 << REG_DFS_BLOCK_OFFS); /* [1] - DfsBlock - Enable */ in ddr3_dfs_high_2_low()
151 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
159 reg = (0x9 & REG_SDRAM_OPERATION_CWA_RC_MASK) << in ddr3_dfs_high_2_low()
165 reg |= ((0 & REG_SDRAM_OPERATION_CWA_DATA_MASK) << in ddr3_dfs_high_2_low()
172 reg |= (0 << REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS); in ddr3_dfs_high_2_low()
175 reg |= (REG_SDRAM_OPERATION_CMD_CWA & in ddr3_dfs_high_2_low()
179 dfs_reg_write(REG_SDRAM_OPERATION_ADDR, reg); in ddr3_dfs_high_2_low()
183 reg = reg_read(REG_SDRAM_OPERATION_ADDR) & in ddr3_dfs_high_2_low()
185 } while (reg); in ddr3_dfs_high_2_low()
188 reg = reg_read(REG_REGISTERED_DRAM_CTRL_ADDR); in ddr3_dfs_high_2_low()
190 reg &= ~(1 << REG_REGISTERED_DRAM_CTRL_SR_FLOAT_OFFS); in ddr3_dfs_high_2_low()
192 dfs_reg_write(REG_REGISTERED_DRAM_CTRL_ADDR, reg); in ddr3_dfs_high_2_low()
198 reg = reg_read(REG_DDR3_MR1_CS_ADDR + in ddr3_dfs_high_2_low()
200 reg &= REG_DDR3_MR1_RTT_MASK; in ddr3_dfs_high_2_low()
202 (cs << MR_CS_ADDR_OFFS), reg); in ddr3_dfs_high_2_low()
207 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
208 reg |= (1 << REG_DFS_SR_OFFS); /* [2] - DfsSR - Enable */ in ddr3_dfs_high_2_low()
209 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
213 reg = ((reg_read(REG_DFS_ADDR)) & (1 << REG_DFS_ATSR_OFFS)); in ddr3_dfs_high_2_low()
214 } while (reg == 0x0); /* 0x1528 [3] - DfsAtSR - Wait for '1' */ in ddr3_dfs_high_2_low()
220 reg = reg_read(CPU_PLL_CLOCK_DIVIDER_CNTRL0); in ddr3_dfs_high_2_low()
221 reg &= CPU_PLL_CLOCK_DIVIDER_CNTRL0_MASK; in ddr3_dfs_high_2_low()
223 dfs_reg_write(CPU_PLL_CLOCK_DIVIDER_CNTRL0, (reg + 0xFF)); in ddr3_dfs_high_2_low()
226 reg = reg_read(CPU_PLL_CNTRL0); in ddr3_dfs_high_2_low()
227 reg &= CPU_PLL_CNTRL0_RELOAD_SMOOTH_MASK; in ddr3_dfs_high_2_low()
230 (reg + (2 << CPU_PLL_CNTRL0_RELOAD_SMOOTH_OFFS))); in ddr3_dfs_high_2_low()
233 reg = reg_read(CPU_PLL_CNTRL0); in ddr3_dfs_high_2_low()
234 reg &= CPU_PLL_CNTRL0_RELAX_EN_MASK; in ddr3_dfs_high_2_low()
237 (reg + (2 << CPU_PLL_CNTRL0_RELAX_EN_OFFS))); in ddr3_dfs_high_2_low()
240 reg = reg_read(CPU_PLL_CLOCK_DIVIDER_CNTRL1); in ddr3_dfs_high_2_low()
245 reg &= CPU_PLL_CLOCK_DIVIDER_CNTRL1_MASK; in ddr3_dfs_high_2_low()
246 reg |= (freq_par << 8); /* full Integer ratio from PLL-out to ddr-clk */ in ddr3_dfs_high_2_low()
247 dfs_reg_write(CPU_PLL_CLOCK_DIVIDER_CNTRL1, reg); in ddr3_dfs_high_2_low()
250 reg = reg_read(CPU_PLL_CLOCK_DIVIDER_CNTRL0); in ddr3_dfs_high_2_low()
251 reg &= CPU_PLL_CLOCK_RELOAD_RATIO_MASK; in ddr3_dfs_high_2_low()
254 (reg + (1 << CPU_PLL_CLOCK_RELOAD_RATIO_OFFS))); in ddr3_dfs_high_2_low()
259 reg = reg_read(CPU_PLL_CLOCK_DIVIDER_CNTRL0); in ddr3_dfs_high_2_low()
260 reg &= CPU_PLL_CLOCK_RELOAD_RATIO_MASK; in ddr3_dfs_high_2_low()
262 dfs_reg_write(CPU_PLL_CLOCK_DIVIDER_CNTRL0, reg); in ddr3_dfs_high_2_low()
272 reg = 0x0000FDFF; in ddr3_dfs_high_2_low()
274 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_high_2_low()
280 reg = 0x0000FF00; in ddr3_dfs_high_2_low()
282 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_1_ADDR, reg); in ddr3_dfs_high_2_low()
284 reg = reg_read(REG_CPU_DIV_CLK_CTRL_2_ADDR) & in ddr3_dfs_high_2_low()
288 reg |= (freq_par << REG_CPU_DIV_CLK_CTRL_3_FREQ_OFFS); in ddr3_dfs_high_2_low()
290 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_2_ADDR, reg); in ddr3_dfs_high_2_low()
299 reg = 0x000FFF02; in ddr3_dfs_high_2_low()
300 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_4_ADDR, reg); in ddr3_dfs_high_2_low()
314 reg = 0x0102FDFF; in ddr3_dfs_high_2_low()
316 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_high_2_low()
325 reg = (reg_read(REG_CPU_DIV_CLK_STATUS_0_ADDR)) & in ddr3_dfs_high_2_low()
327 } while (reg == 0); in ddr3_dfs_high_2_low()
333 reg = 0x000000FF; in ddr3_dfs_high_2_low()
335 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_high_2_low()
342 reg = reg_read(REG_DRAM_INIT_CTRL_STATUS_ADDR); in ddr3_dfs_high_2_low()
344 reg |= (1 << REG_DRAM_INIT_CTRL_TRN_CLK_OFFS); in ddr3_dfs_high_2_low()
346 dfs_reg_write(REG_DRAM_INIT_CTRL_STATUS_ADDR, reg); in ddr3_dfs_high_2_low()
351 reg = reg_read(REG_DDR_IO_ADDR) & ~(1 << REG_DDR_IO_CLK_RATIO_OFFS); in ddr3_dfs_high_2_low()
352 dfs_reg_write(REG_DDR_IO_ADDR, reg); /* 0x1524 - DDR IO Register */ in ddr3_dfs_high_2_low()
355 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR); in ddr3_dfs_high_2_low()
357 reg &= ~(REG_DUNIT_CTRL_LOW_2T_MASK << REG_DUNIT_CTRL_LOW_2T_OFFS); in ddr3_dfs_high_2_low()
359 dfs_reg_write(REG_DUNIT_CTRL_LOW_ADDR, reg); in ddr3_dfs_high_2_low()
362 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
363 reg &= ~(REG_DFS_CL_NEXT_STATE_MASK << REG_DFS_CL_NEXT_STATE_OFFS); in ddr3_dfs_high_2_low()
364 reg &= ~(REG_DFS_CWL_NEXT_STATE_MASK << REG_DFS_CWL_NEXT_STATE_OFFS); in ddr3_dfs_high_2_low()
366 reg |= (0x4 << REG_DFS_CL_NEXT_STATE_OFFS); in ddr3_dfs_high_2_low()
368 reg |= (0x1 << REG_DFS_CWL_NEXT_STATE_OFFS); in ddr3_dfs_high_2_low()
369 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
373 reg = (reg_read(REG_PHY_LOCK_STATUS_ADDR)) & in ddr3_dfs_high_2_low()
376 } while (reg != REG_PHY_LOCK_APLL_ADLL_STATUS_MASK); in ddr3_dfs_high_2_low()
379 reg = (reg_read(REG_SDRAM_CONFIG_ADDR) & REG_SDRAM_CONFIG_MASK); in ddr3_dfs_high_2_low()
382 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_high_2_low()
388 reg = (reg_read(REG_SDRAM_CONFIG_ADDR) | ~REG_SDRAM_CONFIG_MASK); in ddr3_dfs_high_2_low()
391 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_high_2_low()
399 reg = (0xA & REG_SDRAM_OPERATION_CWA_RC_MASK) << in ddr3_dfs_high_2_low()
406 reg |= ((0x0 & REG_SDRAM_OPERATION_CWA_DATA_MASK) << in ddr3_dfs_high_2_low()
410 reg |= (0x1 << REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS); in ddr3_dfs_high_2_low()
413 reg |= (REG_SDRAM_OPERATION_CMD_CWA & in ddr3_dfs_high_2_low()
417 dfs_reg_write(REG_SDRAM_OPERATION_ADDR, reg); in ddr3_dfs_high_2_low()
421 reg = reg_read(REG_SDRAM_OPERATION_ADDR) & in ddr3_dfs_high_2_low()
423 } while (reg); in ddr3_dfs_high_2_low()
428 reg = (reg_read(REG_DFS_ADDR) & ~(1 << REG_DFS_SR_OFFS)); in ddr3_dfs_high_2_low()
429 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
436 reg = ((reg_read(REG_DFS_ADDR)) & (1 << REG_DFS_ATSR_OFFS)); in ddr3_dfs_high_2_low()
437 } while (reg); /* Wait for '0' */ in ddr3_dfs_high_2_low()
441 reg = REG_SDRAM_OPERATION_CMD_RFRS; in ddr3_dfs_high_2_low()
444 reg &= ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_dfs_high_2_low()
448 dfs_reg_write(REG_SDRAM_OPERATION_ADDR, reg); in ddr3_dfs_high_2_low()
454 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_high_2_low()
455 reg &= ~(1 << REG_DFS_BLOCK_OFFS); /* [1] - DfsBlock - Disable */ in ddr3_dfs_high_2_low()
456 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
462 reg = reg_read(REG_METAL_MASK_ADDR); in ddr3_dfs_high_2_low()
464 reg |= (1 << REG_METAL_MASK_RETRY_OFFS); in ddr3_dfs_high_2_low()
466 dfs_reg_write(REG_METAL_MASK_ADDR, reg); in ddr3_dfs_high_2_low()
471 reg = reg_read(REG_DDR3_MR0_CS_ADDR + in ddr3_dfs_high_2_low()
475 reg |= ((tmp & 0x1) << REG_DDR3_MR0_CL_OFFS); in ddr3_dfs_high_2_low()
476 reg |= ((tmp & 0xE) << REG_DDR3_MR0_CL_HIGH_OFFS); in ddr3_dfs_high_2_low()
478 (cs << MR_CS_ADDR_OFFS), reg); in ddr3_dfs_high_2_low()
481 reg = reg_read(REG_DDR3_MR2_CS_ADDR + in ddr3_dfs_high_2_low()
485 reg |= ((0x1) << REG_DDR3_MR2_CWL_OFFS); in ddr3_dfs_high_2_low()
487 (cs << MR_CS_ADDR_OFFS), reg); in ddr3_dfs_high_2_low()
498 u32 reg, freq_par; in ddr3_dfs_high_2_low()
507 reg = 0x0000FF00; in ddr3_dfs_high_2_low()
509 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_1_ADDR, reg); in ddr3_dfs_high_2_low()
512 reg = reg_read(REG_ODPG_CNTRL_ADDR); in ddr3_dfs_high_2_low()
514 reg |= (1 << REG_ODPG_CNTRL_OFFS); in ddr3_dfs_high_2_low()
515 dfs_reg_write(REG_ODPG_CNTRL_ADDR, reg); in ddr3_dfs_high_2_low()
518 reg = reg_read(REG_PHY_LOCK_MASK_ADDR); in ddr3_dfs_high_2_low()
519 reg &= REG_PHY_LOCK_MASK_MASK; /* [11:0] = 0 */ in ddr3_dfs_high_2_low()
520 dfs_reg_write(REG_PHY_LOCK_MASK_ADDR, reg); in ddr3_dfs_high_2_low()
522 reg = reg_read(REG_DFS_ADDR); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
525 reg &= ~0x10; /* [4] - Enable reconfig MR registers after DFS_ERG */ in ddr3_dfs_high_2_low()
526 reg |= 0x1; /* [0] - DRAM DLL disabled after DFS */ in ddr3_dfs_high_2_low()
528 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
530 reg = reg_read(REG_METAL_MASK_ADDR) & ~(1 << 0); /* [0] - disable */ in ddr3_dfs_high_2_low()
532 dfs_reg_write(REG_METAL_MASK_ADDR, reg); in ddr3_dfs_high_2_low()
535 reg = reg_read(REG_DFS_ADDR) | (1 << REG_DFS_BLOCK_OFFS); in ddr3_dfs_high_2_low()
536 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
539 reg = reg_read(REG_DFS_ADDR) | (1 << REG_DFS_SR_OFFS); in ddr3_dfs_high_2_low()
540 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
548 reg = reg_read(REG_DFS_ADDR) & (1 << REG_DFS_ATSR_OFFS); in ddr3_dfs_high_2_low()
549 } while (reg == 0x0); /* Wait for '1' */ in ddr3_dfs_high_2_low()
556 reg = (reg_read(REG_PHY_LOCK_MASK_ADDR) & REG_PHY_LOCK_MASK_MASK); in ddr3_dfs_high_2_low()
558 dfs_reg_write(REG_PHY_LOCK_MASK_ADDR, reg); in ddr3_dfs_high_2_low()
568 reg = 0x0000FDFF; in ddr3_dfs_high_2_low()
570 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_high_2_low()
575 reg = 0x0000FF00; in ddr3_dfs_high_2_low()
577 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_1_ADDR, reg); in ddr3_dfs_high_2_low()
579 reg = reg_read(REG_CPU_DIV_CLK_CTRL_3_ADDR) & in ddr3_dfs_high_2_low()
582 reg |= (freq_par << REG_CPU_DIV_CLK_CTRL_3_FREQ_OFFS); in ddr3_dfs_high_2_low()
584 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_3_ADDR, reg); in ddr3_dfs_high_2_low()
593 reg = 0x000FFF02; in ddr3_dfs_high_2_low()
594 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_4_ADDR, reg); in ddr3_dfs_high_2_low()
608 reg = 0x0102FDFF; in ddr3_dfs_high_2_low()
610 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_high_2_low()
619 reg = (reg_read(REG_CPU_DIV_CLK_STATUS_0_ADDR)) & in ddr3_dfs_high_2_low()
621 } while (reg == 0); in ddr3_dfs_high_2_low()
627 reg = 0x000000FF; in ddr3_dfs_high_2_low()
629 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_high_2_low()
634 reg = 0x20050000; in ddr3_dfs_high_2_low()
636 dfs_reg_write(REG_DRAM_INIT_CTRL_STATUS_ADDR, reg); in ddr3_dfs_high_2_low()
638 reg = reg_read(REG_DDR_IO_ADDR) & ~(1 << REG_DDR_IO_CLK_RATIO_OFFS); in ddr3_dfs_high_2_low()
640 dfs_reg_write(REG_DDR_IO_ADDR, reg); /* 0x1524 - DDR IO Regist */ in ddr3_dfs_high_2_low()
642 reg = reg_read(REG_DRAM_PHY_CONFIG_ADDR) & REG_DRAM_PHY_CONFIG_MASK; in ddr3_dfs_high_2_low()
645 dfs_reg_write(REG_DRAM_PHY_CONFIG_ADDR, reg); in ddr3_dfs_high_2_low()
647 reg = (reg_read(REG_DRAM_PHY_CONFIG_ADDR) | ~REG_DRAM_PHY_CONFIG_MASK); in ddr3_dfs_high_2_low()
650 dfs_reg_write(REG_DRAM_PHY_CONFIG_ADDR, reg); in ddr3_dfs_high_2_low()
655 reg = (reg_read(REG_DUNIT_CTRL_LOW_ADDR) & 0xFFFFFFE7); in ddr3_dfs_high_2_low()
656 dfs_reg_write(REG_DUNIT_CTRL_LOW_ADDR, reg); in ddr3_dfs_high_2_low()
660 reg = (reg_read(REG_PHY_LOCK_STATUS_ADDR)) & in ddr3_dfs_high_2_low()
662 } while (reg != REG_PHY_LOCK_STATUS_LOCK_MASK); /* Wait for '0xFFF' */ in ddr3_dfs_high_2_low()
664 reg = (reg_read(REG_SDRAM_CONFIG_ADDR) & REG_SDRAM_CONFIG_MASK); in ddr3_dfs_high_2_low()
667 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_high_2_low()
669 reg = reg_read(REG_SDRAM_CONFIG_ADDR) | ~REG_SDRAM_CONFIG_MASK; in ddr3_dfs_high_2_low()
672 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_high_2_low()
682 reg = reg_read(REG_DDR3_MR0_ADDR); in ddr3_dfs_high_2_low()
683 reg &= ~0x74; /* CL [3:0]; [6:4],[2] */ in ddr3_dfs_high_2_low()
684 reg |= (1 << 5); /* CL = 4, CAS is 6 */ in ddr3_dfs_high_2_low()
685 dfs_reg_write(REG_DDR3_MR0_ADDR, reg); in ddr3_dfs_high_2_low()
686 reg = REG_SDRAM_OPERATION_CMD_MR0 & in ddr3_dfs_high_2_low()
689 dfs_reg_write(REG_SDRAM_OPERATION_ADDR, reg); in ddr3_dfs_high_2_low()
694 reg = reg_read(REG_DDR3_MR2_ADDR); in ddr3_dfs_high_2_low()
695 reg &= ~0x38; /* CWL [5:3] */ in ddr3_dfs_high_2_low()
696 reg |= (1 << 3); /* CWL = 1, CWL is 6 */ in ddr3_dfs_high_2_low()
697 dfs_reg_write(REG_DDR3_MR2_ADDR, reg); in ddr3_dfs_high_2_low()
699 reg = REG_SDRAM_OPERATION_CMD_MR2 & in ddr3_dfs_high_2_low()
702 dfs_reg_write(REG_SDRAM_OPERATION_ADDR, reg); in ddr3_dfs_high_2_low()
708 reg = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in ddr3_dfs_high_2_low()
709 reg &= ~(REG_READ_DATA_SAMPLE_DELAYS_MASK << in ddr3_dfs_high_2_low()
711 reg |= (5 << (REG_READ_DATA_SAMPLE_DELAYS_OFFS * cs)); in ddr3_dfs_high_2_low()
712 dfs_reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, reg); in ddr3_dfs_high_2_low()
715 reg = reg_read(REG_READ_DATA_READY_DELAYS_ADDR); in ddr3_dfs_high_2_low()
716 reg &= ~(REG_READ_DATA_READY_DELAYS_MASK << in ddr3_dfs_high_2_low()
718 reg |= ((6) << (REG_READ_DATA_READY_DELAYS_OFFS * cs)); in ddr3_dfs_high_2_low()
719 dfs_reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg); in ddr3_dfs_high_2_low()
724 reg = reg_read(REG_DFS_ADDR) & ~(1 << REG_DFS_SR_OFFS); in ddr3_dfs_high_2_low()
725 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
728 reg = reg_read(REG_DFS_ADDR) & ~(1 << REG_DFS_BLOCK_OFFS); in ddr3_dfs_high_2_low()
729 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_high_2_low()
737 reg = reg_read(REG_DFS_ADDR) & (1 << REG_DFS_ATSR_OFFS); in ddr3_dfs_high_2_low()
738 } while (reg); /* Wait for '1' */ in ddr3_dfs_high_2_low()
740 reg = (reg_read(REG_METAL_MASK_ADDR) | (1 << 0)); in ddr3_dfs_high_2_low()
743 dfs_reg_write(REG_METAL_MASK_ADDR, reg); in ddr3_dfs_high_2_low()
746 reg = reg_read(REG_ODPG_CNTRL_ADDR); in ddr3_dfs_high_2_low()
747 reg &= ~(1 << REG_ODPG_CNTRL_OFFS); /* [21] = 0 */ in ddr3_dfs_high_2_low()
748 dfs_reg_write(REG_ODPG_CNTRL_ADDR, reg); in ddr3_dfs_high_2_low()
751 reg = reg_read(REG_PHY_LOCK_MASK_ADDR); in ddr3_dfs_high_2_low()
752 reg |= ~REG_PHY_LOCK_MASK_MASK; /* [11:0] = FFF */ in ddr3_dfs_high_2_low()
753 dfs_reg_write(REG_PHY_LOCK_MASK_ADDR, reg); in ddr3_dfs_high_2_low()
773 u32 reg, freq_par, tmp; in ddr3_dfs_low_2_high() local
789 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_low_2_high()
791 reg &= ~(1 << REG_DFS_DLLNEXTSTATE_OFFS); in ddr3_dfs_low_2_high()
792 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
798 reg = reg_read(REG_METAL_MASK_ADDR); in ddr3_dfs_low_2_high()
800 reg &= ~(1 << REG_METAL_MASK_RETRY_OFFS); in ddr3_dfs_low_2_high()
802 dfs_reg_write(REG_METAL_MASK_ADDR, reg); in ddr3_dfs_low_2_high()
805 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_low_2_high()
806 reg |= (1 << REG_DFS_BLOCK_OFFS); /* [1] - DfsBlock - Enable */ in ddr3_dfs_low_2_high()
807 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
810 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_low_2_high()
811 reg |= (1 << REG_DFS_SR_OFFS); /* [2] - DfsSR - Enable */ in ddr3_dfs_low_2_high()
812 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
816 reg = ((reg_read(REG_DFS_ADDR)) & (1 << REG_DFS_ATSR_OFFS)); in ddr3_dfs_low_2_high()
817 } while (reg == 0x0); /* 0x1528 [3] - DfsAtSR - Wait for '1' */ in ddr3_dfs_low_2_high()
823 reg = reg_read(CPU_PLL_CLOCK_DIVIDER_CNTRL0); in ddr3_dfs_low_2_high()
824 reg &= CPU_PLL_CLOCK_DIVIDER_CNTRL0_MASK; in ddr3_dfs_low_2_high()
826 dfs_reg_write(CPU_PLL_CLOCK_DIVIDER_CNTRL0, (reg + 0xFF)); in ddr3_dfs_low_2_high()
829 reg = reg_read(CPU_PLL_CNTRL0); in ddr3_dfs_low_2_high()
830 reg &= CPU_PLL_CNTRL0_RELOAD_SMOOTH_MASK; in ddr3_dfs_low_2_high()
833 reg + (2 << CPU_PLL_CNTRL0_RELOAD_SMOOTH_OFFS)); in ddr3_dfs_low_2_high()
836 reg = reg_read(CPU_PLL_CNTRL0); in ddr3_dfs_low_2_high()
837 reg &= CPU_PLL_CNTRL0_RELAX_EN_MASK; in ddr3_dfs_low_2_high()
840 reg + (2 << CPU_PLL_CNTRL0_RELAX_EN_OFFS)); in ddr3_dfs_low_2_high()
843 reg = reg_read(CPU_PLL_CLOCK_DIVIDER_CNTRL1); in ddr3_dfs_low_2_high()
848 reg &= CPU_PLL_CLOCK_DIVIDER_CNTRL1_MASK; in ddr3_dfs_low_2_high()
849 reg |= (freq_par << 8); /* full Integer ratio from PLL-out to ddr-clk */ in ddr3_dfs_low_2_high()
850 dfs_reg_write(CPU_PLL_CLOCK_DIVIDER_CNTRL1, reg); in ddr3_dfs_low_2_high()
852 reg = reg_read(CPU_PLL_CLOCK_DIVIDER_CNTRL0); in ddr3_dfs_low_2_high()
853 reg &= CPU_PLL_CLOCK_RELOAD_RATIO_MASK; in ddr3_dfs_low_2_high()
856 reg + (1 << CPU_PLL_CLOCK_RELOAD_RATIO_OFFS)); in ddr3_dfs_low_2_high()
861 reg = reg_read(CPU_PLL_CLOCK_DIVIDER_CNTRL0); in ddr3_dfs_low_2_high()
862 reg &= CPU_PLL_CLOCK_RELOAD_RATIO_MASK; in ddr3_dfs_low_2_high()
864 dfs_reg_write(CPU_PLL_CLOCK_DIVIDER_CNTRL0, reg); in ddr3_dfs_low_2_high()
874 reg = 0x0000FFFF; in ddr3_dfs_low_2_high()
877 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_low_2_high()
882 reg = 0x0000FF00; in ddr3_dfs_low_2_high()
884 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_1_ADDR, reg); in ddr3_dfs_low_2_high()
886 reg = reg_read(REG_CPU_DIV_CLK_CTRL_2_ADDR) & in ddr3_dfs_low_2_high()
888 reg |= (freq_par << REG_CPU_DIV_CLK_CTRL_3_FREQ_OFFS); in ddr3_dfs_low_2_high()
891 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_2_ADDR, reg); in ddr3_dfs_low_2_high()
898 reg = 0x000FFF02; in ddr3_dfs_low_2_high()
899 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_4_ADDR, reg); in ddr3_dfs_low_2_high()
904 reg = 0x0102FDFF; in ddr3_dfs_low_2_high()
915 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_low_2_high()
924 reg = reg_read(REG_CPU_DIV_CLK_STATUS_0_ADDR) & in ddr3_dfs_low_2_high()
926 } while (reg == 0); in ddr3_dfs_low_2_high()
928 reg = 0x000000FF; in ddr3_dfs_low_2_high()
934 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_low_2_high()
940 reg = reg_read(REG_DRAM_INIT_CTRL_STATUS_ADDR); in ddr3_dfs_low_2_high()
942 reg &= ~(1 << REG_DRAM_INIT_CTRL_TRN_CLK_OFFS); in ddr3_dfs_low_2_high()
944 dfs_reg_write(REG_DRAM_INIT_CTRL_STATUS_ADDR, reg); in ddr3_dfs_low_2_high()
956 reg = reg_read(REG_DDR_IO_ADDR) | in ddr3_dfs_low_2_high()
963 reg = reg_read(REG_DDR_IO_ADDR) & in ddr3_dfs_low_2_high()
966 dfs_reg_write(REG_DDR_IO_ADDR, reg); /* 0x1524 - DDR IO Register */ in ddr3_dfs_low_2_high()
969 reg = reg_read(REG_DUNIT_CTRL_LOW_ADDR); in ddr3_dfs_low_2_high()
971 reg &= ~(REG_DUNIT_CTRL_LOW_2T_MASK << REG_DUNIT_CTRL_LOW_2T_OFFS); in ddr3_dfs_low_2_high()
972 reg |= ((dram_info->mode_2t & REG_DUNIT_CTRL_LOW_2T_MASK) << in ddr3_dfs_low_2_high()
975 dfs_reg_write(REG_DUNIT_CTRL_LOW_ADDR, reg); in ddr3_dfs_low_2_high()
978 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_low_2_high()
979 reg &= ~(REG_DFS_CL_NEXT_STATE_MASK << REG_DFS_CL_NEXT_STATE_OFFS); in ddr3_dfs_low_2_high()
980 reg &= ~(REG_DFS_CWL_NEXT_STATE_MASK << REG_DFS_CWL_NEXT_STATE_OFFS); in ddr3_dfs_low_2_high()
992 reg |= ((tmp & REG_DFS_CL_NEXT_STATE_MASK) << REG_DFS_CL_NEXT_STATE_OFFS); in ddr3_dfs_low_2_high()
995 reg |= (((0) & REG_DFS_CWL_NEXT_STATE_MASK) << in ddr3_dfs_low_2_high()
999 reg |= (((dram_info->cwl) & REG_DFS_CWL_NEXT_STATE_MASK) << in ddr3_dfs_low_2_high()
1002 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1007 reg = reg_read(REG_DDR3_MR1_CS_ADDR + in ddr3_dfs_low_2_high()
1009 reg &= REG_DDR3_MR1_RTT_MASK; in ddr3_dfs_low_2_high()
1010 reg |= odt_static[dram_info->cs_ena][cs]; in ddr3_dfs_low_2_high()
1012 (cs << MR_CS_ADDR_OFFS), reg); in ddr3_dfs_low_2_high()
1017 reg = reg_read(REG_DRAM_PHY_CONFIG_ADDR) & REG_DRAM_PHY_CONFIG_MASK; in ddr3_dfs_low_2_high()
1020 dfs_reg_write(REG_DRAM_PHY_CONFIG_ADDR, reg); in ddr3_dfs_low_2_high()
1023 reg = reg_read(REG_DRAM_PHY_CONFIG_ADDR) | ~REG_DRAM_PHY_CONFIG_MASK; in ddr3_dfs_low_2_high()
1026 dfs_reg_write(REG_DRAM_PHY_CONFIG_ADDR, reg); in ddr3_dfs_low_2_high()
1030 reg = reg_read(REG_PHY_LOCK_STATUS_ADDR) & in ddr3_dfs_low_2_high()
1033 } while (reg != REG_PHY_LOCK_APLL_ADLL_STATUS_MASK); in ddr3_dfs_low_2_high()
1039 reg = reg_read(REG_SDRAM_CONFIG_ADDR) & in ddr3_dfs_low_2_high()
1045 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_low_2_high()
1053 reg = reg_read(REG_SDRAM_CONFIG_ADDR) & REG_SDRAM_CONFIG_MASK; in ddr3_dfs_low_2_high()
1056 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_low_2_high()
1062 reg = reg_read(REG_SDRAM_CONFIG_ADDR) | ~REG_SDRAM_CONFIG_MASK; in ddr3_dfs_low_2_high()
1065 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_low_2_high()
1073 reg = (0xA & REG_SDRAM_OPERATION_CWA_RC_MASK) << in ddr3_dfs_low_2_high()
1080 reg |= ((0x0 & REG_SDRAM_OPERATION_CWA_DATA_MASK) << in ddr3_dfs_low_2_high()
1087 reg |= ((0x1 & REG_SDRAM_OPERATION_CWA_DATA_MASK) << in ddr3_dfs_low_2_high()
1094 reg |= ((0x2 & REG_SDRAM_OPERATION_CWA_DATA_MASK) << in ddr3_dfs_low_2_high()
1101 reg |= ((0x3 & REG_SDRAM_OPERATION_CWA_DATA_MASK) << in ddr3_dfs_low_2_high()
1106 reg |= (0x1 << REG_SDRAM_OPERATION_CWA_DELAY_SEL_OFFS); in ddr3_dfs_low_2_high()
1108 reg |= (REG_SDRAM_OPERATION_CMD_CWA & in ddr3_dfs_low_2_high()
1112 dfs_reg_write(REG_SDRAM_OPERATION_ADDR, reg); in ddr3_dfs_low_2_high()
1116 reg = reg_read(REG_SDRAM_OPERATION_ADDR) & in ddr3_dfs_low_2_high()
1118 } while (reg); in ddr3_dfs_low_2_high()
1123 reg = reg_read(REG_DFS_ADDR) & ~(1 << REG_DFS_SR_OFFS); in ddr3_dfs_low_2_high()
1124 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1131 reg = reg_read(REG_DFS_ADDR) & (1 << REG_DFS_ATSR_OFFS); in ddr3_dfs_low_2_high()
1132 } while (reg); /* Wait for '0' */ in ddr3_dfs_low_2_high()
1136 reg = REG_SDRAM_OPERATION_CMD_RFRS; in ddr3_dfs_low_2_high()
1139 reg &= ~(1 << (REG_SDRAM_OPERATION_CS_OFFS + cs)); in ddr3_dfs_low_2_high()
1143 dfs_reg_write(REG_SDRAM_OPERATION_ADDR, reg); in ddr3_dfs_low_2_high()
1149 reg = reg_read(REG_DFS_ADDR); in ddr3_dfs_low_2_high()
1150 reg &= ~(1 << REG_DFS_BLOCK_OFFS); /* [1] - DfsBlock - Disable */ in ddr3_dfs_low_2_high()
1151 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1157 reg = reg_read(REG_METAL_MASK_ADDR); in ddr3_dfs_low_2_high()
1159 reg |= (1 << REG_METAL_MASK_RETRY_OFFS); in ddr3_dfs_low_2_high()
1161 dfs_reg_write(REG_METAL_MASK_ADDR, reg); in ddr3_dfs_low_2_high()
1166 reg = reg_read(REG_DDR3_MR0_CS_ADDR + in ddr3_dfs_low_2_high()
1173 reg |= ((tmp & 0x1) << REG_DDR3_MR0_CL_OFFS); in ddr3_dfs_low_2_high()
1174 reg |= ((tmp & 0xE) << REG_DDR3_MR0_CL_HIGH_OFFS); in ddr3_dfs_low_2_high()
1176 (cs << MR_CS_ADDR_OFFS), reg); in ddr3_dfs_low_2_high()
1179 reg = reg_read(REG_DDR3_MR2_CS_ADDR + in ddr3_dfs_low_2_high()
1183 reg |= ((0) << REG_DDR3_MR2_CWL_OFFS); in ddr3_dfs_low_2_high()
1185 reg |= ((dram_info->cwl) << REG_DDR3_MR2_CWL_OFFS); in ddr3_dfs_low_2_high()
1187 (cs << MR_CS_ADDR_OFFS), reg); in ddr3_dfs_low_2_high()
1200 u32 reg, freq_par, tmp; in ddr3_dfs_low_2_high()
1209 reg = 0x0000FF00; in ddr3_dfs_low_2_high()
1210 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_1_ADDR, reg); in ddr3_dfs_low_2_high()
1213 reg = reg_read(REG_ODPG_CNTRL_ADDR); in ddr3_dfs_low_2_high()
1214 reg |= (1 << REG_ODPG_CNTRL_OFFS); /* [21] = 1 */ in ddr3_dfs_low_2_high()
1215 dfs_reg_write(REG_ODPG_CNTRL_ADDR, reg); in ddr3_dfs_low_2_high()
1218 reg = reg_read(REG_PHY_LOCK_MASK_ADDR); in ddr3_dfs_low_2_high()
1219 reg &= REG_PHY_LOCK_MASK_MASK; /* [11:0] = 0 */ in ddr3_dfs_low_2_high()
1220 dfs_reg_write(REG_PHY_LOCK_MASK_ADDR, reg); in ddr3_dfs_low_2_high()
1223 reg = reg_read(REG_DFS_ADDR); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1225 reg &= ~0x11; in ddr3_dfs_low_2_high()
1227 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1231 reg = reg_read(REG_METAL_MASK_ADDR) & ~(1 << 0); in ddr3_dfs_low_2_high()
1233 dfs_reg_write(REG_METAL_MASK_ADDR, reg); in ddr3_dfs_low_2_high()
1237 reg = reg_read(REG_DFS_ADDR) | (1 << REG_DFS_BLOCK_OFFS); in ddr3_dfs_low_2_high()
1238 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1242 reg = reg_read(REG_DFS_ADDR) | (1 << REG_DFS_SR_OFFS); in ddr3_dfs_low_2_high()
1243 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1251 reg = reg_read(REG_DFS_ADDR) & (1 << REG_DFS_ATSR_OFFS); in ddr3_dfs_low_2_high()
1252 } while (reg == 0x0); /* Wait for '1' */ in ddr3_dfs_low_2_high()
1260 reg = reg_read(REG_DDR_IO_ADDR) | in ddr3_dfs_low_2_high()
1264 reg = reg_read(REG_DDR_IO_ADDR) & in ddr3_dfs_low_2_high()
1267 dfs_reg_write(REG_DDR_IO_ADDR, reg); /* 0x1524 - DDR IO Register */ in ddr3_dfs_low_2_high()
1270 reg = 0x20040000; in ddr3_dfs_low_2_high()
1277 dfs_reg_write(REG_DRAM_INIT_CTRL_STATUS_ADDR, reg); in ddr3_dfs_low_2_high()
1287 reg = 0x0000FFFF; in ddr3_dfs_low_2_high()
1289 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_low_2_high()
1294 reg = 0x0000FF00; in ddr3_dfs_low_2_high()
1296 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_1_ADDR, reg); in ddr3_dfs_low_2_high()
1298 reg = reg_read(REG_CPU_DIV_CLK_CTRL_3_ADDR) & in ddr3_dfs_low_2_high()
1300 reg |= (freq_par << REG_CPU_DIV_CLK_CTRL_3_FREQ_OFFS); in ddr3_dfs_low_2_high()
1303 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_3_ADDR, reg); in ddr3_dfs_low_2_high()
1311 reg = 0x000FFF02; in ddr3_dfs_low_2_high()
1313 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_4_ADDR, reg); in ddr3_dfs_low_2_high()
1318 reg = 0x0102FDFF; in ddr3_dfs_low_2_high()
1329 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_low_2_high()
1338 reg = reg_read(REG_CPU_DIV_CLK_STATUS_0_ADDR) & in ddr3_dfs_low_2_high()
1340 } while (reg == 0); in ddr3_dfs_low_2_high()
1342 reg = 0x000000FF; in ddr3_dfs_low_2_high()
1348 dfs_reg_write(REG_CPU_DIV_CLK_CTRL_0_ADDR, reg); in ddr3_dfs_low_2_high()
1355 reg = reg_read(REG_SDRAM_CONFIG_ADDR) & ~(1 << 28); in ddr3_dfs_low_2_high()
1359 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_low_2_high()
1367 reg = (reg_read(REG_DRAM_PHY_CONFIG_ADDR) & REG_DRAM_PHY_CONFIG_MASK); in ddr3_dfs_low_2_high()
1370 dfs_reg_write(REG_DRAM_PHY_CONFIG_ADDR, reg); in ddr3_dfs_low_2_high()
1376 reg = reg_read(REG_PHY_LOCK_STATUS_ADDR) & in ddr3_dfs_low_2_high()
1378 } while (reg == 0); in ddr3_dfs_low_2_high()
1381 reg = reg_read(REG_DRAM_PHY_CONFIG_ADDR) | ~REG_DRAM_PHY_CONFIG_MASK; in ddr3_dfs_low_2_high()
1384 dfs_reg_write(REG_DRAM_PHY_CONFIG_ADDR, reg); in ddr3_dfs_low_2_high()
1392 reg = reg_read(REG_PHY_LOCK_STATUS_ADDR) & in ddr3_dfs_low_2_high()
1394 } while (reg != REG_PHY_LOCK_STATUS_LOCK_MASK); in ddr3_dfs_low_2_high()
1397 reg = reg_read(REG_SDRAM_CONFIG_ADDR) & REG_SDRAM_CONFIG_MASK; in ddr3_dfs_low_2_high()
1400 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_low_2_high()
1403 reg = reg_read(REG_SDRAM_CONFIG_ADDR) | ~REG_SDRAM_CONFIG_MASK; in ddr3_dfs_low_2_high()
1406 dfs_reg_write(REG_SDRAM_CONFIG_ADDR, reg); in ddr3_dfs_low_2_high()
1409 reg = reg_read(REG_DFS_ADDR) & ~(1 << 4); in ddr3_dfs_low_2_high()
1410 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1413 reg = reg_read(REG_DFS_ADDR) & ~(1 << REG_DFS_SR_OFFS); in ddr3_dfs_low_2_high()
1414 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1421 reg = reg_read(REG_DFS_ADDR) & (1 << REG_DFS_ATSR_OFFS); in ddr3_dfs_low_2_high()
1422 } while (reg); /* Wait for '0' */ in ddr3_dfs_low_2_high()
1425 reg = (reg_read(REG_DUNIT_CTRL_LOW_ADDR) & 0xFFFFFFE7) | 0x2; in ddr3_dfs_low_2_high()
1429 reg &= ~(REG_DUNIT_CTRL_LOW_2T_MASK << REG_DUNIT_CTRL_LOW_2T_OFFS); in ddr3_dfs_low_2_high()
1430 reg |= ((dram_info->mode_2t & REG_DUNIT_CTRL_LOW_2T_MASK) << in ddr3_dfs_low_2_high()
1432 dfs_reg_write(REG_DUNIT_CTRL_LOW_ADDR, reg); in ddr3_dfs_low_2_high()
1438 reg = (reg_read(REG_DDR3_MR1_ADDR)); in ddr3_dfs_low_2_high()
1440 reg &= ~(1 << REG_DDR3_MR1_DLL_ENA_OFFS); in ddr3_dfs_low_2_high()
1441 dfs_reg_write(REG_DDR3_MR1_ADDR, reg); in ddr3_dfs_low_2_high()
1444 reg = REG_SDRAM_OPERATION_CMD_MR1 & in ddr3_dfs_low_2_high()
1451 dfs_reg_write(REG_SDRAM_OPERATION_ADDR, reg); in ddr3_dfs_low_2_high()
1457 reg = reg_read(REG_DDR3_MR0_ADDR); in ddr3_dfs_low_2_high()
1458 dfs_reg_write(REG_DDR3_MR0_ADDR, reg); in ddr3_dfs_low_2_high()
1461 reg = REG_SDRAM_OPERATION_CMD_MR0 & in ddr3_dfs_low_2_high()
1468 dfs_reg_write(REG_SDRAM_OPERATION_ADDR, reg); in ddr3_dfs_low_2_high()
1473 reg = reg_read(REG_DDR3_MR0_ADDR); in ddr3_dfs_low_2_high()
1474 reg &= ~0x74; /* CL [3:0]; [6:4],[2] */ in ddr3_dfs_low_2_high()
1481 reg |= ((tmp & 0x1) << 2); in ddr3_dfs_low_2_high()
1482 reg |= ((tmp >> 1) << 4); /* to bit 4 */ in ddr3_dfs_low_2_high()
1483 dfs_reg_write(REG_DDR3_MR0_ADDR, reg); in ddr3_dfs_low_2_high()
1485 reg = REG_SDRAM_OPERATION_CMD_MR0 & in ddr3_dfs_low_2_high()
1488 dfs_reg_write(REG_SDRAM_OPERATION_ADDR, reg); in ddr3_dfs_low_2_high()
1493 reg = reg_read(REG_DDR3_MR2_ADDR); in ddr3_dfs_low_2_high()
1494 reg &= ~0x38; /* CWL [5:3] */ in ddr3_dfs_low_2_high()
1497 reg |= dram_info->cwl << REG_DDR3_MR2_CWL_OFFS; in ddr3_dfs_low_2_high()
1498 dfs_reg_write(REG_DDR3_MR2_ADDR, reg); in ddr3_dfs_low_2_high()
1499 reg = REG_SDRAM_OPERATION_CMD_MR2 & in ddr3_dfs_low_2_high()
1502 dfs_reg_write(REG_SDRAM_OPERATION_ADDR, reg); in ddr3_dfs_low_2_high()
1508 reg = reg_read(REG_READ_DATA_SAMPLE_DELAYS_ADDR); in ddr3_dfs_low_2_high()
1509 reg &= ~(REG_READ_DATA_SAMPLE_DELAYS_MASK << in ddr3_dfs_low_2_high()
1511 reg |= (dram_info->cl << in ddr3_dfs_low_2_high()
1513 dfs_reg_write(REG_READ_DATA_SAMPLE_DELAYS_ADDR, reg); in ddr3_dfs_low_2_high()
1516 reg = reg_read(REG_READ_DATA_READY_DELAYS_ADDR); in ddr3_dfs_low_2_high()
1517 reg &= ~(REG_READ_DATA_READY_DELAYS_MASK << in ddr3_dfs_low_2_high()
1519 reg |= ((dram_info->cl + 1) << in ddr3_dfs_low_2_high()
1521 dfs_reg_write(REG_READ_DATA_READY_DELAYS_ADDR, reg); in ddr3_dfs_low_2_high()
1529 reg = reg_read(REG_DFS_ADDR) & ~(1 << REG_DFS_BLOCK_OFFS); in ddr3_dfs_low_2_high()
1530 dfs_reg_write(REG_DFS_ADDR, reg); /* 0x1528 - DFS register */ in ddr3_dfs_low_2_high()
1534 reg = reg_read(REG_ODPG_CNTRL_ADDR); in ddr3_dfs_low_2_high()
1535 reg &= ~(1 << REG_ODPG_CNTRL_OFFS); /* [21] = 0 */ in ddr3_dfs_low_2_high()
1536 dfs_reg_write(REG_ODPG_CNTRL_ADDR, reg); in ddr3_dfs_low_2_high()
1540 reg = reg_read(REG_PHY_LOCK_MASK_ADDR); in ddr3_dfs_low_2_high()
1541 reg |= ~REG_PHY_LOCK_MASK_MASK; /* [11:0] = FFF */ in ddr3_dfs_low_2_high()
1542 dfs_reg_write(REG_PHY_LOCK_MASK_ADDR, reg); in ddr3_dfs_low_2_high()
1544 reg = reg_read(REG_METAL_MASK_ADDR) | (1 << 0); /* [0] - disable */ in ddr3_dfs_low_2_high()
1546 dfs_reg_write(REG_METAL_MASK_ADDR, reg); in ddr3_dfs_low_2_high()