119 	union smi_x_wr_dat smix_wr_dat;  in octeontx_c45_addr()  local
122 	smix_wr_dat.u = 0;  in octeontx_c45_addr()
123 	smix_wr_dat.s.dat = regnum;  in octeontx_c45_addr()
125 	writeq(smix_wr_dat.u, priv->baseaddr + SMI_X_WR_DAT);  in octeontx_c45_addr()
135 		smix_wr_dat.u = readq(priv->baseaddr + SMI_X_WR_DAT);  in octeontx_c45_addr()
138 	} while (smix_wr_dat.s.pending && timeout);  in octeontx_c45_addr()
196 	union smi_x_wr_dat smix_wr_dat;  in octeontx_phy_write()  local
214 	smix_wr_dat.u = 0;  in octeontx_phy_write()
215 	smix_wr_dat.s.dat = value;  in octeontx_phy_write()
217 	writeq(smix_wr_dat.u, priv->baseaddr + SMI_X_WR_DAT);  in octeontx_phy_write()
233 		smix_wr_dat.u = readq(priv->baseaddr + SMI_X_WR_DAT);  in octeontx_phy_write()
236 	} while (smix_wr_dat.s.pending && timeout);  in octeontx_phy_write()
238 	debug("SMIX_WR_DAT: %lx\n", (unsigned long)smix_wr_dat.u);  in octeontx_phy_write()