Lines Matching defs:dest
133 void move32(Imm32 imm, Register dest) { in move32()
139 void move32(Imm32 imm, const Operand& dest) { movl(imm, dest); } in move32()
140 void move32(Register src, Register dest) { movl(src, dest); } in move32()
141 void move32(Register src, const Operand& dest) { movl(src, dest); } in move32()
182 void convertInt32ToDouble(Register src, FloatRegister dest) { in convertInt32ToDouble()
192 void convertInt32ToDouble(const Address& src, FloatRegister dest) { in convertInt32ToDouble()
195 void convertInt32ToDouble(const BaseIndex& src, FloatRegister dest) { in convertInt32ToDouble()
198 void convertInt32ToDouble(const Operand& src, FloatRegister dest) { in convertInt32ToDouble()
203 void convertInt32ToFloat32(Register src, FloatRegister dest) { in convertInt32ToFloat32()
208 void convertInt32ToFloat32(const Address& src, FloatRegister dest) { in convertInt32ToFloat32()
211 void convertInt32ToFloat32(const Operand& src, FloatRegister dest) { in convertInt32ToFloat32()
263 void load8ZeroExtend(const Operand& src, Register dest) { movzbl(src, dest); } in load8ZeroExtend()
264 void load8ZeroExtend(const Address& src, Register dest) { in load8ZeroExtend()
267 void load8ZeroExtend(const BaseIndex& src, Register dest) { in load8ZeroExtend()
270 void load8SignExtend(const Operand& src, Register dest) { movsbl(src, dest); } in load8SignExtend()
271 void load8SignExtend(const Address& src, Register dest) { in load8SignExtend()
274 void load8SignExtend(const BaseIndex& src, Register dest) { in load8SignExtend()
278 void store8(Imm32 src, const T& dest) { in store8()
282 void store8(Register src, const T& dest) { in store8()
286 void load16ZeroExtend(const Operand& src, Register dest) { in load16ZeroExtend()
289 void load16ZeroExtend(const Address& src, Register dest) { in load16ZeroExtend()
292 void load16ZeroExtend(const BaseIndex& src, Register dest) { in load16ZeroExtend()
296 void load16UnalignedZeroExtend(const S& src, Register dest) { in load16UnalignedZeroExtend()
300 void store16(const S& src, const T& dest) { in store16()
304 void store16Unaligned(const S& src, const T& dest) { in store16Unaligned()
307 void load16SignExtend(const Operand& src, Register dest) { in load16SignExtend()
310 void load16SignExtend(const Address& src, Register dest) { in load16SignExtend()
313 void load16SignExtend(const BaseIndex& src, Register dest) { in load16SignExtend()
317 void load16UnalignedSignExtend(const S& src, Register dest) { in load16UnalignedSignExtend()
320 void load32(const Address& address, Register dest) { in load32()
323 void load32(const BaseIndex& src, Register dest) { movl(Operand(src), dest); } in load32()
324 void load32(const Operand& src, Register dest) { movl(src, dest); } in load32()
326 void load32Unaligned(const S& src, Register dest) { in load32Unaligned()
330 void store32(const S& src, const T& dest) { in store32()
334 void store32_NoSecondScratch(const S& src, const T& dest) { in store32_NoSecondScratch()
338 void store32Unaligned(const S& src, const T& dest) { in store32Unaligned()
341 void loadDouble(const Address& src, FloatRegister dest) { vmovsd(src, dest); } in loadDouble()
342 void loadDouble(const BaseIndex& src, FloatRegister dest) { in loadDouble()
345 void loadDouble(const Operand& src, FloatRegister dest) { in loadDouble()
357 void moveDouble(FloatRegister src, FloatRegister dest) { in moveDouble()
363 void convertFloat32ToDouble(FloatRegister src, FloatRegister dest) { in convertFloat32ToDouble()
366 void convertDoubleToFloat32(FloatRegister src, FloatRegister dest) { in convertDoubleToFloat32()
370 void loadInt32x4(const Address& addr, FloatRegister dest) { in loadInt32x4()
373 void loadFloat32x4(const Address& addr, FloatRegister dest) { in loadFloat32x4()
383 void convertFloat32x4ToInt32x4(FloatRegister src, FloatRegister dest) { in convertFloat32x4ToInt32x4()
390 void convertInt32x4ToFloat32x4(FloatRegister src, FloatRegister dest) { in convertInt32x4ToFloat32x4()
548 void zeroSimd128Float(FloatRegister dest) { vxorps(dest, dest, dest); } in zeroSimd128Float()
549 void zeroSimd128Int(FloatRegister dest) { vpxor(dest, dest, dest); } in zeroSimd128Int()
560 void loadAlignedSimd128Int(const Address& src, FloatRegister dest) { in loadAlignedSimd128Int()
563 void loadAlignedSimd128Int(const Operand& src, FloatRegister dest) { in loadAlignedSimd128Int()
566 void storeAlignedSimd128Int(FloatRegister src, const Address& dest) { in storeAlignedSimd128Int()
569 void moveSimd128Int(FloatRegister src, FloatRegister dest) { in moveSimd128Int()
574 FloatRegister reusedInputInt32x4(FloatRegister src, FloatRegister dest) { in reusedInputInt32x4()
582 void loadUnalignedSimd128Int(const Address& src, FloatRegister dest) { in loadUnalignedSimd128Int()
585 void loadUnalignedSimd128Int(const BaseIndex& src, FloatRegister dest) { in loadUnalignedSimd128Int()
588 void loadUnalignedSimd128Int(const Operand& src, FloatRegister dest) { in loadUnalignedSimd128Int()
591 void storeUnalignedSimd128Int(FloatRegister src, const Address& dest) { in storeUnalignedSimd128Int()
594 void storeUnalignedSimd128Int(FloatRegister src, const BaseIndex& dest) { in storeUnalignedSimd128Int()
597 void storeUnalignedSimd128Int(FloatRegister src, const Operand& dest) { in storeUnalignedSimd128Int()
600 void packedLeftShiftByScalarInt16x8(Imm32 count, FloatRegister dest) { in packedLeftShiftByScalarInt16x8()
604 void packedRightShiftByScalarInt16x8(Imm32 count, FloatRegister dest) { in packedRightShiftByScalarInt16x8()
609 FloatRegister dest) { in packedUnsignedRightShiftByScalarInt16x8()
613 void packedLeftShiftByScalarInt32x4(Imm32 count, FloatRegister dest) { in packedLeftShiftByScalarInt32x4()
617 void packedRightShiftByScalarInt32x4(Imm32 count, FloatRegister dest) { in packedRightShiftByScalarInt32x4()
622 FloatRegister dest) { in packedUnsignedRightShiftByScalarInt32x4()
626 void loadAlignedSimd128Float(const Address& src, FloatRegister dest) { in loadAlignedSimd128Float()
629 void loadAlignedSimd128Float(const Operand& src, FloatRegister dest) { in loadAlignedSimd128Float()
632 void storeAlignedSimd128Float(FloatRegister src, const Address& dest) { in storeAlignedSimd128Float()
635 void moveSimd128Float(FloatRegister src, FloatRegister dest) { in moveSimd128Float()
640 FloatRegister reusedInputSimd128Float(FloatRegister src, FloatRegister dest) { in reusedInputSimd128Float()
648 void loadUnalignedSimd128(const Operand& src, FloatRegister dest) { in loadUnalignedSimd128()
651 void storeUnalignedSimd128(FloatRegister src, const Operand& dest) { in storeUnalignedSimd128()
663 void shuffleInt32(uint32_t mask, FloatRegister src, FloatRegister dest) { in shuffleInt32()
666 void moveLowInt32(FloatRegister src, Register dest) { vmovd(src, dest); } in moveLowInt32()
668 void moveHighPairToLowPairFloat32(FloatRegister src, FloatRegister dest) { in moveHighPairToLowPairFloat32()
671 void shuffleFloat32(uint32_t mask, FloatRegister src, FloatRegister dest) { in shuffleFloat32()
722 FloatRegister dest) { in bitwiseAndSimdInt()
726 FloatRegister dest) { in bitwiseOrSimdInt()
730 FloatRegister dest) { in bitwiseOrFloat32x4()
734 FloatRegister dest) { in bitwiseAndNotFloat32x4()
738 FloatRegister dest) { in reusedInputAlignedInt32x4()
746 void packedAddInt8(const Operand& src, FloatRegister dest) { in packedAddInt8()
749 void packedSubInt8(const Operand& src, FloatRegister dest) { in packedSubInt8()
752 void packedAddInt16(const Operand& src, FloatRegister dest) { in packedAddInt16()
755 void packedSubInt16(const Operand& src, FloatRegister dest) { in packedSubInt16()
758 void packedAddInt32(const Operand& src, FloatRegister dest) { in packedAddInt32()
761 void packedSubInt32(const Operand& src, FloatRegister dest) { in packedSubInt32()
764 void packedRcpApproximationFloat32x4(const Operand& src, FloatRegister dest) { in packedRcpApproximationFloat32x4()
771 FloatRegister dest) { in packedRcpSqrtApproximationFloat32x4()
776 FloatRegister dest) { in reusedInputAlignedSimd128Float()
784 void packedAddFloat32(const Operand& src, FloatRegister dest) { in packedAddFloat32()
787 void packedSubFloat32(const Operand& src, FloatRegister dest) { in packedSubFloat32()
790 void packedMulFloat32(const Operand& src, FloatRegister dest) { in packedMulFloat32()
793 void packedDivFloat32(const Operand& src, FloatRegister dest) { in packedDivFloat32()
796 void shuffleMix(uint32_t mask, const Operand& src, FloatRegister dest) { in shuffleMix()
805 void moveFloatAsDouble(Register src, FloatRegister dest) { in moveFloatAsDouble()
809 void loadFloatAsDouble(const Address& src, FloatRegister dest) { in loadFloatAsDouble()
813 void loadFloatAsDouble(const BaseIndex& src, FloatRegister dest) { in loadFloatAsDouble()
817 void loadFloatAsDouble(const Operand& src, FloatRegister dest) { in loadFloatAsDouble()
821 void loadFloat32(const Address& src, FloatRegister dest) { in loadFloat32()
824 void loadFloat32(const BaseIndex& src, FloatRegister dest) { in loadFloat32()
827 void loadFloat32(const Operand& src, FloatRegister dest) { in loadFloat32()
839 void moveFloat32(FloatRegister src, FloatRegister dest) { in moveFloat32()
880 void truncateDoubleToInt32(FloatRegister src, Register dest, Label* fail) { in truncateDoubleToInt32()
889 void truncateFloat32ToInt32(FloatRegister src, Register dest, Label* fail) { in truncateFloat32ToInt32()
898 bool maybeInlineDouble(double d, FloatRegister dest) { in maybeInlineDouble()
916 bool maybeInlineFloat(float f, FloatRegister dest) { in maybeInlineFloat()
925 bool maybeInlineSimd128Int(const SimdConstant& v, const FloatRegister& dest) { in maybeInlineSimd128Int()
937 const FloatRegister& dest) { in maybeInlineSimd128Float()
945 void convertBoolToInt32(Register source, Register dest) { in convertBoolToInt32()
988 void emitSetRegisterIfZero(Register dest) { in emitSetRegisterIfZero()
1011 void computeEffectiveAddress(const T& address, Register dest) { in computeEffectiveAddress()
1034 FloatRegister dest) { in loadAlignedVector()
1047 const Address& dest) { in storeAlignedVector()